/* $NoKeywords:$ */
/**
 * @file
 *
 *  Register definitions
 *
 *
 *
 * @xrefitem bom "File Content Label" "Release Content"
 * @e project:     AGESA
 * @e sub-project: GNB
 * @e \$Revision: 64732 $   @e \$Date: 2012-01-30 02:16:26 -0600 (Mon, 30 Jan 2012) $
 *
 */
/*
*****************************************************************************
*
 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
 *       its contributors may be used to endorse or promote products derived
 *       from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/

#ifndef _GNBREGISTERSTN_H_
#define _GNBREGISTERSTN_H_
#define  TYPE_D0F0                  0x1
#define  TYPE_D0F0x64               0x2
#define  TYPE_D0F0x98               0x3
#define  TYPE_D0F0xBC               0x4
#define  TYPE_D0F0xE4               0x5
#define  TYPE_DxF0                  0x6
#define  TYPE_DxF0xE4               0x7
#define  TYPE_D0F2                  0x8
#define  TYPE_D0F2xF4               0x9
#define  TYPE_D0F2xFC               0xa
#define  TYPE_D18F1                 0xb
#define  TYPE_D18F2                 0xc
#define  TYPE_D18F3                 0xd
#define  TYPE_D18F4                 0xe
#define  TYPE_D18F5                 0xf
#define  TYPE_MSR                   0x10
#define  TYPE_D1F0                  0x11
#define  TYPE_GMM                   0x12
#define  TYPE_D18F2x9C_dct0         0x13
#define  TYPE_D18F2x9C_dct0_mp0     0x14
#define  TYPE_D18F2x9C_dct0_mp1     0x15
#define  TYPE_D18F2x9C_dct1         0x16
#define  TYPE_D18F2x9C_dct1_mp0     0x17
#define  TYPE_D18F2x9C_dct1_mp1     0x18
#define  TYPE_D18F2_dct0            0x19
#define  TYPE_D18F2_dct1            0x1a
#define  TYPE_D18F2_dct0_mp0        0x1b
#define  TYPE_D18F2_dct0_mp1        0x1c
#define  TYPE_D1F1                  0x1d
#define  TYPE_D18F2_dct1_mp0        0x1e
#define  TYPE_D18F2_dct1_mp1        0x1f
#define  TYPE_CGIND                 0x20
#define  TYPE_SMU_MSG               0x21

#ifndef WRAP_SPACE
  #define  WRAP_SPACE(w, x)   (0x01300000 | (w << 16) | (x))
#endif
#ifndef CORE_SPACE
  #define  CORE_SPACE(c, x)   (0x00010000 | (c << 24) | (x))
#endif
#ifndef PHY_SPACE
  #define  PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x))
#endif
#ifndef PIF_SPACE
  #define  PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x))
#endif

#define  L1_SEL_GFX                         0
#define  L1_SEL_GPPSB                       1
#define  L1_SEL_GBIF                        2
#define  L1_SEL_INTGEN                      3

#define  SMU_MSG_TYPE                       TYPE_SMU_MSG
#define  SMC_MSG_FIRMWARE_AUTH              0
#define  SMC_MSG_HALT                       1
#define  SMC_MSG_PHY_LN_OFF                 2
#define  SMC_MSG_PHY_LN_ON                  3
#define  SMC_MSG_DDI_PHY_OFF                4
#define  SMC_MSG_DDI_PHY_ON                 5
#define  SMC_MSG_CASCADE_PLL_OFF            6
#define  SMC_MSG_CASCADE_PLL_ON             7
#define  SMC_MSG_PWR_OFF_x16                8
#define  SMC_MSG_CONFIG_LCLK_DPM            9
#define  SMC_MSG_FLUSH_DATA_CACHE           10
#define  SMC_MSG_FLUSH_INSTRUCTION_CACHE    11
#define  SMC_MSG_CONFIG_VPC_ACCUMULATOR     12
#define  SMC_MSG_CONFIG_BAPM                13
#define  SMC_MSG_CONFIG_TDC_LIMIT           14
#define  SMC_MSG_CONFIG_LPMx                15
#define  SMC_MSG_CONFIG_HTC_LIMIT           16
#define  SMC_MSG_CONFIG_THERMAL_CNTL        17
#define  SMC_MSG_CONFIG_VOLTAGE_CNTL        18
#define  SMC_MSG_CONFIG_TDP_CNTL            19
#define  SMC_MSG_EN_PM_CNTL                 20
#define  SMC_MSG_DIS_PM_CNTL                21
#define  SMC_MSG_CONFIG_NBDPM               22
#define  SMC_MSG_CONFIG_LOADLINE            23
#define  SMC_MSG_ADJUST_LOADLINE            24
#define  SMC_MSG_RECONFIGURE                25
#define  SMC_MSG_PCIE_PLLSWITCH             27
#define  SMC_MSG_ENABLE_BAPM                32
#define  SMC_MSG_DISABLE_BAPM               33

// **** D0F0x00 Register Definition ****
// Address
#define D0F0x00_ADDRESS                                         0x0

// Type
#define D0F0x00_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0x00_VendorID_OFFSET                                 0
#define D0F0x00_VendorID_WIDTH                                  16
#define D0F0x00_VendorID_MASK                                   0xffff
#define D0F0x00_DeviceID_OFFSET                                 16
#define D0F0x00_DeviceID_WIDTH                                  16
#define D0F0x00_DeviceID_MASK                                   0xffff0000

/// D0F0x00
typedef union {
  struct {                                                              ///<
    UINT32                                                 VendorID:16; ///<
    UINT32                                                 DeviceID:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x00_STRUCT;

// **** D0F0x04 Register Definition ****
// Address
#define D0F0x04_ADDRESS                                         0x4

// Type
#define D0F0x04_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0x04_IoAccessEn_OFFSET                               0
#define D0F0x04_IoAccessEn_WIDTH                                1
#define D0F0x04_IoAccessEn_MASK                                 0x1
#define D0F0x04_MemAccessEn_OFFSET                              1
#define D0F0x04_MemAccessEn_WIDTH                               1
#define D0F0x04_MemAccessEn_MASK                                0x2
#define D0F0x04_BusMasterEn_OFFSET                              2
#define D0F0x04_BusMasterEn_WIDTH                               1
#define D0F0x04_BusMasterEn_MASK                                0x4
#define D0F0x04_SpecialCycleEn_OFFSET                           3
#define D0F0x04_SpecialCycleEn_WIDTH                            1
#define D0F0x04_SpecialCycleEn_MASK                             0x8
#define D0F0x04_MemWriteInvalidateEn_OFFSET                     4
#define D0F0x04_MemWriteInvalidateEn_WIDTH                      1
#define D0F0x04_MemWriteInvalidateEn_MASK                       0x10
#define D0F0x04_PalSnoopEn_OFFSET                               5
#define D0F0x04_PalSnoopEn_WIDTH                                1
#define D0F0x04_PalSnoopEn_MASK                                 0x20
#define D0F0x04_ParityErrorEn_OFFSET                            6
#define D0F0x04_ParityErrorEn_WIDTH                             1
#define D0F0x04_ParityErrorEn_MASK                              0x40
#define D0F0x04_Reserved_7_7_OFFSET                             7
#define D0F0x04_Reserved_7_7_WIDTH                              1
#define D0F0x04_Reserved_7_7_MASK                               0x80
#define D0F0x04_SerrEn_OFFSET                                   8
#define D0F0x04_SerrEn_WIDTH                                    1
#define D0F0x04_SerrEn_MASK                                     0x100
#define D0F0x04_FastB2BEn_OFFSET                                9
#define D0F0x04_FastB2BEn_WIDTH                                 1
#define D0F0x04_FastB2BEn_MASK                                  0x200
#define D0F0x04_Reserved_19_10_OFFSET                           10
#define D0F0x04_Reserved_19_10_WIDTH                            10
#define D0F0x04_Reserved_19_10_MASK                             0xffc00
#define D0F0x04_CapList_OFFSET                                  20
#define D0F0x04_CapList_WIDTH                                   1
#define D0F0x04_CapList_MASK                                    0x100000
#define D0F0x04_PCI66En_OFFSET                                  21
#define D0F0x04_PCI66En_WIDTH                                   1
#define D0F0x04_PCI66En_MASK                                    0x200000
#define D0F0x04_Reserved_22_22_OFFSET                           22
#define D0F0x04_Reserved_22_22_WIDTH                            1
#define D0F0x04_Reserved_22_22_MASK                             0x400000
#define D0F0x04_FastBackCapable_OFFSET                          23
#define D0F0x04_FastBackCapable_WIDTH                           1
#define D0F0x04_FastBackCapable_MASK                            0x800000
#define D0F0x04_Reserved_24_24_OFFSET                           24
#define D0F0x04_Reserved_24_24_WIDTH                            1
#define D0F0x04_Reserved_24_24_MASK                             0x1000000
#define D0F0x04_DevselTiming_OFFSET                             25
#define D0F0x04_DevselTiming_WIDTH                              2
#define D0F0x04_DevselTiming_MASK                               0x6000000
#define D0F0x04_SignalTargetAbort_OFFSET                        27
#define D0F0x04_SignalTargetAbort_WIDTH                         1
#define D0F0x04_SignalTargetAbort_MASK                          0x8000000
#define D0F0x04_ReceivedTargetAbort_OFFSET                      28
#define D0F0x04_ReceivedTargetAbort_WIDTH                       1
#define D0F0x04_ReceivedTargetAbort_MASK                        0x10000000
#define D0F0x04_ReceivedMasterAbort_OFFSET                      29
#define D0F0x04_ReceivedMasterAbort_WIDTH                       1
#define D0F0x04_ReceivedMasterAbort_MASK                        0x20000000
#define D0F0x04_SignaledSystemError_OFFSET                      30
#define D0F0x04_SignaledSystemError_WIDTH                       1
#define D0F0x04_SignaledSystemError_MASK                        0x40000000
#define D0F0x04_ParityErrorDetected_OFFSET                      31
#define D0F0x04_ParityErrorDetected_WIDTH                       1
#define D0F0x04_ParityErrorDetected_MASK                        0x80000000

/// D0F0x04
typedef union {
  struct {                                                              ///<
    UINT32                                               IoAccessEn:1 ; ///<
    UINT32                                              MemAccessEn:1 ; ///<
    UINT32                                              BusMasterEn:1 ; ///<
    UINT32                                           SpecialCycleEn:1 ; ///<
    UINT32                                     MemWriteInvalidateEn:1 ; ///<
    UINT32                                               PalSnoopEn:1 ; ///<
    UINT32                                            ParityErrorEn:1 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                                   SerrEn:1 ; ///<
    UINT32                                                FastB2BEn:1 ; ///<
    UINT32                                           Reserved_19_10:10; ///<
    UINT32                                                  CapList:1 ; ///<
    UINT32                                                  PCI66En:1 ; ///<
    UINT32                                           Reserved_22_22:1 ; ///<
    UINT32                                          FastBackCapable:1 ; ///<
    UINT32                                           Reserved_24_24:1 ; ///<
    UINT32                                             DevselTiming:2 ; ///<
    UINT32                                        SignalTargetAbort:1 ; ///<
    UINT32                                      ReceivedTargetAbort:1 ; ///<
    UINT32                                      ReceivedMasterAbort:1 ; ///<
    UINT32                                      SignaledSystemError:1 ; ///<
    UINT32                                      ParityErrorDetected:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x04_STRUCT;

// **** D0F0x08 Register Definition ****
// Address
#define D0F0x08_ADDRESS                                         0x8

// Type
#define D0F0x08_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0x08_RevID_OFFSET                                    0
#define D0F0x08_RevID_WIDTH                                     8
#define D0F0x08_RevID_MASK                                      0xff
#define D0F0x08_ClassCode_OFFSET                                8
#define D0F0x08_ClassCode_WIDTH                                 24
#define D0F0x08_ClassCode_MASK                                  0xffffff00

/// D0F0x08
typedef union {
  struct {                                                              ///<
    UINT32                                                    RevID:8 ; ///<
    UINT32                                                ClassCode:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x08_STRUCT;

// **** D0F0x0C Register Definition ****
// Address
#define D0F0x0C_ADDRESS                                         0xc

// Type
#define D0F0x0C_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0x0C_CacheLineSize_OFFSET                            0
#define D0F0x0C_CacheLineSize_WIDTH                             8
#define D0F0x0C_CacheLineSize_MASK                              0xff
#define D0F0x0C_LatencyTimer_OFFSET                             8
#define D0F0x0C_LatencyTimer_WIDTH                              8
#define D0F0x0C_LatencyTimer_MASK                               0xff00
#define D0F0x0C_HeaderTypeReg_OFFSET                            16
#define D0F0x0C_HeaderTypeReg_WIDTH                             8
#define D0F0x0C_HeaderTypeReg_MASK                              0xff0000
#define D0F0x0C_BIST_OFFSET                                     24
#define D0F0x0C_BIST_WIDTH                                      8
#define D0F0x0C_BIST_MASK                                       0xff000000

/// D0F0x0C
typedef union {
  struct {                                                              ///<
    UINT32                                            CacheLineSize:8 ; ///<
    UINT32                                             LatencyTimer:8 ; ///<
    UINT32                                            HeaderTypeReg:8 ; ///<
    UINT32                                                     BIST:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x0C_STRUCT;

// **** D0F0x2C Register Definition ****
// Address
#define D0F0x2C_ADDRESS                                         0x2c

// Type
#define D0F0x2C_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0x2C_SubsystemVendorID_OFFSET                        0
#define D0F0x2C_SubsystemVendorID_WIDTH                         16
#define D0F0x2C_SubsystemVendorID_MASK                          0xffff
#define D0F0x2C_SubsystemID_OFFSET                              16
#define D0F0x2C_SubsystemID_WIDTH                               16
#define D0F0x2C_SubsystemID_MASK                                0xffff0000

/// D0F0x2C
typedef union {
  struct {                                                              ///<
    UINT32                                        SubsystemVendorID:16; ///<
    UINT32                                              SubsystemID:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x2C_STRUCT;

// **** D0F0x34 Register Definition ****
// Address
#define D0F0x34_ADDRESS                                         0x34

// Type
#define D0F0x34_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0x34_CapPtr_OFFSET                                   0
#define D0F0x34_CapPtr_WIDTH                                    8
#define D0F0x34_CapPtr_MASK                                     0xff
#define D0F0x34_Reserved_31_8_OFFSET                            8
#define D0F0x34_Reserved_31_8_WIDTH                             24
#define D0F0x34_Reserved_31_8_MASK                              0xffffff00

/// D0F0x34
typedef union {
  struct {                                                              ///<
    UINT32                                                   CapPtr:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x34_STRUCT;

// **** D0F0x4C Register Definition ****
// Address
#define D0F0x4C_ADDRESS                                         0x4c

// Type
#define D0F0x4C_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0x4C_Function1Enable_OFFSET                          0
#define D0F0x4C_Function1Enable_WIDTH                           1
#define D0F0x4C_Function1Enable_MASK                            0x1
#define D0F0x4C_ApicEnable_OFFSET                               1
#define D0F0x4C_ApicEnable_WIDTH                                1
#define D0F0x4C_ApicEnable_MASK                                 0x2
#define D0F0x4C_Reserved_2_2_OFFSET                             2
#define D0F0x4C_Reserved_2_2_WIDTH                              1
#define D0F0x4C_Reserved_2_2_MASK                               0x4
#define D0F0x4C_Cf8Dis_OFFSET                                   3
#define D0F0x4C_Cf8Dis_WIDTH                                    1
#define D0F0x4C_Cf8Dis_MASK                                     0x8
#define D0F0x4C_PMEDis_OFFSET                                   4
#define D0F0x4C_PMEDis_WIDTH                                    1
#define D0F0x4C_PMEDis_MASK                                     0x10
#define D0F0x4C_SerrDis_OFFSET                                  5
#define D0F0x4C_SerrDis_WIDTH                                   1
#define D0F0x4C_SerrDis_MASK                                    0x20
#define D0F0x4C_Reserved_10_6_OFFSET                            6
#define D0F0x4C_Reserved_10_6_WIDTH                             5
#define D0F0x4C_Reserved_10_6_MASK                              0x7c0
#define D0F0x4C_CRS_OFFSET                                      11
#define D0F0x4C_CRS_WIDTH                                       1
#define D0F0x4C_CRS_MASK                                        0x800
#define D0F0x4C_CfgRdTime_OFFSET                                12
#define D0F0x4C_CfgRdTime_WIDTH                                 3
#define D0F0x4C_CfgRdTime_MASK                                  0x7000
#define D0F0x4C_Reserved_22_15_OFFSET                           15
#define D0F0x4C_Reserved_22_15_WIDTH                            8
#define D0F0x4C_Reserved_22_15_MASK                             0x7f8000
#define D0F0x4C_MMIOEnable_OFFSET                               23
#define D0F0x4C_MMIOEnable_WIDTH                                1
#define D0F0x4C_MMIOEnable_MASK                                 0x800000
#define D0F0x4C_Reserved_25_24_OFFSET                           24
#define D0F0x4C_Reserved_25_24_WIDTH                            2
#define D0F0x4C_Reserved_25_24_MASK                             0x3000000
#define D0F0x4C_HPDis_OFFSET                                    26
#define D0F0x4C_HPDis_WIDTH                                     1
#define D0F0x4C_HPDis_MASK                                      0x4000000
#define D0F0x4C_Reserved_31_27_OFFSET                           27
#define D0F0x4C_Reserved_31_27_WIDTH                            5
#define D0F0x4C_Reserved_31_27_MASK                             0xf8000000

/// D0F0x4C
typedef union {
  struct {                                                              ///<
    UINT32                                          Function1Enable:1 ; ///<
    UINT32                                               ApicEnable:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                                   Cf8Dis:1 ; ///<
    UINT32                                                   PMEDis:1 ; ///<
    UINT32                                                  SerrDis:1 ; ///<
    UINT32                                            Reserved_10_6:5 ; ///<
    UINT32                                                      CRS:1 ; ///<
    UINT32                                                CfgRdTime:3 ; ///<
    UINT32                                           Reserved_22_15:8 ; ///<
    UINT32                                               MMIOEnable:1 ; ///<
    UINT32                                           Reserved_25_24:2 ; ///<
    UINT32                                                    HPDis:1 ; ///<
    UINT32                                           Reserved_31_27:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x4C_STRUCT;

// **** D0F0x60 Register Definition ****
// Address
#define D0F0x60_ADDRESS                                         0x60

// Type
#define D0F0x60_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0x60_MiscIndAddr_OFFSET                              0
#define D0F0x60_MiscIndAddr_WIDTH                               7
#define D0F0x60_MiscIndAddr_MASK                                0x7f
#define D0F0x60_MiscIndWrEn_OFFSET                              7
#define D0F0x60_MiscIndWrEn_WIDTH                               1
#define D0F0x60_MiscIndWrEn_MASK                                0x80
#define D0F0x60_Reserved_31_8_OFFSET                            8
#define D0F0x60_Reserved_31_8_WIDTH                             24
#define D0F0x60_Reserved_31_8_MASK                              0xffffff00

/// D0F0x60
typedef union {
  struct {                                                              ///<
    UINT32                                              MiscIndAddr:7 ; ///<
    UINT32                                              MiscIndWrEn:1 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x60_STRUCT;

// **** D0F0x64 Register Definition ****
// Address
#define D0F0x64_ADDRESS                                         0x64

// Type
#define D0F0x64_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0x64_MiscIndData_OFFSET                              0
#define D0F0x64_MiscIndData_WIDTH                               32
#define D0F0x64_MiscIndData_MASK                                0xffffffff

/// D0F0x64
typedef union {
  struct {                                                              ///<
    UINT32                                              MiscIndData:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_STRUCT;

// **** D0F0x7C Register Definition ****
// Address
#define D0F0x7C_ADDRESS                                         0x7c

// Type
#define D0F0x7C_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0x7C_ForceIntGFXDisable_OFFSET                       0
#define D0F0x7C_ForceIntGFXDisable_WIDTH                        1
#define D0F0x7C_ForceIntGFXDisable_MASK                         0x1
#define D0F0x7C_Reserved_31_1_OFFSET                            1
#define D0F0x7C_Reserved_31_1_WIDTH                             31
#define D0F0x7C_Reserved_31_1_MASK                              0xfffffffe

/// D0F0x7C
typedef union {
  struct {                                                              ///<
    UINT32                                       ForceIntGFXDisable:1 ; ///<
    UINT32                                            Reserved_31_1:31; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x7C_STRUCT;

// **** D0F0x84 Register Definition ****
// Address
#define D0F0x84_ADDRESS                                         0x84

// Type
#define D0F0x84_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0x84_Reserved_2_0_OFFSET                             0
#define D0F0x84_Reserved_2_0_WIDTH                              3
#define D0F0x84_Reserved_2_0_MASK                               0x7
#define D0F0x84_VgaHole_OFFSET                                  3
#define D0F0x84_VgaHole_WIDTH                                   1
#define D0F0x84_VgaHole_MASK                                    0x8
#define D0F0x84_Ev6Mode_OFFSET                                  4
#define D0F0x84_Ev6Mode_WIDTH                                   1
#define D0F0x84_Ev6Mode_MASK                                    0x10
#define D0F0x84_Reserved_7_5_OFFSET                             5
#define D0F0x84_Reserved_7_5_WIDTH                              3
#define D0F0x84_Reserved_7_5_MASK                               0xe0
#define D0F0x84_PmeMode_OFFSET                                  8
#define D0F0x84_PmeMode_WIDTH                                   1
#define D0F0x84_PmeMode_MASK                                    0x100
#define D0F0x84_PmeTurnOff_OFFSET                               9
#define D0F0x84_PmeTurnOff_WIDTH                                1
#define D0F0x84_PmeTurnOff_MASK                                 0x200
#define D0F0x84_Reserved_31_10_OFFSET                           10
#define D0F0x84_Reserved_31_10_WIDTH                            22
#define D0F0x84_Reserved_31_10_MASK                             0xfffffc00

/// D0F0x84
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_2_0:3 ; ///<
    UINT32                                                  VgaHole:1 ; ///<
    UINT32                                                  Ev6Mode:1 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                                  PmeMode:1 ; ///<
    UINT32                                               PmeTurnOff:1 ; ///<
    UINT32                                           Reserved_31_10:22; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x84_STRUCT;

// **** D0F0x90 Register Definition ****
// Address
#define D0F0x90_ADDRESS                                         0x90

// Type
#define D0F0x90_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0x90_Reserved_22_0_OFFSET                            0
#define D0F0x90_Reserved_22_0_WIDTH                             23
#define D0F0x90_Reserved_22_0_MASK                              0x7fffff
#define D0F0x90_TopOfDram_OFFSET                                23
#define D0F0x90_TopOfDram_WIDTH                                 9
#define D0F0x90_TopOfDram_MASK                                  0xff800000

/// D0F0x90
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_22_0:23; ///<
    UINT32                                                TopOfDram:9 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x90_STRUCT;

// **** D0F0x94 Register Definition ****
// Address
#define D0F0x94_ADDRESS                                         0x94

// Type
#define D0F0x94_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0x94_OrbIndAddr_OFFSET                               0
#define D0F0x94_OrbIndAddr_WIDTH                                7
#define D0F0x94_OrbIndAddr_MASK                                 0x7f
#define D0F0x94_Reserved_7_7_OFFSET                             7
#define D0F0x94_Reserved_7_7_WIDTH                              1
#define D0F0x94_Reserved_7_7_MASK                               0x80
#define D0F0x94_OrbIndWrEn_OFFSET                               8
#define D0F0x94_OrbIndWrEn_WIDTH                                1
#define D0F0x94_OrbIndWrEn_MASK                                 0x100
#define D0F0x94_Reserved_31_9_OFFSET                            9
#define D0F0x94_Reserved_31_9_WIDTH                             23
#define D0F0x94_Reserved_31_9_MASK                              0xfffffe00

/// D0F0x94
typedef union {
  struct {                                                              ///<
    UINT32                                               OrbIndAddr:7 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                               OrbIndWrEn:1 ; ///<
    UINT32                                            Reserved_31_9:23; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x94_STRUCT;

// **** D0F0x98 Register Definition ****
// Address
#define D0F0x98_ADDRESS                                         0x98

// Type
#define D0F0x98_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0x98_OrbIndData_OFFSET                               0
#define D0F0x98_OrbIndData_WIDTH                                32
#define D0F0x98_OrbIndData_MASK                                 0xffffffff

/// D0F0x98
typedef union {
  struct {                                                              ///<
    UINT32                                               OrbIndData:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x98_STRUCT;

// **** D0F0xB8 Register Definition ****
// Address
#define D0F0xB8_ADDRESS                                         0xb8

// Type
#define D0F0xB8_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0xB8_NbSmuIndAddr_OFFSET                             0
#define D0F0xB8_NbSmuIndAddr_WIDTH                              32
#define D0F0xB8_NbSmuIndAddr_MASK                               0xffffffff

/// D0F0xB8
typedef union {
  struct {                                                              ///<
    UINT32                                             NbSmuIndAddr:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xB8_STRUCT;

// **** D0F0xBC Register Definition ****
// Address
#define D0F0xBC_ADDRESS                                         0xbc

// Type
#define D0F0xBC_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0xBC_NbSmuIndData_OFFSET                             0
#define D0F0xBC_NbSmuIndData_WIDTH                              32
#define D0F0xBC_NbSmuIndData_MASK                               0xffffffff

/// D0F0xBC
typedef union {
  struct {                                                              ///<
    UINT32                                             NbSmuIndData:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_STRUCT;

// **** D0F0xE0 Register Definition ****
// Address
#define D0F0xE0_ADDRESS                                         0xe0

// Type
#define D0F0xE0_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0xE0_PcieIndxAddr_OFFSET                             0
#define D0F0xE0_PcieIndxAddr_WIDTH                              16
#define D0F0xE0_PcieIndxAddr_MASK                               0xffff
#define D0F0xE0_FrameType_OFFSET                                16
#define D0F0xE0_FrameType_WIDTH                                 8
#define D0F0xE0_FrameType_MASK                                  0xff0000
#define D0F0xE0_BlockSelect_OFFSET                              24
#define D0F0xE0_BlockSelect_WIDTH                               8
#define D0F0xE0_BlockSelect_MASK                                0xff000000

/// D0F0xE0
typedef union {
  struct {                                                              ///<
    UINT32                                             PcieIndxAddr:16; ///<
    UINT32                                                FrameType:8 ; ///<
    UINT32                                              BlockSelect:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE0_STRUCT;

// **** D0F0xE4 Register Definition ****
// Address
#define D0F0xE4_ADDRESS                                         0xe4

// Type
#define D0F0xE4_TYPE                                            TYPE_D0F0
// Field Data
#define D0F0xE4_PcieIndxData_OFFSET                             0
#define D0F0xE4_PcieIndxData_WIDTH                              32
#define D0F0xE4_PcieIndxData_MASK                               0xffffffff

/// D0F0xE4
typedef union {
  struct {                                                              ///<
    UINT32                                             PcieIndxData:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_STRUCT;

// **** D0F2x00 Register Definition ****
// Address
#define D0F2x00_ADDRESS                                         0x0

// Type
#define D0F2x00_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x00_VendorId_OFFSET                                 0
#define D0F2x00_VendorId_WIDTH                                  16
#define D0F2x00_VendorId_MASK                                   0xffff
#define D0F2x00_DeviceId_OFFSET                                 16
#define D0F2x00_DeviceId_WIDTH                                  16
#define D0F2x00_DeviceId_MASK                                   0xffff0000

/// D0F2x00
typedef union {
  struct {                                                              ///<
    UINT32                                                 VendorId:16; ///<
    UINT32                                                 DeviceId:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x00_STRUCT;

// **** D0F2x04 Register Definition ****
// Address
#define D0F2x04_ADDRESS                                         0x4

// Type
#define D0F2x04_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x04_IoAccessEn_OFFSET                               0
#define D0F2x04_IoAccessEn_WIDTH                                1
#define D0F2x04_IoAccessEn_MASK                                 0x1
#define D0F2x04_MemAccessEn_OFFSET                              1
#define D0F2x04_MemAccessEn_WIDTH                               1
#define D0F2x04_MemAccessEn_MASK                                0x2
#define D0F2x04_BusMasterEn_OFFSET                              2
#define D0F2x04_BusMasterEn_WIDTH                               1
#define D0F2x04_BusMasterEn_MASK                                0x4
#define D0F2x04_Reserved_5_3_OFFSET                             3
#define D0F2x04_Reserved_5_3_WIDTH                              3
#define D0F2x04_Reserved_5_3_MASK                               0x38
#define D0F2x04_ParityErrorEn_OFFSET                            6
#define D0F2x04_ParityErrorEn_WIDTH                             1
#define D0F2x04_ParityErrorEn_MASK                              0x40
#define D0F2x04_Reserved_7_7_OFFSET                             7
#define D0F2x04_Reserved_7_7_WIDTH                              1
#define D0F2x04_Reserved_7_7_MASK                               0x80
#define D0F2x04_SerrEn_OFFSET                                   8
#define D0F2x04_SerrEn_WIDTH                                    1
#define D0F2x04_SerrEn_MASK                                     0x100
#define D0F2x04_Reserved_9_9_OFFSET                             9
#define D0F2x04_Reserved_9_9_WIDTH                              1
#define D0F2x04_Reserved_9_9_MASK                               0x200
#define D0F2x04_InterruptDis_OFFSET                             10
#define D0F2x04_InterruptDis_WIDTH                              1
#define D0F2x04_InterruptDis_MASK                               0x400
#define D0F2x04_Reserved_18_11_OFFSET                           11
#define D0F2x04_Reserved_18_11_WIDTH                            8
#define D0F2x04_Reserved_18_11_MASK                             0x7f800
#define D0F2x04_IntStatus_OFFSET                                19
#define D0F2x04_IntStatus_WIDTH                                 1
#define D0F2x04_IntStatus_MASK                                  0x80000
#define D0F2x04_CapList_OFFSET                                  20
#define D0F2x04_CapList_WIDTH                                   1
#define D0F2x04_CapList_MASK                                    0x100000
#define D0F2x04_Reserved_23_21_OFFSET                           21
#define D0F2x04_Reserved_23_21_WIDTH                            3
#define D0F2x04_Reserved_23_21_MASK                             0xe00000
#define D0F2x04_MasterDataError_OFFSET                          24
#define D0F2x04_MasterDataError_WIDTH                           1
#define D0F2x04_MasterDataError_MASK                            0x1000000
#define D0F2x04_Reserved_26_25_OFFSET                           25
#define D0F2x04_Reserved_26_25_WIDTH                            2
#define D0F2x04_Reserved_26_25_MASK                             0x6000000
#define D0F2x04_SignalTargetAbort_OFFSET                        27
#define D0F2x04_SignalTargetAbort_WIDTH                         1
#define D0F2x04_SignalTargetAbort_MASK                          0x8000000
#define D0F2x04_ReceivedTargetAbort_OFFSET                      28
#define D0F2x04_ReceivedTargetAbort_WIDTH                       1
#define D0F2x04_ReceivedTargetAbort_MASK                        0x10000000
#define D0F2x04_ReceivedMasterAbort_OFFSET                      29
#define D0F2x04_ReceivedMasterAbort_WIDTH                       1
#define D0F2x04_ReceivedMasterAbort_MASK                        0x20000000
#define D0F2x04_SignaledSystemError_OFFSET                      30
#define D0F2x04_SignaledSystemError_WIDTH                       1
#define D0F2x04_SignaledSystemError_MASK                        0x40000000
#define D0F2x04_ParityErrorDetected_OFFSET                      31
#define D0F2x04_ParityErrorDetected_WIDTH                       1
#define D0F2x04_ParityErrorDetected_MASK                        0x80000000

/// D0F2x04
typedef union {
  struct {                                                              ///<
    UINT32                                               IoAccessEn:1 ; ///<
    UINT32                                              MemAccessEn:1 ; ///<
    UINT32                                              BusMasterEn:1 ; ///<
    UINT32                                             Reserved_5_3:3 ; ///<
    UINT32                                            ParityErrorEn:1 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                                   SerrEn:1 ; ///<
    UINT32                                             Reserved_9_9:1 ; ///<
    UINT32                                             InterruptDis:1 ; ///<
    UINT32                                           Reserved_18_11:8 ; ///<
    UINT32                                                IntStatus:1 ; ///<
    UINT32                                                  CapList:1 ; ///<
    UINT32                                           Reserved_23_21:3 ; ///<
    UINT32                                          MasterDataError:1 ; ///<
    UINT32                                           Reserved_26_25:2 ; ///<
    UINT32                                        SignalTargetAbort:1 ; ///<
    UINT32                                      ReceivedTargetAbort:1 ; ///<
    UINT32                                      ReceivedMasterAbort:1 ; ///<
    UINT32                                      SignaledSystemError:1 ; ///<
    UINT32                                      ParityErrorDetected:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x04_STRUCT;

// **** D0F2x08 Register Definition ****
// Address
#define D0F2x08_ADDRESS                                         0x8

// Type
#define D0F2x08_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x08_RevID_OFFSET                                    0
#define D0F2x08_RevID_WIDTH                                     8
#define D0F2x08_RevID_MASK                                      0xff
#define D0F2x08_ClassCode_OFFSET                                8
#define D0F2x08_ClassCode_WIDTH                                 24
#define D0F2x08_ClassCode_MASK                                  0xffffff00

/// D0F2x08
typedef union {
  struct {                                                              ///<
    UINT32                                                    RevID:8 ; ///<
    UINT32                                                ClassCode:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x08_STRUCT;

// **** D0F2x0C Register Definition ****
// Address
#define D0F2x0C_ADDRESS                                         0xc

// Type
#define D0F2x0C_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x0C_CacheLineSize_OFFSET                            0
#define D0F2x0C_CacheLineSize_WIDTH                             8
#define D0F2x0C_CacheLineSize_MASK                              0xff
#define D0F2x0C_LatencyTimer_OFFSET                             8
#define D0F2x0C_LatencyTimer_WIDTH                              8
#define D0F2x0C_LatencyTimer_MASK                               0xff00
#define D0F2x0C_HeaderTypeReg_OFFSET                            16
#define D0F2x0C_HeaderTypeReg_WIDTH                             8
#define D0F2x0C_HeaderTypeReg_MASK                              0xff0000
#define D0F2x0C_BIST_OFFSET                                     24
#define D0F2x0C_BIST_WIDTH                                      8
#define D0F2x0C_BIST_MASK                                       0xff000000

/// D0F2x0C
typedef union {
  struct {                                                              ///<
    UINT32                                            CacheLineSize:8 ; ///<
    UINT32                                             LatencyTimer:8 ; ///<
    UINT32                                            HeaderTypeReg:8 ; ///<
    UINT32                                                     BIST:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x0C_STRUCT;

// **** D0F2x2C Register Definition ****
// Address
#define D0F2x2C_ADDRESS                                         0x2c

// Type
#define D0F2x2C_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x2C_SubsystemVendorId_OFFSET                        0
#define D0F2x2C_SubsystemVendorId_WIDTH                         16
#define D0F2x2C_SubsystemVendorId_MASK                          0xffff
#define D0F2x2C_SubsystemId_OFFSET                              16
#define D0F2x2C_SubsystemId_WIDTH                               16
#define D0F2x2C_SubsystemId_MASK                                0xffff0000

/// D0F2x2C
typedef union {
  struct {                                                              ///<
    UINT32                                        SubsystemVendorId:16; ///<
    UINT32                                              SubsystemId:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x2C_STRUCT;

// **** D0F2x34 Register Definition ****
// Address
#define D0F2x34_ADDRESS                                         0x34

// Type
#define D0F2x34_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x34_CapPtr_OFFSET                                   0
#define D0F2x34_CapPtr_WIDTH                                    8
#define D0F2x34_CapPtr_MASK                                     0xff
#define D0F2x34_Reserved_31_8_OFFSET                            8
#define D0F2x34_Reserved_31_8_WIDTH                             24
#define D0F2x34_Reserved_31_8_MASK                              0xffffff00

/// D0F2x34
typedef union {
  struct {                                                              ///<
    UINT32                                                   CapPtr:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x34_STRUCT;

// **** D0F2x3C Register Definition ****
// Address
#define D0F2x3C_ADDRESS                                         0x3c

// Type
#define D0F2x3C_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x3C_InterruptLine_OFFSET                            0
#define D0F2x3C_InterruptLine_WIDTH                             8
#define D0F2x3C_InterruptLine_MASK                              0xff
#define D0F2x3C_InterruptPin_OFFSET                             8
#define D0F2x3C_InterruptPin_WIDTH                              8
#define D0F2x3C_InterruptPin_MASK                               0xff00
#define D0F2x3C_Reserved_31_16_OFFSET                           16
#define D0F2x3C_Reserved_31_16_WIDTH                            16
#define D0F2x3C_Reserved_31_16_MASK                             0xffff0000

/// D0F2x3C
typedef union {
  struct {                                                              ///<
    UINT32                                            InterruptLine:8 ; ///<
    UINT32                                             InterruptPin:8 ; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x3C_STRUCT;

// **** D0F2x40 Register Definition ****
// Address
#define D0F2x40_ADDRESS                                         0x40

// Type
#define D0F2x40_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x40_IommuCapId_OFFSET                               0
#define D0F2x40_IommuCapId_WIDTH                                8
#define D0F2x40_IommuCapId_MASK                                 0xff
#define D0F2x40_IommuCapPtr_OFFSET                              8
#define D0F2x40_IommuCapPtr_WIDTH                               8
#define D0F2x40_IommuCapPtr_MASK                                0xff00
#define D0F2x40_IommuCapType_OFFSET                             16
#define D0F2x40_IommuCapType_WIDTH                              3
#define D0F2x40_IommuCapType_MASK                               0x70000
#define D0F2x40_IommuCapRev_OFFSET                              19
#define D0F2x40_IommuCapRev_WIDTH                               5
#define D0F2x40_IommuCapRev_MASK                                0xf80000
#define D0F2x40_IommuIoTlbsup_OFFSET                            24
#define D0F2x40_IommuIoTlbsup_WIDTH                             1
#define D0F2x40_IommuIoTlbsup_MASK                              0x1000000
#define D0F2x40_IommuHtTunnelSup_OFFSET                         25
#define D0F2x40_IommuHtTunnelSup_WIDTH                          1
#define D0F2x40_IommuHtTunnelSup_MASK                           0x2000000
#define D0F2x40_IommuNpCache_OFFSET                             26
#define D0F2x40_IommuNpCache_WIDTH                              1
#define D0F2x40_IommuNpCache_MASK                               0x4000000
#define D0F2x40_IommuEfrSup_OFFSET                              27
#define D0F2x40_IommuEfrSup_WIDTH                               1
#define D0F2x40_IommuEfrSup_MASK                                0x8000000
#define D0F2x40_Reserved_31_28_OFFSET                           28
#define D0F2x40_Reserved_31_28_WIDTH                            4
#define D0F2x40_Reserved_31_28_MASK                             0xf0000000

/// D0F2x40
typedef union {
  struct {                                                              ///<
    UINT32                                               IommuCapId:8 ; ///<
    UINT32                                              IommuCapPtr:8 ; ///<
    UINT32                                             IommuCapType:3 ; ///<
    UINT32                                              IommuCapRev:5 ; ///<
    UINT32                                            IommuIoTlbsup:1 ; ///<
    UINT32                                         IommuHtTunnelSup:1 ; ///<
    UINT32                                             IommuNpCache:1 ; ///<
    UINT32                                              IommuEfrSup:1 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x40_STRUCT;

// **** D0F2x44 Register Definition ****
// Address
#define D0F2x44_ADDRESS                                         0x44

// Type
#define D0F2x44_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x44_IommuEnable_OFFSET                              0
#define D0F2x44_IommuEnable_WIDTH                               1
#define D0F2x44_IommuEnable_MASK                                0x1
#define D0F2x44_Reserved_13_1_OFFSET                            1
#define D0F2x44_Reserved_13_1_WIDTH                             13
#define D0F2x44_Reserved_13_1_MASK                              0x3ffe
#define D0F2x44_IommuBaseAddr_31_14__OFFSET                     14
#define D0F2x44_IommuBaseAddr_31_14__WIDTH                      18
#define D0F2x44_IommuBaseAddr_31_14__MASK                       0xffffc000

/// D0F2x44
typedef union {
  struct {                                                              ///<
    UINT32                                              IommuEnable:1 ; ///<
    UINT32                                            Reserved_13_1:13; ///<
    UINT32                                     IommuBaseAddr_31_14_:18; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x44_STRUCT;

// **** D0F2x48 Register Definition ****
// Address
#define D0F2x48_ADDRESS                                         0x48

// Type
#define D0F2x48_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x48_IommuBaseAddr_63_32__OFFSET                     0
#define D0F2x48_IommuBaseAddr_63_32__WIDTH                      32
#define D0F2x48_IommuBaseAddr_63_32__MASK                       0xffffffff

/// D0F2x48
typedef union {
  struct {                                                              ///<
    UINT32                                     IommuBaseAddr_63_32_:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x48_STRUCT;

// **** D0F2x4C Register Definition ****
// Address
#define D0F2x4C_ADDRESS                                         0x4c

// Type
#define D0F2x4C_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x4C_IommuUnitId_OFFSET                              0
#define D0F2x4C_IommuUnitId_WIDTH                               5
#define D0F2x4C_IommuUnitId_MASK                                0x1f
#define D0F2x4C_Reserved_6_5_OFFSET                             5
#define D0F2x4C_Reserved_6_5_WIDTH                              2
#define D0F2x4C_Reserved_6_5_MASK                               0x60
#define D0F2x4C_IommuRngValid_OFFSET                            7
#define D0F2x4C_IommuRngValid_WIDTH                             1
#define D0F2x4C_IommuRngValid_MASK                              0x80
#define D0F2x4C_IommuBusNumber_OFFSET                           8
#define D0F2x4C_IommuBusNumber_WIDTH                            8
#define D0F2x4C_IommuBusNumber_MASK                             0xff00
#define D0F2x4C_IommuFirstDevice_OFFSET                         16
#define D0F2x4C_IommuFirstDevice_WIDTH                          8
#define D0F2x4C_IommuFirstDevice_MASK                           0xff0000
#define D0F2x4C_IommuLastDevice_OFFSET                          24
#define D0F2x4C_IommuLastDevice_WIDTH                           8
#define D0F2x4C_IommuLastDevice_MASK                            0xff000000

/// D0F2x4C
typedef union {
  struct {                                                              ///<
    UINT32                                              IommuUnitId:5 ; ///<
    UINT32                                             Reserved_6_5:2 ; ///<
    UINT32                                            IommuRngValid:1 ; ///<
    UINT32                                           IommuBusNumber:8 ; ///<
    UINT32                                         IommuFirstDevice:8 ; ///<
    UINT32                                          IommuLastDevice:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x4C_STRUCT;

// **** D0F2x50 Register Definition ****
// Address
#define D0F2x50_ADDRESS                                         0x50

// Type
#define D0F2x50_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x50_IommuMsiNum_OFFSET                              0
#define D0F2x50_IommuMsiNum_WIDTH                               5
#define D0F2x50_IommuMsiNum_MASK                                0x1f
#define D0F2x50_IommuGvaSize_OFFSET                             5
#define D0F2x50_IommuGvaSize_WIDTH                              3
#define D0F2x50_IommuGvaSize_MASK                               0xe0
#define D0F2x50_IommuPaSize_OFFSET                              8
#define D0F2x50_IommuPaSize_WIDTH                               7
#define D0F2x50_IommuPaSize_MASK                                0x7f00
#define D0F2x50_IommuVaSize_OFFSET                              15
#define D0F2x50_IommuVaSize_WIDTH                               7
#define D0F2x50_IommuVaSize_MASK                                0x3f8000
#define D0F2x50_IommuHtAtsResv_OFFSET                           22
#define D0F2x50_IommuHtAtsResv_WIDTH                            1
#define D0F2x50_IommuHtAtsResv_MASK                             0x400000
#define D0F2x50_Reserved_26_23_OFFSET                           23
#define D0F2x50_Reserved_26_23_WIDTH                            4
#define D0F2x50_Reserved_26_23_MASK                             0x7800000
#define D0F2x50_IommuMsiNumPpr_OFFSET                           27
#define D0F2x50_IommuMsiNumPpr_WIDTH                            5
#define D0F2x50_IommuMsiNumPpr_MASK                             0xf8000000

/// D0F2x50
typedef union {
  struct {                                                              ///<
    UINT32                                              IommuMsiNum:5 ; ///<
    UINT32                                             IommuGvaSize:3 ; ///<
    UINT32                                              IommuPaSize:7 ; ///<
    UINT32                                              IommuVaSize:7 ; ///<
    UINT32                                           IommuHtAtsResv:1 ; ///<
    UINT32                                           Reserved_26_23:4 ; ///<
    UINT32                                           IommuMsiNumPpr:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x50_STRUCT;

// **** D0F2x54 Register Definition ****
// Address
#define D0F2x54_ADDRESS                                         0x54

// Type
#define D0F2x54_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x54_MsiCapId_OFFSET                                 0
#define D0F2x54_MsiCapId_WIDTH                                  8
#define D0F2x54_MsiCapId_MASK                                   0xff
#define D0F2x54_MsiCapPtr_OFFSET                                8
#define D0F2x54_MsiCapPtr_WIDTH                                 8
#define D0F2x54_MsiCapPtr_MASK                                  0xff00
#define D0F2x54_MsiEn_OFFSET                                    16
#define D0F2x54_MsiEn_WIDTH                                     1
#define D0F2x54_MsiEn_MASK                                      0x10000
#define D0F2x54_MsiMultMessCap_OFFSET                           17
#define D0F2x54_MsiMultMessCap_WIDTH                            3
#define D0F2x54_MsiMultMessCap_MASK                             0xe0000
#define D0F2x54_MsiMultMessEn_OFFSET                            20
#define D0F2x54_MsiMultMessEn_WIDTH                             3
#define D0F2x54_MsiMultMessEn_MASK                              0x700000
#define D0F2x54_Msi64En_OFFSET                                  23
#define D0F2x54_Msi64En_WIDTH                                   1
#define D0F2x54_Msi64En_MASK                                    0x800000
#define D0F2x54_Reserved_31_24_OFFSET                           24
#define D0F2x54_Reserved_31_24_WIDTH                            8
#define D0F2x54_Reserved_31_24_MASK                             0xff000000

/// D0F2x54
typedef union {
  struct {                                                              ///<
    UINT32                                                 MsiCapId:8 ; ///<
    UINT32                                                MsiCapPtr:8 ; ///<
    UINT32                                                    MsiEn:1 ; ///<
    UINT32                                           MsiMultMessCap:3 ; ///<
    UINT32                                            MsiMultMessEn:3 ; ///<
    UINT32                                                  Msi64En:1 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x54_STRUCT;

// **** D0F2x58 Register Definition ****
// Address
#define D0F2x58_ADDRESS                                         0x58

// Type
#define D0F2x58_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x58_Reserved_1_0_OFFSET                             0
#define D0F2x58_Reserved_1_0_WIDTH                              2
#define D0F2x58_Reserved_1_0_MASK                               0x3
#define D0F2x58_MsiAddr_31_2__OFFSET                            2
#define D0F2x58_MsiAddr_31_2__WIDTH                             30
#define D0F2x58_MsiAddr_31_2__MASK                              0xfffffffc

/// D0F2x58
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_1_0:2 ; ///<
    UINT32                                            MsiAddr_31_2_:30; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x58_STRUCT;

// **** D0F2x5C Register Definition ****
// Address
#define D0F2x5C_ADDRESS                                         0x5c

// Type
#define D0F2x5C_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x5C_MsiAddr_63_32__OFFSET                           0
#define D0F2x5C_MsiAddr_63_32__WIDTH                            32
#define D0F2x5C_MsiAddr_63_32__MASK                             0xffffffff

/// D0F2x5C
typedef union {
  struct {                                                              ///<
    UINT32                                           MsiAddr_63_32_:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x5C_STRUCT;

// **** D0F2x60 Register Definition ****
// Address
#define D0F2x60_ADDRESS                                         0x60

// Type
#define D0F2x60_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x60_MsiData_OFFSET                                  0
#define D0F2x60_MsiData_WIDTH                                   16
#define D0F2x60_MsiData_MASK                                    0xffff
#define D0F2x60_Reserved_31_16_OFFSET                           16
#define D0F2x60_Reserved_31_16_WIDTH                            16
#define D0F2x60_Reserved_31_16_MASK                             0xffff0000

/// D0F2x60
typedef union {
  struct {                                                              ///<
    UINT32                                                  MsiData:16; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x60_STRUCT;

// **** D0F2x64 Register Definition ****
// Address
#define D0F2x64_ADDRESS                                         0x64

// Type
#define D0F2x64_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x64_MsiMapCapId_OFFSET                              0
#define D0F2x64_MsiMapCapId_WIDTH                               8
#define D0F2x64_MsiMapCapId_MASK                                0xff
#define D0F2x64_MsiMapCapPtr_OFFSET                             8
#define D0F2x64_MsiMapCapPtr_WIDTH                              8
#define D0F2x64_MsiMapCapPtr_MASK                               0xff00
#define D0F2x64_MsiMapEn_OFFSET                                 16
#define D0F2x64_MsiMapEn_WIDTH                                  1
#define D0F2x64_MsiMapEn_MASK                                   0x10000
#define D0F2x64_MsiMapFixd_OFFSET                               17
#define D0F2x64_MsiMapFixd_WIDTH                                1
#define D0F2x64_MsiMapFixd_MASK                                 0x20000
#define D0F2x64_Reserved_26_18_OFFSET                           18
#define D0F2x64_Reserved_26_18_WIDTH                            9
#define D0F2x64_Reserved_26_18_MASK                             0x7fc0000
#define D0F2x64_MsiMapCapType_OFFSET                            27
#define D0F2x64_MsiMapCapType_WIDTH                             5
#define D0F2x64_MsiMapCapType_MASK                              0xf8000000

/// D0F2x64
typedef union {
  struct {                                                              ///<
    UINT32                                              MsiMapCapId:8 ; ///<
    UINT32                                             MsiMapCapPtr:8 ; ///<
    UINT32                                                 MsiMapEn:1 ; ///<
    UINT32                                               MsiMapFixd:1 ; ///<
    UINT32                                           Reserved_26_18:9 ; ///<
    UINT32                                            MsiMapCapType:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x64_STRUCT;

// **** D0F2x6C Register Definition ****
// Address
#define D0F2x6C_ADDRESS                                         0x6c

// Type
#define D0F2x6C_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x6C_InterruptPinW_OFFSET                            0
#define D0F2x6C_InterruptPinW_WIDTH                             3
#define D0F2x6C_InterruptPinW_MASK                              0x7
#define D0F2x6C_Reserved_3_3_OFFSET                             3
#define D0F2x6C_Reserved_3_3_WIDTH                              1
#define D0F2x6C_Reserved_3_3_MASK                               0x8
#define D0F2x6C_MinorRevIdW_OFFSET                              4
#define D0F2x6C_MinorRevIdW_WIDTH                               4
#define D0F2x6C_MinorRevIdW_MASK                                0xf0
#define D0F2x6C_IoTlbsupW_OFFSET                                8
#define D0F2x6C_IoTlbsupW_WIDTH                                 1
#define D0F2x6C_IoTlbsupW_MASK                                  0x100
#define D0F2x6C_EfrSupW_OFFSET                                  9
#define D0F2x6C_EfrSupW_WIDTH                                   1
#define D0F2x6C_EfrSupW_MASK                                    0x200
#define D0F2x6C_Reserved_31_10_OFFSET                           10
#define D0F2x6C_Reserved_31_10_WIDTH                            22
#define D0F2x6C_Reserved_31_10_MASK                             0xfffffc00

/// D0F2x6C
typedef union {
  struct {                                                              ///<
    UINT32                                            InterruptPinW:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                              MinorRevIdW:4 ; ///<
    UINT32                                                IoTlbsupW:1 ; ///<
    UINT32                                                  EfrSupW:1 ; ///<
    UINT32                                           Reserved_31_10:22; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x6C_STRUCT;

// **** D0F2x70 Register Definition ****
// Address
#define D0F2x70_ADDRESS                                         0x70

// Type
#define D0F2x70_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x70_PrefSupW_OFFSET                                 0
#define D0F2x70_PrefSupW_WIDTH                                  1
#define D0F2x70_PrefSupW_MASK                                   0x1
#define D0F2x70_PprSupW_OFFSET                                  1
#define D0F2x70_PprSupW_WIDTH                                   1
#define D0F2x70_PprSupW_MASK                                    0x2
#define D0F2x70_Reserved_2_2_OFFSET                             2
#define D0F2x70_Reserved_2_2_WIDTH                              1
#define D0F2x70_Reserved_2_2_MASK                               0x4
#define D0F2x70_NxSupW_OFFSET                                   3
#define D0F2x70_NxSupW_WIDTH                                    1
#define D0F2x70_NxSupW_MASK                                     0x8
#define D0F2x70_GtSupW_OFFSET                                   4
#define D0F2x70_GtSupW_WIDTH                                    1
#define D0F2x70_GtSupW_MASK                                     0x10
#define D0F2x70_Reserved_5_5_OFFSET                             5
#define D0F2x70_Reserved_5_5_WIDTH                              1
#define D0F2x70_Reserved_5_5_MASK                               0x20
#define D0F2x70_IaSupW_OFFSET                                   6
#define D0F2x70_IaSupW_WIDTH                                    1
#define D0F2x70_IaSupW_MASK                                     0x40
#define D0F2x70_Reserved_7_7_OFFSET                             7
#define D0F2x70_Reserved_7_7_WIDTH                              1
#define D0F2x70_Reserved_7_7_MASK                               0x80
#define D0F2x70_Reserved_8_8_OFFSET                             8
#define D0F2x70_Reserved_8_8_WIDTH                              1
#define D0F2x70_Reserved_8_8_MASK                               0x100
#define D0F2x70_PcSupW_OFFSET                                   9
#define D0F2x70_PcSupW_WIDTH                                    1
#define D0F2x70_PcSupW_MASK                                     0x200
#define D0F2x70_HatsW_OFFSET                                    10
#define D0F2x70_HatsW_WIDTH                                     2
#define D0F2x70_HatsW_MASK                                      0xc00
#define D0F2x70_Reserved_31_12_OFFSET                           12
#define D0F2x70_Reserved_31_12_WIDTH                            20
#define D0F2x70_Reserved_31_12_MASK                             0xfffff000

/// D0F2x70
typedef union {
  struct {                                                              ///<
    UINT32                                                 PrefSupW:1 ; ///<
    UINT32                                                  PprSupW:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                                   NxSupW:1 ; ///<
    UINT32                                                   GtSupW:1 ; ///<
    UINT32                                             Reserved_5_5:1 ; ///<
    UINT32                                                   IaSupW:1 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                             Reserved_8_8:1 ; ///<
    UINT32                                                   PcSupW:1 ; ///<
    UINT32                                                    HatsW:2 ; ///<
    UINT32                                           Reserved_31_12:20; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x70_STRUCT;

// **** D0F2x74 Register Definition ****
// Address
#define D0F2x74_ADDRESS                                         0x74

// Type
#define D0F2x74_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x74_PasMaxW_OFFSET                                  0
#define D0F2x74_PasMaxW_WIDTH                                   4
#define D0F2x74_PasMaxW_MASK                                    0xf
#define D0F2x74_Reserved_31_4_OFFSET                            4
#define D0F2x74_Reserved_31_4_WIDTH                             28
#define D0F2x74_Reserved_31_4_MASK                              0xfffffff0

/// D0F2x74
typedef union {
  struct {                                                              ///<
    UINT32                                                  PasMaxW:4 ; ///<
    UINT32                                            Reserved_31_4:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x74_STRUCT;

// **** D0F2x78 Register Definition ****
// Address
#define D0F2x78_ADDRESS                                         0x78

// Type
#define D0F2x78_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2x78_Reserved_6_0_OFFSET                             0
#define D0F2x78_Reserved_6_0_WIDTH                              7
#define D0F2x78_Reserved_6_0_MASK                               0x7f
#define D0F2x78_RngValidW_OFFSET                                7
#define D0F2x78_RngValidW_WIDTH                                 1
#define D0F2x78_RngValidW_MASK                                  0x80
#define D0F2x78_BusNumberW_OFFSET                               8
#define D0F2x78_BusNumberW_WIDTH                                8
#define D0F2x78_BusNumberW_MASK                                 0xff00
#define D0F2x78_FirstDeviceW_OFFSET                             16
#define D0F2x78_FirstDeviceW_WIDTH                              8
#define D0F2x78_FirstDeviceW_MASK                               0xff0000
#define D0F2x78_LastDeviceW_OFFSET                              24
#define D0F2x78_LastDeviceW_WIDTH                               8
#define D0F2x78_LastDeviceW_MASK                                0xff000000

/// D0F2x78
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_6_0:7 ; ///<
    UINT32                                                RngValidW:1 ; ///<
    UINT32                                               BusNumberW:8 ; ///<
    UINT32                                             FirstDeviceW:8 ; ///<
    UINT32                                              LastDeviceW:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2x78_STRUCT;

// **** D0F2xF0 Register Definition ****
// Address
#define D0F2xF0_ADDRESS                                         0xf0

// Type
#define D0F2xF0_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2xF0_L2cfgIndex_OFFSET                               0
#define D0F2xF0_L2cfgIndex_WIDTH                                8
#define D0F2xF0_L2cfgIndex_MASK                                 0xff
#define D0F2xF0_L2cfgWrEn_OFFSET                                8
#define D0F2xF0_L2cfgWrEn_WIDTH                                 1
#define D0F2xF0_L2cfgWrEn_MASK                                  0x100
#define D0F2xF0_Reserved_31_9_OFFSET                            9
#define D0F2xF0_Reserved_31_9_WIDTH                             23
#define D0F2xF0_Reserved_31_9_MASK                              0xfffffe00

/// D0F2xF0
typedef union {
  struct {                                                              ///<
    UINT32                                               L2cfgIndex:8 ; ///<
    UINT32                                                L2cfgWrEn:1 ; ///<
    UINT32                                            Reserved_31_9:23; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF0_STRUCT;

// **** D0F2xF4 Register Definition ****
// Address
#define D0F2xF4_ADDRESS                                         0xf4

// Type
#define D0F2xF4_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2xF4_L2cfgData_OFFSET                                0
#define D0F2xF4_L2cfgData_WIDTH                                 32
#define D0F2xF4_L2cfgData_MASK                                  0xffffffff

/// D0F2xF4
typedef union {
  struct {                                                              ///<
    UINT32                                                L2cfgData:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_STRUCT;

// **** D0F2xF8 Register Definition ****
// Address
#define D0F2xF8_ADDRESS                                         0xf8

// Type
#define D0F2xF8_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2xF8_L1cfgIndex_OFFSET                               0
#define D0F2xF8_L1cfgIndex_WIDTH                                16
#define D0F2xF8_L1cfgIndex_MASK                                 0xffff
#define D0F2xF8_L1cfgSel_OFFSET                                 16
#define D0F2xF8_L1cfgSel_WIDTH                                  4
#define D0F2xF8_L1cfgSel_MASK                                   0xf0000
#define D0F2xF8_Reserved_30_20_OFFSET                           20
#define D0F2xF8_Reserved_30_20_WIDTH                            11
#define D0F2xF8_Reserved_30_20_MASK                             0x7ff00000
#define D0F2xF8_L1cfgEn_OFFSET                                  31
#define D0F2xF8_L1cfgEn_WIDTH                                   1
#define D0F2xF8_L1cfgEn_MASK                                    0x80000000

/// D0F2xF8
typedef union {
  struct {                                                              ///<
    UINT32                                               L1cfgIndex:16; ///<
    UINT32                                                 L1cfgSel:4 ; ///<
    UINT32                                           Reserved_30_20:11; ///<
    UINT32                                                  L1cfgEn:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF8_STRUCT;

// **** D0F2xFC Register Definition ****
// Address
#define D0F2xFC_ADDRESS                                         0xfc

// Type
#define D0F2xFC_TYPE                                            TYPE_D0F2
// Field Data
#define D0F2xFC_L1cfgData_OFFSET                                0
#define D0F2xFC_L1cfgData_WIDTH                                 32
#define D0F2xFC_L1cfgData_MASK                                  0xffffffff

/// D0F2xFC
typedef union {
  struct {                                                              ///<
    UINT32                                                L1cfgData:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_STRUCT;

// **** D18F0x00 Register Definition ****
// Address
#define D18F0x00_ADDRESS                                        0x0

// Type
#define D18F0x00_TYPE                                           TYPE_D18F0
// Field Data
#define D18F0x00_VendorID_OFFSET                                0
#define D18F0x00_VendorID_WIDTH                                 16
#define D18F0x00_VendorID_MASK                                  0xffff
#define D18F0x00_DeviceID_OFFSET                                16
#define D18F0x00_DeviceID_WIDTH                                 16
#define D18F0x00_DeviceID_MASK                                  0xffff0000

/// D18F0x00
typedef union {
  struct {                                                              ///<
    UINT32                                                 VendorID:16; ///<
    UINT32                                                 DeviceID:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x00_STRUCT;

// **** D18F0x04 Register Definition ****
// Address
#define D18F0x04_ADDRESS                                        0x4

// Type
#define D18F0x04_TYPE                                           TYPE_D18F0
// Field Data
#define D18F0x04_Command_OFFSET                                 0
#define D18F0x04_Command_WIDTH                                  16
#define D18F0x04_Command_MASK                                   0xffff
#define D18F0x04_Status_OFFSET                                  16
#define D18F0x04_Status_WIDTH                                   16
#define D18F0x04_Status_MASK                                    0xffff0000

/// D18F0x04
typedef union {
  struct {                                                              ///<
    UINT32                                                  Command:16; ///<
    UINT32                                                   Status:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x04_STRUCT;

// **** D18F0x08 Register Definition ****
// Address
#define D18F0x08_ADDRESS                                        0x8

// Type
#define D18F0x08_TYPE                                           TYPE_D18F0
// Field Data
#define D18F0x08_RevID_OFFSET                                   0
#define D18F0x08_RevID_WIDTH                                    8
#define D18F0x08_RevID_MASK                                     0xff
#define D18F0x08_ClassCode_OFFSET                               8
#define D18F0x08_ClassCode_WIDTH                                24
#define D18F0x08_ClassCode_MASK                                 0xffffff00

/// D18F0x08
typedef union {
  struct {                                                              ///<
    UINT32                                                    RevID:8 ; ///<
    UINT32                                                ClassCode:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x08_STRUCT;

// **** D18F0x0C Register Definition ****
// Address
#define D18F0x0C_ADDRESS                                        0xc

// Type
#define D18F0x0C_TYPE                                           TYPE_D18F0
// Field Data
#define D18F0x0C_HeaderTypeReg_OFFSET                           0
#define D18F0x0C_HeaderTypeReg_WIDTH                            32
#define D18F0x0C_HeaderTypeReg_MASK                             0xffffffff

/// D18F0x0C
typedef union {
  struct {                                                              ///<
    UINT32                                            HeaderTypeReg:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x0C_STRUCT;

// **** D18F0x34 Register Definition ****
// Address
#define D18F0x34_ADDRESS                                        0x34

// Type
#define D18F0x34_TYPE                                           TYPE_D18F0
// Field Data
#define D18F0x34_CapPtr_OFFSET                                  0
#define D18F0x34_CapPtr_WIDTH                                   8
#define D18F0x34_CapPtr_MASK                                    0xff
#define D18F0x34_Reserved_31_8_OFFSET                           8
#define D18F0x34_Reserved_31_8_WIDTH                            24
#define D18F0x34_Reserved_31_8_MASK                             0xffffff00

/// D18F0x34
typedef union {
  struct {                                                              ///<
    UINT32                                                   CapPtr:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x34_STRUCT;

// **** D18F0x40 Register Definition ****
// Address
#define D18F0x40_ADDRESS                                        0x40

// Type
#define D18F0x40_TYPE                                           TYPE_D18F0
// Field Data
#define D18F0x40_Reserved_31_0_OFFSET                           0
#define D18F0x40_Reserved_31_0_WIDTH                            32
#define D18F0x40_Reserved_31_0_MASK                             0xffffffff

/// D18F0x40
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_31_0:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x40_STRUCT;

// **** D18F0x60 Register Definition ****
// Address
#define D18F0x60_ADDRESS                                        0x60

// Type
#define D18F0x60_TYPE                                           TYPE_D18F0
// Field Data
#define D18F0x60_Reserved_15_0_OFFSET                           0
#define D18F0x60_Reserved_15_0_WIDTH                            16
#define D18F0x60_Reserved_15_0_MASK                             0xffff
#define D18F0x60_CpuCnt_4_0__OFFSET                             16
#define D18F0x60_CpuCnt_4_0__WIDTH                              5
#define D18F0x60_CpuCnt_4_0__MASK                               0x1f0000
#define D18F0x60_Reserved_31_21_OFFSET                          21
#define D18F0x60_Reserved_31_21_WIDTH                           11
#define D18F0x60_Reserved_31_21_MASK                            0xffe00000

/// D18F0x60
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_15_0:16; ///<
    UINT32                                              CpuCnt_4_0_:5 ; ///<
    UINT32                                           Reserved_31_21:11; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x60_STRUCT;

// **** D18F0x64 Register Definition ****
// Address
#define D18F0x64_ADDRESS                                        0x64

// Type
#define D18F0x64_TYPE                                           TYPE_D18F0
// Field Data
#define D18F0x64_MctUnit_OFFSET                                 4
#define D18F0x64_MctUnit_WIDTH                                  2
#define D18F0x64_MctUnit_MASK                                   0x30
#define D18F0x64_HbUnit_OFFSET                                  6
#define D18F0x64_HbUnit_WIDTH                                   2
#define D18F0x64_HbUnit_MASK                                    0xc0
#define D18F0x64_Reserved_31_8_OFFSET                           8
#define D18F0x64_Reserved_31_8_WIDTH                            24
#define D18F0x64_Reserved_31_8_MASK                             0xffffff00

/// D18F0x64
typedef union {
  struct {                                                              ///<
    UINT32                                                  CpuUnit:2 ; ///<
    UINT32                                               ExtCpuUnit:2 ; ///<
    UINT32                                                  MctUnit:2 ; ///<
    UINT32                                                   HbUnit:2 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x64_STRUCT;

// **** D18F0x68 Register Definition ****
// Address
#define D18F0x68_ADDRESS                                        0x68

// Type
#define D18F0x68_TYPE                                           TYPE_D18F0
// Field Data
#define D18F0x68_Reserved_3_0_OFFSET                            0
#define D18F0x68_Reserved_3_0_WIDTH                             4
#define D18F0x68_Reserved_3_0_MASK                              0xf
#define D18F0x68_DisMTS_OFFSET                                  4
#define D18F0x68_DisMTS_WIDTH                                   1
#define D18F0x68_DisMTS_MASK                                    0x10
#define D18F0x68_Reserved_5_5_OFFSET                            5
#define D18F0x68_Reserved_5_5_WIDTH                             1
#define D18F0x68_Reserved_5_5_MASK                              0x20
#define D18F0x68_CPUReqPassPW_OFFSET                            6
#define D18F0x68_CPUReqPassPW_WIDTH                             1
#define D18F0x68_CPUReqPassPW_MASK                              0x40
#define D18F0x68_CPURdRspPassPW_OFFSET                          7
#define D18F0x68_CPURdRspPassPW_WIDTH                           1
#define D18F0x68_CPURdRspPassPW_MASK                            0x80
#define D18F0x68_DisPMemC_OFFSET                                8
#define D18F0x68_DisPMemC_WIDTH                                 1
#define D18F0x68_DisPMemC_MASK                                  0x100
#define D18F0x68_DisRmtPMemC_OFFSET                             9
#define D18F0x68_DisRmtPMemC_WIDTH                              1
#define D18F0x68_DisRmtPMemC_MASK                               0x200
#define D18F0x68_DisFillP_OFFSET                                10
#define D18F0x68_DisFillP_WIDTH                                 1
#define D18F0x68_DisFillP_MASK                                  0x400
#define D18F0x68_RespPassPW_OFFSET                              11
#define D18F0x68_RespPassPW_WIDTH                               1
#define D18F0x68_RespPassPW_MASK                                0x800
#define D18F0x68_Reserved_14_12_OFFSET                          12
#define D18F0x68_Reserved_14_12_WIDTH                           3
#define D18F0x68_Reserved_14_12_MASK                            0x7000
#define D18F0x68_LimitCldtCfg_OFFSET                            15
#define D18F0x68_LimitCldtCfg_WIDTH                             1
#define D18F0x68_LimitCldtCfg_MASK                              0x8000
#define D18F0x68_LintEn_OFFSET                                  16
#define D18F0x68_LintEn_WIDTH                                   1
#define D18F0x68_LintEn_MASK                                    0x10000
#define D18F0x68_ApicExtBrdCst_OFFSET                           17
#define D18F0x68_ApicExtBrdCst_WIDTH                            1
#define D18F0x68_ApicExtBrdCst_MASK                             0x20000
#define D18F0x68_ApicExtId_OFFSET                               18
#define D18F0x68_ApicExtId_WIDTH                                1
#define D18F0x68_ApicExtId_MASK                                 0x40000
#define D18F0x68_ApicExtSpur_OFFSET                             19
#define D18F0x68_ApicExtSpur_WIDTH                              1
#define D18F0x68_ApicExtSpur_MASK                               0x80000
#define D18F0x68_SeqIdSrcNodeEn_OFFSET                          20
#define D18F0x68_SeqIdSrcNodeEn_WIDTH                           1
#define D18F0x68_SeqIdSrcNodeEn_MASK                            0x100000
#define D18F0x68_DsNpReqLmt_OFFSET                              21
#define D18F0x68_DsNpReqLmt_WIDTH                               2
#define D18F0x68_DsNpReqLmt_MASK                                0x600000
#define D18F0x68_Reserved_31_23_OFFSET                          23
#define D18F0x68_Reserved_31_23_WIDTH                           9
#define D18F0x68_Reserved_31_23_MASK                            0xff800000

/// D18F0x68
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_3_0:4 ; ///<
    UINT32                                                   DisMTS:1 ; ///<
    UINT32                                             Reserved_5_5:1 ; ///<
    UINT32                                             CPUReqPassPW:1 ; ///<
    UINT32                                           CPURdRspPassPW:1 ; ///<
    UINT32                                                 DisPMemC:1 ; ///<
    UINT32                                              DisRmtPMemC:1 ; ///<
    UINT32                                                 DisFillP:1 ; ///<
    UINT32                                               RespPassPW:1 ; ///<
    UINT32                                           Reserved_14_12:3 ; ///<
    UINT32                                             LimitCldtCfg:1 ; ///<
    UINT32                                                   LintEn:1 ; ///<
    UINT32                                            ApicExtBrdCst:1 ; ///<
    UINT32                                                ApicExtId:1 ; ///<
    UINT32                                              ApicExtSpur:1 ; ///<
    UINT32                                           SeqIdSrcNodeEn:1 ; ///<
    UINT32                                               DsNpReqLmt:2 ; ///<
    UINT32                                           Reserved_31_23:9 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x68_STRUCT;

// **** D18F0x6C Register Definition ****
// Address
#define D18F0x6C_ADDRESS                                        0x6c

// Type
#define D18F0x6C_TYPE                                           TYPE_D18F0
// Field Data
#define D18F0x6C_RouteTblDis_OFFSET                             0
#define D18F0x6C_RouteTblDis_WIDTH                              1
#define D18F0x6C_RouteTblDis_MASK                               0x1
#define D18F0x6C_Reserved_3_1_OFFSET                            1
#define D18F0x6C_Reserved_3_1_WIDTH                             3
#define D18F0x6C_Reserved_3_1_MASK                              0xe
#define D18F0x6C_ColdRstDet_OFFSET                              4
#define D18F0x6C_ColdRstDet_WIDTH                               1
#define D18F0x6C_ColdRstDet_MASK                                0x10
#define D18F0x6C_BiosRstDet_0__OFFSET                           5
#define D18F0x6C_BiosRstDet_0__WIDTH                            1
#define D18F0x6C_BiosRstDet_0__MASK                             0x20
#define D18F0x6C_InitDet_OFFSET                                 6
#define D18F0x6C_InitDet_WIDTH                                  1
#define D18F0x6C_InitDet_MASK                                   0x40
#define D18F0x6C_Reserved_8_7_OFFSET                            7
#define D18F0x6C_Reserved_8_7_WIDTH                             2
#define D18F0x6C_Reserved_8_7_MASK                              0x180
#define D18F0x6C_BiosRstDet_2_1__OFFSET                         9
#define D18F0x6C_BiosRstDet_2_1__WIDTH                          2
#define D18F0x6C_BiosRstDet_2_1__MASK                           0x600
#define D18F0x6C_Reserved_26_11_OFFSET                          11
#define D18F0x6C_Reserved_26_11_WIDTH                           16
#define D18F0x6C_Reserved_26_11_MASK                            0x7fff800
#define D18F0x6C_ApplyIsocModeEnNow_OFFSET                      27
#define D18F0x6C_ApplyIsocModeEnNow_WIDTH                       1
#define D18F0x6C_ApplyIsocModeEnNow_MASK                        0x8000000
#define D18F0x6C_RlsIntFullTokCntImm_OFFSET                     28
#define D18F0x6C_RlsIntFullTokCntImm_WIDTH                      1
#define D18F0x6C_RlsIntFullTokCntImm_MASK                       0x10000000
#define D18F0x6C_Reserved_29_29_OFFSET                          29
#define D18F0x6C_Reserved_29_29_WIDTH                           1
#define D18F0x6C_Reserved_29_29_MASK                            0x20000000
#define D18F0x6C_RlsLnkFullTokCntImm_OFFSET                     30
#define D18F0x6C_RlsLnkFullTokCntImm_WIDTH                      1
#define D18F0x6C_RlsLnkFullTokCntImm_MASK                       0x40000000
#define D18F0x6C_Reserved_31_31_OFFSET                          31
#define D18F0x6C_Reserved_31_31_WIDTH                           1
#define D18F0x6C_Reserved_31_31_MASK                            0x80000000

/// D18F0x6C
typedef union {
  struct {                                                              ///<
    UINT32                                              RouteTblDis:1 ; ///<
    UINT32                                             Reserved_3_1:3 ; ///<
    UINT32                                               ColdRstDet:1 ; ///<
    UINT32                                            BiosRstDet_0_:1 ; ///<
    UINT32                                                  InitDet:1 ; ///<
    UINT32                                             Reserved_8_7:2 ; ///<
    UINT32                                          BiosRstDet_2_1_:2 ; ///<
    UINT32                                           Reserved_26_11:16; ///<
    UINT32                                       ApplyIsocModeEnNow:1 ; ///<
    UINT32                                      RlsIntFullTokCntImm:1 ; ///<
    UINT32                                           Reserved_29_29:1 ; ///<
    UINT32                                      RlsLnkFullTokCntImm:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x6C_STRUCT;

// **** D18F0x84 Register Definition ****
// Address
#define D18F0x84_ADDRESS                                        0x84

// Type
#define D18F0x84_TYPE                                           TYPE_D18F0
// Field Data
#define D18F0x84_Reserved_3_0_OFFSET                            0
#define D18F0x84_Reserved_3_0_WIDTH                             4
#define D18F0x84_Reserved_3_0_MASK                              0xf
#define D18F0x84_LinkFail_OFFSET                                4
#define D18F0x84_LinkFail_WIDTH                                 1
#define D18F0x84_LinkFail_MASK                                  0x10
#define D18F0x84_Reserved_5_5_OFFSET                            5
#define D18F0x84_Reserved_5_5_WIDTH                             1
#define D18F0x84_Reserved_5_5_MASK                              0x20
#define D18F0x84_Reserved_11_6_OFFSET                           6
#define D18F0x84_Reserved_11_6_WIDTH                            6
#define D18F0x84_Reserved_11_6_MASK                             0xfc0
#define D18F0x84_IsocEn_OFFSET                                  12
#define D18F0x84_IsocEn_WIDTH                                   1
#define D18F0x84_IsocEn_MASK                                    0x1000
#define D18F0x84_Reserved_31_13_OFFSET                          13
#define D18F0x84_Reserved_31_13_WIDTH                           19
#define D18F0x84_Reserved_31_13_MASK                            0xffffe000

/// D18F0x84
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_3_0:4 ; ///<
    UINT32                                                 LinkFail:1 ; ///<
    UINT32                                             Reserved_5_5:1 ; ///<
    UINT32                                            Reserved_11_6:6 ; ///<
    UINT32                                                   IsocEn:1 ; ///<
    UINT32                                           Reserved_31_13:19; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x84_STRUCT;

// **** D18F0x90 Register Definition ****
// Address
#define D18F0x90_ADDRESS                                        0x90

// Type
#define D18F0x90_TYPE                                           TYPE_D18F0
// Field Data
#define D18F0x90_NpReqCmd_OFFSET                                0
#define D18F0x90_NpReqCmd_WIDTH                                 5
#define D18F0x90_NpReqCmd_MASK                                  0x1f
#define D18F0x90_PReq_OFFSET                                    5
#define D18F0x90_PReq_WIDTH                                     3
#define D18F0x90_PReq_MASK                                      0xe0
#define D18F0x90_RspCmd_OFFSET                                  8
#define D18F0x90_RspCmd_WIDTH                                   4
#define D18F0x90_RspCmd_MASK                                    0xf00
#define D18F0x90_ProbeCmd_OFFSET                                12
#define D18F0x90_ProbeCmd_WIDTH                                 4
#define D18F0x90_ProbeCmd_MASK                                  0xf000
#define D18F0x90_NpReqData_OFFSET                               16
#define D18F0x90_NpReqData_WIDTH                                2
#define D18F0x90_NpReqData_MASK                                 0x30000
#define D18F0x90_RspData_OFFSET                                 18
#define D18F0x90_RspData_WIDTH                                  2
#define D18F0x90_RspData_MASK                                   0xc0000
#define D18F0x90_FreeCmd_OFFSET                                 20
#define D18F0x90_FreeCmd_WIDTH                                  5
#define D18F0x90_FreeCmd_MASK                                   0x1f00000
#define D18F0x90_FreeData_OFFSET                                25
#define D18F0x90_FreeData_WIDTH                                 3
#define D18F0x90_FreeData_MASK                                  0xe000000
#define D18F0x90_Reserved_30_28_OFFSET                          28
#define D18F0x90_Reserved_30_28_WIDTH                           3
#define D18F0x90_Reserved_30_28_MASK                            0x70000000
#define D18F0x90_LockBc_OFFSET                                  31
#define D18F0x90_LockBc_WIDTH                                   1
#define D18F0x90_LockBc_MASK                                    0x80000000

/// D18F0x90
typedef union {
  struct {                                                              ///<
    UINT32                                                 NpReqCmd:5 ; ///<
    UINT32                                                     PReq:3 ; ///<
    UINT32                                                   RspCmd:4 ; ///<
    UINT32                                                 ProbeCmd:4 ; ///<
    UINT32                                                NpReqData:2 ; ///<
    UINT32                                                  RspData:2 ; ///<
    UINT32                                                  FreeCmd:5 ; ///<
    UINT32                                                 FreeData:3 ; ///<
    UINT32                                           Reserved_30_28:3 ; ///<
    UINT32                                                   LockBc:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x90_STRUCT;

// **** D18F0x94 Register Definition ****
// Address
#define D18F0x94_ADDRESS                                        0x94

// Type
#define D18F0x94_TYPE                                           TYPE_D18F0
// Field Data
#define D18F0x94_Reserved_7_0_OFFSET                            0
#define D18F0x94_Reserved_7_0_WIDTH                             8
#define D18F0x94_Reserved_7_0_MASK                              0xff
#define D18F0x94_SecBusNum_OFFSET                               8
#define D18F0x94_SecBusNum_WIDTH                                8
#define D18F0x94_SecBusNum_MASK                                 0xff00
#define D18F0x94_IsocNpReqCmd_OFFSET                            16
#define D18F0x94_IsocNpReqCmd_WIDTH                             3
#define D18F0x94_IsocNpReqCmd_MASK                              0x70000
#define D18F0x94_IsocPReq_OFFSET                                19
#define D18F0x94_IsocPReq_WIDTH                                 3
#define D18F0x94_IsocPReq_MASK                                  0x380000
#define D18F0x94_IsocRspCmd_OFFSET                              22
#define D18F0x94_IsocRspCmd_WIDTH                               3
#define D18F0x94_IsocRspCmd_MASK                                0x1c00000
#define D18F0x94_IsocNpReqData_OFFSET                           25
#define D18F0x94_IsocNpReqData_WIDTH                            2
#define D18F0x94_IsocNpReqData_MASK                             0x6000000
#define D18F0x94_IsocRspData_OFFSET                             27
#define D18F0x94_IsocRspData_WIDTH                              2
#define D18F0x94_IsocRspData_MASK                               0x18000000
#define D18F0x94_Reserved_31_29_OFFSET                          29
#define D18F0x94_Reserved_31_29_WIDTH                           3
#define D18F0x94_Reserved_31_29_MASK                            0xe0000000

/// D18F0x94
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_7_0:8 ; ///<
    UINT32                                                SecBusNum:8 ; ///<
    UINT32                                             IsocNpReqCmd:3 ; ///<
    UINT32                                                 IsocPReq:3 ; ///<
    UINT32                                               IsocRspCmd:3 ; ///<
    UINT32                                            IsocNpReqData:2 ; ///<
    UINT32                                              IsocRspData:2 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x94_STRUCT;

// **** D18F0x98 Register Definition ****
// Address
#define D18F0x98_ADDRESS                                        0x98

// Type
#define D18F0x98_TYPE                                           TYPE_D18F0
// Field Data
#define D18F0x98_Reserved_0_0_OFFSET                            0
#define D18F0x98_Reserved_0_0_WIDTH                             1
#define D18F0x98_Reserved_0_0_MASK                              0x1
#define D18F0x98_Reserved_1_1_OFFSET                            1
#define D18F0x98_Reserved_1_1_WIDTH                             1
#define D18F0x98_Reserved_1_1_MASK                              0x2
#define D18F0x98_Reserved_2_2_OFFSET                            2
#define D18F0x98_Reserved_2_2_WIDTH                             1
#define D18F0x98_Reserved_2_2_MASK                              0x4
#define D18F0x98_Reserved_4_3_OFFSET                            3
#define D18F0x98_Reserved_4_3_WIDTH                             2
#define D18F0x98_Reserved_4_3_MASK                              0x18
#define D18F0x98_PciEligible_OFFSET                             5
#define D18F0x98_PciEligible_WIDTH                              1
#define D18F0x98_PciEligible_MASK                               0x20
#define D18F0x98_Reserved_31_6_OFFSET                           6
#define D18F0x98_Reserved_31_6_WIDTH                            26
#define D18F0x98_Reserved_31_6_MASK                             0xffffffc0

/// D18F0x98
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                             Reserved_4_3:2 ; ///<
    UINT32                                              PciEligible:1 ; ///<
    UINT32                                            Reserved_31_6:26; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x98_STRUCT;

// **** D18F0x9C Register Definition ****
// Address
#define D18F0x9C_ADDRESS                                        0x9c

// Type
#define D18F0x9C_TYPE                                           TYPE_D18F0
// Field Data
#define D18F0x9C_Reserved_0_0_OFFSET                            0
#define D18F0x9C_Reserved_0_0_WIDTH                             1
#define D18F0x9C_Reserved_0_0_MASK                              0x1
#define D18F0x9C_Reserved_15_1_OFFSET                           1
#define D18F0x9C_Reserved_15_1_WIDTH                            15
#define D18F0x9C_Reserved_15_1_MASK                             0xfffe
#define D18F0x9C_Reserved_31_16_OFFSET                          16
#define D18F0x9C_Reserved_31_16_WIDTH                           16
#define D18F0x9C_Reserved_31_16_MASK                            0xffff0000

/// D18F0x9C
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                            Reserved_15_1:15; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x9C_STRUCT;

// **** D18F0x110 Register Definition ****
// Address
#define D18F0x110_ADDRESS                                       0x110

// Type
#define D18F0x110_TYPE                                          TYPE_D18F0
// Field Data
#define D18F0x110_Reserved_0_0_OFFSET                           0
#define D18F0x110_Reserved_0_0_WIDTH                            1
#define D18F0x110_Reserved_0_0_MASK                             0x1
#define D18F0x110_Reserved_1_1_OFFSET                           1
#define D18F0x110_Reserved_1_1_WIDTH                            1
#define D18F0x110_Reserved_1_1_MASK                             0x2
#define D18F0x110_ClumpEn_OFFSET                                2
#define D18F0x110_ClumpEn_WIDTH                                 30
#define D18F0x110_ClumpEn_MASK                                  0xfffffffc

/// D18F0x110
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                                  ClumpEn:30; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x110_STRUCT;

// **** D18F0x16C Register Definition ****
// Address
#define D18F0x16C_ADDRESS                                       0x16c

// Type
#define D18F0x16C_TYPE                                          TYPE_D18F0
// Field Data
#define D18F0x16C_Reserved_31_0_OFFSET                          0
#define D18F0x16C_Reserved_31_0_WIDTH                           32
#define D18F0x16C_Reserved_31_0_MASK                            0xffffffff

/// D18F0x16C
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_31_0:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x16C_STRUCT;

// **** D18F0x170 Register Definition ****
// Address
#define D18F0x170_ADDRESS                                       0x170

// Type
#define D18F0x170_TYPE                                          TYPE_D18F0
// Field Data
#define D18F0x170_Reserved_31_0_OFFSET                          0
#define D18F0x170_Reserved_31_0_WIDTH                           32
#define D18F0x170_Reserved_31_0_MASK                            0xffffffff

/// D18F0x170
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_31_0:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x170_STRUCT;

// **** D18F0x1A0 Register Definition ****
// Address
#define D18F0x1A0_ADDRESS                                       0x1a0

// Type
#define D18F0x1A0_TYPE                                          TYPE_D18F0
// Field Data
#define D18F0x1A0_InitComplete_OFFSET                           0
#define D18F0x1A0_InitComplete_WIDTH                            2
#define D18F0x1A0_InitComplete_MASK                             0x3
#define D18F0x1A0_Reserved_30_2_OFFSET                          2
#define D18F0x1A0_Reserved_30_2_WIDTH                           29
#define D18F0x1A0_Reserved_30_2_MASK                            0x7ffffffc
#define D18F0x1A0_InitStatusValid_OFFSET                        31
#define D18F0x1A0_InitStatusValid_WIDTH                         1
#define D18F0x1A0_InitStatusValid_MASK                          0x80000000

/// D18F0x1A0
typedef union {
  struct {                                                              ///<
    UINT32                                             InitComplete:2 ; ///<
    UINT32                                            Reserved_30_2:29; ///<
    UINT32                                          InitStatusValid:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x1A0_STRUCT;

// **** D18F0x1DC Register Definition ****
// Address
#define D18F0x1DC_ADDRESS                                       0x1dc

// Type
#define D18F0x1DC_TYPE                                          TYPE_D18F0
// Field Data
#define D18F0x1DC_Reserved_0_0_OFFSET                           0
#define D18F0x1DC_Reserved_0_0_WIDTH                            1
#define D18F0x1DC_Reserved_0_0_MASK                             0x1
#define D18F0x1DC_CpuEn_OFFSET                                  1
#define D18F0x1DC_CpuEn_WIDTH                                   7
#define D18F0x1DC_CpuEn_MASK                                    0xfe
#define D18F0x1DC_Reserved_31_8_OFFSET                          8
#define D18F0x1DC_Reserved_31_8_WIDTH                           24
#define D18F0x1DC_Reserved_31_8_MASK                            0xffffff00

/// D18F0x1DC
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                    CpuEn:7 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F0x1DC_STRUCT;

// **** D18F1x00 Register Definition ****
// Address
#define D18F1x00_ADDRESS                                        0x0

// Type
#define D18F1x00_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1x00_VendorID_OFFSET                                0
#define D18F1x00_VendorID_WIDTH                                 16
#define D18F1x00_VendorID_MASK                                  0xffff
#define D18F1x00_DeviceID_OFFSET                                16
#define D18F1x00_DeviceID_WIDTH                                 16
#define D18F1x00_DeviceID_MASK                                  0xffff0000

/// D18F1x00
typedef union {
  struct {                                                              ///<
    UINT32                                                 VendorID:16; ///<
    UINT32                                                 DeviceID:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x00_STRUCT;

// **** D18F1x08 Register Definition ****
// Address
#define D18F1x08_ADDRESS                                        0x8

// Type
#define D18F1x08_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1x08_RevID_OFFSET                                   0
#define D18F1x08_RevID_WIDTH                                    8
#define D18F1x08_RevID_MASK                                     0xff
#define D18F1x08_ClassCode_OFFSET                               8
#define D18F1x08_ClassCode_WIDTH                                24
#define D18F1x08_ClassCode_MASK                                 0xffffff00

/// D18F1x08
typedef union {
  struct {                                                              ///<
    UINT32                                                    RevID:8 ; ///<
    UINT32                                                ClassCode:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x08_STRUCT;

// **** D18F1x0C Register Definition ****
// Address
#define D18F1x0C_ADDRESS                                        0xc

// Type
#define D18F1x0C_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1x0C_HeaderTypeReg_OFFSET                           0
#define D18F1x0C_HeaderTypeReg_WIDTH                            32
#define D18F1x0C_HeaderTypeReg_MASK                             0xffffffff

/// D18F1x0C
typedef union {
  struct {                                                              ///<
    UINT32                                            HeaderTypeReg:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x0C_STRUCT;

// **** D18F1x40 Register Definition ****
// Address
#define D18F1x40_ADDRESS                                        0x40

// Type
#define D18F1x40_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1x40_RE_OFFSET                                      0
#define D18F1x40_RE_WIDTH                                       1
#define D18F1x40_RE_MASK                                        0x1
#define D18F1x40_WE_OFFSET                                      1
#define D18F1x40_WE_WIDTH                                       1
#define D18F1x40_WE_MASK                                        0x2
#define D18F1x40_Reserved_15_2_OFFSET                           2
#define D18F1x40_Reserved_15_2_WIDTH                            14
#define D18F1x40_Reserved_15_2_MASK                             0xfffc
#define D18F1x40_DramBase_39_24__OFFSET                         16
#define D18F1x40_DramBase_39_24__WIDTH                          16
#define D18F1x40_DramBase_39_24__MASK                           0xffff0000

/// D18F1x40
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                            Reserved_15_2:14; ///<
    UINT32                                          DramBase_39_24_:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x40_STRUCT;

// **** D18F1x44 Register Definition ****
// Address
#define D18F1x44_ADDRESS                                        0x44

// Type
#define D18F1x44_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1x44_DstNode_OFFSET                                 0
#define D18F1x44_DstNode_WIDTH                                  3
#define D18F1x44_DstNode_MASK                                   0x7
#define D18F1x44_Reserved_7_3_OFFSET                            3
#define D18F1x44_Reserved_7_3_WIDTH                             5
#define D18F1x44_Reserved_7_3_MASK                              0xf8
#define D18F1x44_Reserved_10_8_OFFSET                           8
#define D18F1x44_Reserved_10_8_WIDTH                            3
#define D18F1x44_Reserved_10_8_MASK                             0x700
#define D18F1x44_Reserved_15_11_OFFSET                          11
#define D18F1x44_Reserved_15_11_WIDTH                           5
#define D18F1x44_Reserved_15_11_MASK                            0xf800
#define D18F1x44_DramLimit_39_24__OFFSET                        16
#define D18F1x44_DramLimit_39_24__WIDTH                         16
#define D18F1x44_DramLimit_39_24__MASK                          0xffff0000

/// D18F1x44
typedef union {
  struct {                                                              ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                             Reserved_7_3:5 ; ///<
    UINT32                                            Reserved_10_8:3 ; ///<
    UINT32                                           Reserved_15_11:5 ; ///<
    UINT32                                         DramLimit_39_24_:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x44_STRUCT;

// **** D18F1x80 Register Definition ****
// Address
#define D18F1x80_ADDRESS                                        0x80

// Type
#define D18F1x80_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1x80_RE_OFFSET                                      0
#define D18F1x80_RE_WIDTH                                       1
#define D18F1x80_RE_MASK                                        0x1
#define D18F1x80_WE_OFFSET                                      1
#define D18F1x80_WE_WIDTH                                       1
#define D18F1x80_WE_MASK                                        0x2
#define D18F1x80_Reserved_2_2_OFFSET                            2
#define D18F1x80_Reserved_2_2_WIDTH                             1
#define D18F1x80_Reserved_2_2_MASK                              0x4
#define D18F1x80_Lock_OFFSET                                    3
#define D18F1x80_Lock_WIDTH                                     1
#define D18F1x80_Lock_MASK                                      0x8
#define D18F1x80_Reserved_7_4_OFFSET                            4
#define D18F1x80_Reserved_7_4_WIDTH                             4
#define D18F1x80_Reserved_7_4_MASK                              0xf0
#define D18F1x80_MMIOBase_39_16__OFFSET                         8
#define D18F1x80_MMIOBase_39_16__WIDTH                          24
#define D18F1x80_MMIOBase_39_16__MASK                           0xffffff00

/// D18F1x80
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                                     Lock:1 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                          MMIOBase_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x80_STRUCT;

// **** D18F1x84 Register Definition ****
// Address
#define D18F1x84_ADDRESS                                        0x84

// Type
#define D18F1x84_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1x84_DstNode_OFFSET                                 0
#define D18F1x84_DstNode_WIDTH                                  3
#define D18F1x84_DstNode_MASK                                   0x7
#define D18F1x84_Reserved_3_3_OFFSET                            3
#define D18F1x84_Reserved_3_3_WIDTH                             1
#define D18F1x84_Reserved_3_3_MASK                              0x8
#define D18F1x84_DstLink_OFFSET                                 4
#define D18F1x84_DstLink_WIDTH                                  2
#define D18F1x84_DstLink_MASK                                   0x30
#define D18F1x84_DstSubLink_OFFSET                              6
#define D18F1x84_DstSubLink_WIDTH                               1
#define D18F1x84_DstSubLink_MASK                                0x40
#define D18F1x84_NP_OFFSET                                      7
#define D18F1x84_NP_WIDTH                                       1
#define D18F1x84_NP_MASK                                        0x80
#define D18F1x84_MMIOLimit_39_16__OFFSET                        8
#define D18F1x84_MMIOLimit_39_16__WIDTH                         24
#define D18F1x84_MMIOLimit_39_16__MASK                          0xffffff00

/// D18F1x84
typedef union {
  struct {                                                              ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                  DstLink:2 ; ///<
    UINT32                                               DstSubLink:1 ; ///<
    UINT32                                                       NP:1 ; ///<
    UINT32                                         MMIOLimit_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x84_STRUCT;

// **** D18F1x88 Register Definition ****
// Address
#define D18F1x88_ADDRESS                                        0x88

// Type
#define D18F1x88_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1x88_RE_OFFSET                                      0
#define D18F1x88_RE_WIDTH                                       1
#define D18F1x88_RE_MASK                                        0x1
#define D18F1x88_WE_OFFSET                                      1
#define D18F1x88_WE_WIDTH                                       1
#define D18F1x88_WE_MASK                                        0x2
#define D18F1x88_Reserved_2_2_OFFSET                            2
#define D18F1x88_Reserved_2_2_WIDTH                             1
#define D18F1x88_Reserved_2_2_MASK                              0x4
#define D18F1x88_Lock_OFFSET                                    3
#define D18F1x88_Lock_WIDTH                                     1
#define D18F1x88_Lock_MASK                                      0x8
#define D18F1x88_Reserved_7_4_OFFSET                            4
#define D18F1x88_Reserved_7_4_WIDTH                             4
#define D18F1x88_Reserved_7_4_MASK                              0xf0
#define D18F1x88_MMIOBase_39_16__OFFSET                         8
#define D18F1x88_MMIOBase_39_16__WIDTH                          24
#define D18F1x88_MMIOBase_39_16__MASK                           0xffffff00

/// D18F1x88
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                                     Lock:1 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                          MMIOBase_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x88_STRUCT;

// **** D18F1x8C Register Definition ****
// Address
#define D18F1x8C_ADDRESS                                        0x8c

// Type
#define D18F1x8C_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1x8C_DstNode_OFFSET                                 0
#define D18F1x8C_DstNode_WIDTH                                  3
#define D18F1x8C_DstNode_MASK                                   0x7
#define D18F1x8C_Reserved_3_3_OFFSET                            3
#define D18F1x8C_Reserved_3_3_WIDTH                             1
#define D18F1x8C_Reserved_3_3_MASK                              0x8
#define D18F1x8C_DstLink_OFFSET                                 4
#define D18F1x8C_DstLink_WIDTH                                  2
#define D18F1x8C_DstLink_MASK                                   0x30
#define D18F1x8C_DstSubLink_OFFSET                              6
#define D18F1x8C_DstSubLink_WIDTH                               1
#define D18F1x8C_DstSubLink_MASK                                0x40
#define D18F1x8C_NP_OFFSET                                      7
#define D18F1x8C_NP_WIDTH                                       1
#define D18F1x8C_NP_MASK                                        0x80
#define D18F1x8C_MMIOLimit_39_16__OFFSET                        8
#define D18F1x8C_MMIOLimit_39_16__WIDTH                         24
#define D18F1x8C_MMIOLimit_39_16__MASK                          0xffffff00

/// D18F1x8C
typedef union {
  struct {                                                              ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                  DstLink:2 ; ///<
    UINT32                                               DstSubLink:1 ; ///<
    UINT32                                                       NP:1 ; ///<
    UINT32                                         MMIOLimit_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x8C_STRUCT;

// **** D18F1x90 Register Definition ****
// Address
#define D18F1x90_ADDRESS                                        0x90

// Type
#define D18F1x90_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1x90_RE_OFFSET                                      0
#define D18F1x90_RE_WIDTH                                       1
#define D18F1x90_RE_MASK                                        0x1
#define D18F1x90_WE_OFFSET                                      1
#define D18F1x90_WE_WIDTH                                       1
#define D18F1x90_WE_MASK                                        0x2
#define D18F1x90_Reserved_2_2_OFFSET                            2
#define D18F1x90_Reserved_2_2_WIDTH                             1
#define D18F1x90_Reserved_2_2_MASK                              0x4
#define D18F1x90_Lock_OFFSET                                    3
#define D18F1x90_Lock_WIDTH                                     1
#define D18F1x90_Lock_MASK                                      0x8
#define D18F1x90_Reserved_7_4_OFFSET                            4
#define D18F1x90_Reserved_7_4_WIDTH                             4
#define D18F1x90_Reserved_7_4_MASK                              0xf0
#define D18F1x90_MMIOBase_39_16__OFFSET                         8
#define D18F1x90_MMIOBase_39_16__WIDTH                          24
#define D18F1x90_MMIOBase_39_16__MASK                           0xffffff00

/// D18F1x90
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                                     Lock:1 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                          MMIOBase_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x90_STRUCT;

// **** D18F1x94 Register Definition ****
// Address
#define D18F1x94_ADDRESS                                        0x94

// Type
#define D18F1x94_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1x94_DstNode_OFFSET                                 0
#define D18F1x94_DstNode_WIDTH                                  3
#define D18F1x94_DstNode_MASK                                   0x7
#define D18F1x94_Reserved_3_3_OFFSET                            3
#define D18F1x94_Reserved_3_3_WIDTH                             1
#define D18F1x94_Reserved_3_3_MASK                              0x8
#define D18F1x94_DstLink_OFFSET                                 4
#define D18F1x94_DstLink_WIDTH                                  2
#define D18F1x94_DstLink_MASK                                   0x30
#define D18F1x94_DstSubLink_OFFSET                              6
#define D18F1x94_DstSubLink_WIDTH                               1
#define D18F1x94_DstSubLink_MASK                                0x40
#define D18F1x94_NP_OFFSET                                      7
#define D18F1x94_NP_WIDTH                                       1
#define D18F1x94_NP_MASK                                        0x80
#define D18F1x94_MMIOLimit_39_16__OFFSET                        8
#define D18F1x94_MMIOLimit_39_16__WIDTH                         24
#define D18F1x94_MMIOLimit_39_16__MASK                          0xffffff00

/// D18F1x94
typedef union {
  struct {                                                              ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                  DstLink:2 ; ///<
    UINT32                                               DstSubLink:1 ; ///<
    UINT32                                                       NP:1 ; ///<
    UINT32                                         MMIOLimit_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x94_STRUCT;

// **** D18F1x98 Register Definition ****
// Address
#define D18F1x98_ADDRESS                                        0x98

// Type
#define D18F1x98_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1x98_RE_OFFSET                                      0
#define D18F1x98_RE_WIDTH                                       1
#define D18F1x98_RE_MASK                                        0x1
#define D18F1x98_WE_OFFSET                                      1
#define D18F1x98_WE_WIDTH                                       1
#define D18F1x98_WE_MASK                                        0x2
#define D18F1x98_Reserved_2_2_OFFSET                            2
#define D18F1x98_Reserved_2_2_WIDTH                             1
#define D18F1x98_Reserved_2_2_MASK                              0x4
#define D18F1x98_Lock_OFFSET                                    3
#define D18F1x98_Lock_WIDTH                                     1
#define D18F1x98_Lock_MASK                                      0x8
#define D18F1x98_Reserved_7_4_OFFSET                            4
#define D18F1x98_Reserved_7_4_WIDTH                             4
#define D18F1x98_Reserved_7_4_MASK                              0xf0
#define D18F1x98_MMIOBase_39_16__OFFSET                         8
#define D18F1x98_MMIOBase_39_16__WIDTH                          24
#define D18F1x98_MMIOBase_39_16__MASK                           0xffffff00

/// D18F1x98
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                                     Lock:1 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                          MMIOBase_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x98_STRUCT;

// **** D18F1x9C Register Definition ****
// Address
#define D18F1x9C_ADDRESS                                        0x9c

// Type
#define D18F1x9C_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1x9C_DstNode_OFFSET                                 0
#define D18F1x9C_DstNode_WIDTH                                  3
#define D18F1x9C_DstNode_MASK                                   0x7
#define D18F1x9C_Reserved_3_3_OFFSET                            3
#define D18F1x9C_Reserved_3_3_WIDTH                             1
#define D18F1x9C_Reserved_3_3_MASK                              0x8
#define D18F1x9C_DstLink_OFFSET                                 4
#define D18F1x9C_DstLink_WIDTH                                  2
#define D18F1x9C_DstLink_MASK                                   0x30
#define D18F1x9C_DstSubLink_OFFSET                              6
#define D18F1x9C_DstSubLink_WIDTH                               1
#define D18F1x9C_DstSubLink_MASK                                0x40
#define D18F1x9C_NP_OFFSET                                      7
#define D18F1x9C_NP_WIDTH                                       1
#define D18F1x9C_NP_MASK                                        0x80
#define D18F1x9C_MMIOLimit_39_16__OFFSET                        8
#define D18F1x9C_MMIOLimit_39_16__WIDTH                         24
#define D18F1x9C_MMIOLimit_39_16__MASK                          0xffffff00

/// D18F1x9C
typedef union {
  struct {                                                              ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                  DstLink:2 ; ///<
    UINT32                                               DstSubLink:1 ; ///<
    UINT32                                                       NP:1 ; ///<
    UINT32                                         MMIOLimit_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x9C_STRUCT;

// **** D18F1xA0 Register Definition ****
// Address
#define D18F1xA0_ADDRESS                                        0xa0

// Type
#define D18F1xA0_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xA0_RE_OFFSET                                      0
#define D18F1xA0_RE_WIDTH                                       1
#define D18F1xA0_RE_MASK                                        0x1
#define D18F1xA0_WE_OFFSET                                      1
#define D18F1xA0_WE_WIDTH                                       1
#define D18F1xA0_WE_MASK                                        0x2
#define D18F1xA0_Reserved_2_2_OFFSET                            2
#define D18F1xA0_Reserved_2_2_WIDTH                             1
#define D18F1xA0_Reserved_2_2_MASK                              0x4
#define D18F1xA0_Lock_OFFSET                                    3
#define D18F1xA0_Lock_WIDTH                                     1
#define D18F1xA0_Lock_MASK                                      0x8
#define D18F1xA0_Reserved_7_4_OFFSET                            4
#define D18F1xA0_Reserved_7_4_WIDTH                             4
#define D18F1xA0_Reserved_7_4_MASK                              0xf0
#define D18F1xA0_MMIOBase_39_16__OFFSET                         8
#define D18F1xA0_MMIOBase_39_16__WIDTH                          24
#define D18F1xA0_MMIOBase_39_16__MASK                           0xffffff00

/// D18F1xA0
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                                     Lock:1 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                          MMIOBase_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xA0_STRUCT;

// **** D18F1xA4 Register Definition ****
// Address
#define D18F1xA4_ADDRESS                                        0xa4

// Type
#define D18F1xA4_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xA4_DstNode_OFFSET                                 0
#define D18F1xA4_DstNode_WIDTH                                  3
#define D18F1xA4_DstNode_MASK                                   0x7
#define D18F1xA4_Reserved_3_3_OFFSET                            3
#define D18F1xA4_Reserved_3_3_WIDTH                             1
#define D18F1xA4_Reserved_3_3_MASK                              0x8
#define D18F1xA4_DstLink_OFFSET                                 4
#define D18F1xA4_DstLink_WIDTH                                  2
#define D18F1xA4_DstLink_MASK                                   0x30
#define D18F1xA4_DstSubLink_OFFSET                              6
#define D18F1xA4_DstSubLink_WIDTH                               1
#define D18F1xA4_DstSubLink_MASK                                0x40
#define D18F1xA4_NP_OFFSET                                      7
#define D18F1xA4_NP_WIDTH                                       1
#define D18F1xA4_NP_MASK                                        0x80
#define D18F1xA4_MMIOLimit_39_16__OFFSET                        8
#define D18F1xA4_MMIOLimit_39_16__WIDTH                         24
#define D18F1xA4_MMIOLimit_39_16__MASK                          0xffffff00

/// D18F1xA4
typedef union {
  struct {                                                              ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                  DstLink:2 ; ///<
    UINT32                                               DstSubLink:1 ; ///<
    UINT32                                                       NP:1 ; ///<
    UINT32                                         MMIOLimit_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xA4_STRUCT;

// **** D18F1xA8 Register Definition ****
// Address
#define D18F1xA8_ADDRESS                                        0xa8

// Type
#define D18F1xA8_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xA8_RE_OFFSET                                      0
#define D18F1xA8_RE_WIDTH                                       1
#define D18F1xA8_RE_MASK                                        0x1
#define D18F1xA8_WE_OFFSET                                      1
#define D18F1xA8_WE_WIDTH                                       1
#define D18F1xA8_WE_MASK                                        0x2
#define D18F1xA8_Reserved_2_2_OFFSET                            2
#define D18F1xA8_Reserved_2_2_WIDTH                             1
#define D18F1xA8_Reserved_2_2_MASK                              0x4
#define D18F1xA8_Lock_OFFSET                                    3
#define D18F1xA8_Lock_WIDTH                                     1
#define D18F1xA8_Lock_MASK                                      0x8
#define D18F1xA8_Reserved_7_4_OFFSET                            4
#define D18F1xA8_Reserved_7_4_WIDTH                             4
#define D18F1xA8_Reserved_7_4_MASK                              0xf0
#define D18F1xA8_MMIOBase_39_16__OFFSET                         8
#define D18F1xA8_MMIOBase_39_16__WIDTH                          24
#define D18F1xA8_MMIOBase_39_16__MASK                           0xffffff00

/// D18F1xA8
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                                     Lock:1 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                          MMIOBase_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xA8_STRUCT;

// **** D18F1xAC Register Definition ****
// Address
#define D18F1xAC_ADDRESS                                        0xac

// Type
#define D18F1xAC_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xAC_DstNode_OFFSET                                 0
#define D18F1xAC_DstNode_WIDTH                                  3
#define D18F1xAC_DstNode_MASK                                   0x7
#define D18F1xAC_Reserved_3_3_OFFSET                            3
#define D18F1xAC_Reserved_3_3_WIDTH                             1
#define D18F1xAC_Reserved_3_3_MASK                              0x8
#define D18F1xAC_DstLink_OFFSET                                 4
#define D18F1xAC_DstLink_WIDTH                                  2
#define D18F1xAC_DstLink_MASK                                   0x30
#define D18F1xAC_DstSubLink_OFFSET                              6
#define D18F1xAC_DstSubLink_WIDTH                               1
#define D18F1xAC_DstSubLink_MASK                                0x40
#define D18F1xAC_NP_OFFSET                                      7
#define D18F1xAC_NP_WIDTH                                       1
#define D18F1xAC_NP_MASK                                        0x80
#define D18F1xAC_MMIOLimit_39_16__OFFSET                        8
#define D18F1xAC_MMIOLimit_39_16__WIDTH                         24
#define D18F1xAC_MMIOLimit_39_16__MASK                          0xffffff00

/// D18F1xAC
typedef union {
  struct {                                                              ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                  DstLink:2 ; ///<
    UINT32                                               DstSubLink:1 ; ///<
    UINT32                                                       NP:1 ; ///<
    UINT32                                         MMIOLimit_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xAC_STRUCT;

// **** D18F1xB0 Register Definition ****
// Address
#define D18F1xB0_ADDRESS                                        0xb0

// Type
#define D18F1xB0_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xB0_RE_OFFSET                                      0
#define D18F1xB0_RE_WIDTH                                       1
#define D18F1xB0_RE_MASK                                        0x1
#define D18F1xB0_WE_OFFSET                                      1
#define D18F1xB0_WE_WIDTH                                       1
#define D18F1xB0_WE_MASK                                        0x2
#define D18F1xB0_Reserved_2_2_OFFSET                            2
#define D18F1xB0_Reserved_2_2_WIDTH                             1
#define D18F1xB0_Reserved_2_2_MASK                              0x4
#define D18F1xB0_Lock_OFFSET                                    3
#define D18F1xB0_Lock_WIDTH                                     1
#define D18F1xB0_Lock_MASK                                      0x8
#define D18F1xB0_Reserved_7_4_OFFSET                            4
#define D18F1xB0_Reserved_7_4_WIDTH                             4
#define D18F1xB0_Reserved_7_4_MASK                              0xf0
#define D18F1xB0_MMIOBase_39_16__OFFSET                         8
#define D18F1xB0_MMIOBase_39_16__WIDTH                          24
#define D18F1xB0_MMIOBase_39_16__MASK                           0xffffff00

/// D18F1xB0
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                                     Lock:1 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                          MMIOBase_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xB0_STRUCT;

// **** D18F1xB4 Register Definition ****
// Address
#define D18F1xB4_ADDRESS                                        0xb4

// Type
#define D18F1xB4_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xB4_DstNode_OFFSET                                 0
#define D18F1xB4_DstNode_WIDTH                                  3
#define D18F1xB4_DstNode_MASK                                   0x7
#define D18F1xB4_Reserved_3_3_OFFSET                            3
#define D18F1xB4_Reserved_3_3_WIDTH                             1
#define D18F1xB4_Reserved_3_3_MASK                              0x8
#define D18F1xB4_DstLink_OFFSET                                 4
#define D18F1xB4_DstLink_WIDTH                                  2
#define D18F1xB4_DstLink_MASK                                   0x30
#define D18F1xB4_DstSubLink_OFFSET                              6
#define D18F1xB4_DstSubLink_WIDTH                               1
#define D18F1xB4_DstSubLink_MASK                                0x40
#define D18F1xB4_NP_OFFSET                                      7
#define D18F1xB4_NP_WIDTH                                       1
#define D18F1xB4_NP_MASK                                        0x80
#define D18F1xB4_MMIOLimit_39_16__OFFSET                        8
#define D18F1xB4_MMIOLimit_39_16__WIDTH                         24
#define D18F1xB4_MMIOLimit_39_16__MASK                          0xffffff00

/// D18F1xB4
typedef union {
  struct {                                                              ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                  DstLink:2 ; ///<
    UINT32                                               DstSubLink:1 ; ///<
    UINT32                                                       NP:1 ; ///<
    UINT32                                         MMIOLimit_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xB4_STRUCT;

// **** D18F1xB8 Register Definition ****
// Address
#define D18F1xB8_ADDRESS                                        0xb8

// Type
#define D18F1xB8_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xB8_RE_OFFSET                                      0
#define D18F1xB8_RE_WIDTH                                       1
#define D18F1xB8_RE_MASK                                        0x1
#define D18F1xB8_WE_OFFSET                                      1
#define D18F1xB8_WE_WIDTH                                       1
#define D18F1xB8_WE_MASK                                        0x2
#define D18F1xB8_Reserved_2_2_OFFSET                            2
#define D18F1xB8_Reserved_2_2_WIDTH                             1
#define D18F1xB8_Reserved_2_2_MASK                              0x4
#define D18F1xB8_Lock_OFFSET                                    3
#define D18F1xB8_Lock_WIDTH                                     1
#define D18F1xB8_Lock_MASK                                      0x8
#define D18F1xB8_Reserved_7_4_OFFSET                            4
#define D18F1xB8_Reserved_7_4_WIDTH                             4
#define D18F1xB8_Reserved_7_4_MASK                              0xf0
#define D18F1xB8_MMIOBase_39_16__OFFSET                         8
#define D18F1xB8_MMIOBase_39_16__WIDTH                          24
#define D18F1xB8_MMIOBase_39_16__MASK                           0xffffff00

/// D18F1xB8
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                                     Lock:1 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                          MMIOBase_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xB8_STRUCT;

// **** D18F1xBC Register Definition ****
// Address
#define D18F1xBC_ADDRESS                                        0xbc

// Type
#define D18F1xBC_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xBC_DstNode_OFFSET                                 0
#define D18F1xBC_DstNode_WIDTH                                  3
#define D18F1xBC_DstNode_MASK                                   0x7
#define D18F1xBC_Reserved_3_3_OFFSET                            3
#define D18F1xBC_Reserved_3_3_WIDTH                             1
#define D18F1xBC_Reserved_3_3_MASK                              0x8
#define D18F1xBC_DstLink_OFFSET                                 4
#define D18F1xBC_DstLink_WIDTH                                  2
#define D18F1xBC_DstLink_MASK                                   0x30
#define D18F1xBC_DstSubLink_OFFSET                              6
#define D18F1xBC_DstSubLink_WIDTH                               1
#define D18F1xBC_DstSubLink_MASK                                0x40
#define D18F1xBC_NP_OFFSET                                      7
#define D18F1xBC_NP_WIDTH                                       1
#define D18F1xBC_NP_MASK                                        0x80
#define D18F1xBC_MMIOLimit_39_16__OFFSET                        8
#define D18F1xBC_MMIOLimit_39_16__WIDTH                         24
#define D18F1xBC_MMIOLimit_39_16__MASK                          0xffffff00

/// D18F1xBC
typedef union {
  struct {                                                              ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                  DstLink:2 ; ///<
    UINT32                                               DstSubLink:1 ; ///<
    UINT32                                                       NP:1 ; ///<
    UINT32                                         MMIOLimit_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xBC_STRUCT;

// **** D18F1xC0 Register Definition ****
// Address
#define D18F1xC0_ADDRESS                                        0xc0

// Type
#define D18F1xC0_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xC0_RE_OFFSET                                      0
#define D18F1xC0_RE_WIDTH                                       1
#define D18F1xC0_RE_MASK                                        0x1
#define D18F1xC0_WE_OFFSET                                      1
#define D18F1xC0_WE_WIDTH                                       1
#define D18F1xC0_WE_MASK                                        0x2
#define D18F1xC0_Reserved_3_2_OFFSET                            2
#define D18F1xC0_Reserved_3_2_WIDTH                             2
#define D18F1xC0_Reserved_3_2_MASK                              0xc
#define D18F1xC0_VE_OFFSET                                      4
#define D18F1xC0_VE_WIDTH                                       1
#define D18F1xC0_VE_MASK                                        0x10
#define D18F1xC0_IE_OFFSET                                      5
#define D18F1xC0_IE_WIDTH                                       1
#define D18F1xC0_IE_MASK                                        0x20
#define D18F1xC0_Reserved_11_6_OFFSET                           6
#define D18F1xC0_Reserved_11_6_WIDTH                            6
#define D18F1xC0_Reserved_11_6_MASK                             0xfc0
#define D18F1xC0_IOBase_24_12__OFFSET                           12
#define D18F1xC0_IOBase_24_12__WIDTH                            13
#define D18F1xC0_IOBase_24_12__MASK                             0x1fff000
#define D18F1xC0_Reserved_31_25_OFFSET                          25
#define D18F1xC0_Reserved_31_25_WIDTH                           7
#define D18F1xC0_Reserved_31_25_MASK                            0xfe000000

/// D18F1xC0
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                             Reserved_3_2:2 ; ///<
    UINT32                                                       VE:1 ; ///<
    UINT32                                                       IE:1 ; ///<
    UINT32                                            Reserved_11_6:6 ; ///<
    UINT32                                            IOBase_24_12_:13; ///<
    UINT32                                           Reserved_31_25:7 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xC0_STRUCT;

// **** D18F1xC4 Register Definition ****
// Address
#define D18F1xC4_ADDRESS                                        0xc4

// Type
#define D18F1xC4_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xC4_DstNode_OFFSET                                 0
#define D18F1xC4_DstNode_WIDTH                                  3
#define D18F1xC4_DstNode_MASK                                   0x7
#define D18F1xC4_Reserved_3_3_OFFSET                            3
#define D18F1xC4_Reserved_3_3_WIDTH                             1
#define D18F1xC4_Reserved_3_3_MASK                              0x8
#define D18F1xC4_DstLink_OFFSET                                 4
#define D18F1xC4_DstLink_WIDTH                                  2
#define D18F1xC4_DstLink_MASK                                   0x30
#define D18F1xC4_DstSubLink_OFFSET                              6
#define D18F1xC4_DstSubLink_WIDTH                               1
#define D18F1xC4_DstSubLink_MASK                                0x40
#define D18F1xC4_Reserved_11_7_OFFSET                           7
#define D18F1xC4_Reserved_11_7_WIDTH                            5
#define D18F1xC4_Reserved_11_7_MASK                             0xf80
#define D18F1xC4_IOLimit_24_12__OFFSET                          12
#define D18F1xC4_IOLimit_24_12__WIDTH                           13
#define D18F1xC4_IOLimit_24_12__MASK                            0x1fff000
#define D18F1xC4_Reserved_31_25_OFFSET                          25
#define D18F1xC4_Reserved_31_25_WIDTH                           7
#define D18F1xC4_Reserved_31_25_MASK                            0xfe000000

/// D18F1xC4
typedef union {
  struct {                                                              ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                  DstLink:2 ; ///<
    UINT32                                               DstSubLink:1 ; ///<
    UINT32                                            Reserved_11_7:5 ; ///<
    UINT32                                           IOLimit_24_12_:13; ///<
    UINT32                                           Reserved_31_25:7 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xC4_STRUCT;

// **** D18F1xC8 Register Definition ****
// Address
#define D18F1xC8_ADDRESS                                        0xc8

// Type
#define D18F1xC8_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xC8_RE_OFFSET                                      0
#define D18F1xC8_RE_WIDTH                                       1
#define D18F1xC8_RE_MASK                                        0x1
#define D18F1xC8_WE_OFFSET                                      1
#define D18F1xC8_WE_WIDTH                                       1
#define D18F1xC8_WE_MASK                                        0x2
#define D18F1xC8_Reserved_3_2_OFFSET                            2
#define D18F1xC8_Reserved_3_2_WIDTH                             2
#define D18F1xC8_Reserved_3_2_MASK                              0xc
#define D18F1xC8_VE_OFFSET                                      4
#define D18F1xC8_VE_WIDTH                                       1
#define D18F1xC8_VE_MASK                                        0x10
#define D18F1xC8_IE_OFFSET                                      5
#define D18F1xC8_IE_WIDTH                                       1
#define D18F1xC8_IE_MASK                                        0x20
#define D18F1xC8_Reserved_11_6_OFFSET                           6
#define D18F1xC8_Reserved_11_6_WIDTH                            6
#define D18F1xC8_Reserved_11_6_MASK                             0xfc0
#define D18F1xC8_IOBase_24_12__OFFSET                           12
#define D18F1xC8_IOBase_24_12__WIDTH                            13
#define D18F1xC8_IOBase_24_12__MASK                             0x1fff000
#define D18F1xC8_Reserved_31_25_OFFSET                          25
#define D18F1xC8_Reserved_31_25_WIDTH                           7
#define D18F1xC8_Reserved_31_25_MASK                            0xfe000000

/// D18F1xC8
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                             Reserved_3_2:2 ; ///<
    UINT32                                                       VE:1 ; ///<
    UINT32                                                       IE:1 ; ///<
    UINT32                                            Reserved_11_6:6 ; ///<
    UINT32                                            IOBase_24_12_:13; ///<
    UINT32                                           Reserved_31_25:7 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xC8_STRUCT;

// **** D18F1xCC Register Definition ****
// Address
#define D18F1xCC_ADDRESS                                        0xcc

// Type
#define D18F1xCC_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xCC_DstNode_OFFSET                                 0
#define D18F1xCC_DstNode_WIDTH                                  3
#define D18F1xCC_DstNode_MASK                                   0x7
#define D18F1xCC_Reserved_3_3_OFFSET                            3
#define D18F1xCC_Reserved_3_3_WIDTH                             1
#define D18F1xCC_Reserved_3_3_MASK                              0x8
#define D18F1xCC_DstLink_OFFSET                                 4
#define D18F1xCC_DstLink_WIDTH                                  2
#define D18F1xCC_DstLink_MASK                                   0x30
#define D18F1xCC_DstSubLink_OFFSET                              6
#define D18F1xCC_DstSubLink_WIDTH                               1
#define D18F1xCC_DstSubLink_MASK                                0x40
#define D18F1xCC_Reserved_11_7_OFFSET                           7
#define D18F1xCC_Reserved_11_7_WIDTH                            5
#define D18F1xCC_Reserved_11_7_MASK                             0xf80
#define D18F1xCC_IOLimit_24_12__OFFSET                          12
#define D18F1xCC_IOLimit_24_12__WIDTH                           13
#define D18F1xCC_IOLimit_24_12__MASK                            0x1fff000
#define D18F1xCC_Reserved_31_25_OFFSET                          25
#define D18F1xCC_Reserved_31_25_WIDTH                           7
#define D18F1xCC_Reserved_31_25_MASK                            0xfe000000

/// D18F1xCC
typedef union {
  struct {                                                              ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                  DstLink:2 ; ///<
    UINT32                                               DstSubLink:1 ; ///<
    UINT32                                            Reserved_11_7:5 ; ///<
    UINT32                                           IOLimit_24_12_:13; ///<
    UINT32                                           Reserved_31_25:7 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xCC_STRUCT;

// **** D18F1xD0 Register Definition ****
// Address
#define D18F1xD0_ADDRESS                                        0xd0

// Type
#define D18F1xD0_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xD0_RE_OFFSET                                      0
#define D18F1xD0_RE_WIDTH                                       1
#define D18F1xD0_RE_MASK                                        0x1
#define D18F1xD0_WE_OFFSET                                      1
#define D18F1xD0_WE_WIDTH                                       1
#define D18F1xD0_WE_MASK                                        0x2
#define D18F1xD0_Reserved_3_2_OFFSET                            2
#define D18F1xD0_Reserved_3_2_WIDTH                             2
#define D18F1xD0_Reserved_3_2_MASK                              0xc
#define D18F1xD0_VE_OFFSET                                      4
#define D18F1xD0_VE_WIDTH                                       1
#define D18F1xD0_VE_MASK                                        0x10
#define D18F1xD0_IE_OFFSET                                      5
#define D18F1xD0_IE_WIDTH                                       1
#define D18F1xD0_IE_MASK                                        0x20
#define D18F1xD0_Reserved_11_6_OFFSET                           6
#define D18F1xD0_Reserved_11_6_WIDTH                            6
#define D18F1xD0_Reserved_11_6_MASK                             0xfc0
#define D18F1xD0_IOBase_24_12__OFFSET                           12
#define D18F1xD0_IOBase_24_12__WIDTH                            13
#define D18F1xD0_IOBase_24_12__MASK                             0x1fff000
#define D18F1xD0_Reserved_31_25_OFFSET                          25
#define D18F1xD0_Reserved_31_25_WIDTH                           7
#define D18F1xD0_Reserved_31_25_MASK                            0xfe000000

/// D18F1xD0
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                             Reserved_3_2:2 ; ///<
    UINT32                                                       VE:1 ; ///<
    UINT32                                                       IE:1 ; ///<
    UINT32                                            Reserved_11_6:6 ; ///<
    UINT32                                            IOBase_24_12_:13; ///<
    UINT32                                           Reserved_31_25:7 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xD0_STRUCT;

// **** D18F1xD4 Register Definition ****
// Address
#define D18F1xD4_ADDRESS                                        0xd4

// Type
#define D18F1xD4_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xD4_DstNode_OFFSET                                 0
#define D18F1xD4_DstNode_WIDTH                                  3
#define D18F1xD4_DstNode_MASK                                   0x7
#define D18F1xD4_Reserved_3_3_OFFSET                            3
#define D18F1xD4_Reserved_3_3_WIDTH                             1
#define D18F1xD4_Reserved_3_3_MASK                              0x8
#define D18F1xD4_DstLink_OFFSET                                 4
#define D18F1xD4_DstLink_WIDTH                                  2
#define D18F1xD4_DstLink_MASK                                   0x30
#define D18F1xD4_DstSubLink_OFFSET                              6
#define D18F1xD4_DstSubLink_WIDTH                               1
#define D18F1xD4_DstSubLink_MASK                                0x40
#define D18F1xD4_Reserved_11_7_OFFSET                           7
#define D18F1xD4_Reserved_11_7_WIDTH                            5
#define D18F1xD4_Reserved_11_7_MASK                             0xf80
#define D18F1xD4_IOLimit_24_12__OFFSET                          12
#define D18F1xD4_IOLimit_24_12__WIDTH                           13
#define D18F1xD4_IOLimit_24_12__MASK                            0x1fff000
#define D18F1xD4_Reserved_31_25_OFFSET                          25
#define D18F1xD4_Reserved_31_25_WIDTH                           7
#define D18F1xD4_Reserved_31_25_MASK                            0xfe000000

/// D18F1xD4
typedef union {
  struct {                                                              ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                  DstLink:2 ; ///<
    UINT32                                               DstSubLink:1 ; ///<
    UINT32                                            Reserved_11_7:5 ; ///<
    UINT32                                           IOLimit_24_12_:13; ///<
    UINT32                                           Reserved_31_25:7 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xD4_STRUCT;

// **** D18F1xD8 Register Definition ****
// Address
#define D18F1xD8_ADDRESS                                        0xd8

// Type
#define D18F1xD8_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xD8_RE_OFFSET                                      0
#define D18F1xD8_RE_WIDTH                                       1
#define D18F1xD8_RE_MASK                                        0x1
#define D18F1xD8_WE_OFFSET                                      1
#define D18F1xD8_WE_WIDTH                                       1
#define D18F1xD8_WE_MASK                                        0x2
#define D18F1xD8_Reserved_3_2_OFFSET                            2
#define D18F1xD8_Reserved_3_2_WIDTH                             2
#define D18F1xD8_Reserved_3_2_MASK                              0xc
#define D18F1xD8_VE_OFFSET                                      4
#define D18F1xD8_VE_WIDTH                                       1
#define D18F1xD8_VE_MASK                                        0x10
#define D18F1xD8_IE_OFFSET                                      5
#define D18F1xD8_IE_WIDTH                                       1
#define D18F1xD8_IE_MASK                                        0x20
#define D18F1xD8_Reserved_11_6_OFFSET                           6
#define D18F1xD8_Reserved_11_6_WIDTH                            6
#define D18F1xD8_Reserved_11_6_MASK                             0xfc0
#define D18F1xD8_IOBase_24_12__OFFSET                           12
#define D18F1xD8_IOBase_24_12__WIDTH                            13
#define D18F1xD8_IOBase_24_12__MASK                             0x1fff000
#define D18F1xD8_Reserved_31_25_OFFSET                          25
#define D18F1xD8_Reserved_31_25_WIDTH                           7
#define D18F1xD8_Reserved_31_25_MASK                            0xfe000000

/// D18F1xD8
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                             Reserved_3_2:2 ; ///<
    UINT32                                                       VE:1 ; ///<
    UINT32                                                       IE:1 ; ///<
    UINT32                                            Reserved_11_6:6 ; ///<
    UINT32                                            IOBase_24_12_:13; ///<
    UINT32                                           Reserved_31_25:7 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xD8_STRUCT;

// **** D18F1xDC Register Definition ****
// Address
#define D18F1xDC_ADDRESS                                        0xdc

// Type
#define D18F1xDC_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xDC_DstNode_OFFSET                                 0
#define D18F1xDC_DstNode_WIDTH                                  3
#define D18F1xDC_DstNode_MASK                                   0x7
#define D18F1xDC_Reserved_3_3_OFFSET                            3
#define D18F1xDC_Reserved_3_3_WIDTH                             1
#define D18F1xDC_Reserved_3_3_MASK                              0x8
#define D18F1xDC_DstLink_OFFSET                                 4
#define D18F1xDC_DstLink_WIDTH                                  2
#define D18F1xDC_DstLink_MASK                                   0x30
#define D18F1xDC_DstSubLink_OFFSET                              6
#define D18F1xDC_DstSubLink_WIDTH                               1
#define D18F1xDC_DstSubLink_MASK                                0x40
#define D18F1xDC_Reserved_11_7_OFFSET                           7
#define D18F1xDC_Reserved_11_7_WIDTH                            5
#define D18F1xDC_Reserved_11_7_MASK                             0xf80
#define D18F1xDC_IOLimit_24_12__OFFSET                          12
#define D18F1xDC_IOLimit_24_12__WIDTH                           13
#define D18F1xDC_IOLimit_24_12__MASK                            0x1fff000
#define D18F1xDC_Reserved_31_25_OFFSET                          25
#define D18F1xDC_Reserved_31_25_WIDTH                           7
#define D18F1xDC_Reserved_31_25_MASK                            0xfe000000

/// D18F1xDC
typedef union {
  struct {                                                              ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                  DstLink:2 ; ///<
    UINT32                                               DstSubLink:1 ; ///<
    UINT32                                            Reserved_11_7:5 ; ///<
    UINT32                                           IOLimit_24_12_:13; ///<
    UINT32                                           Reserved_31_25:7 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xDC_STRUCT;

// **** D18F1xE0 Register Definition ****
// Address
#define D18F1xE0_ADDRESS                                        0xe0

// Type
#define D18F1xE0_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xE0_RE_OFFSET                                      0
#define D18F1xE0_RE_WIDTH                                       1
#define D18F1xE0_RE_MASK                                        0x1
#define D18F1xE0_WE_OFFSET                                      1
#define D18F1xE0_WE_WIDTH                                       1
#define D18F1xE0_WE_MASK                                        0x2
#define D18F1xE0_DevCmpEn_OFFSET                                2
#define D18F1xE0_DevCmpEn_WIDTH                                 1
#define D18F1xE0_DevCmpEn_MASK                                  0x4
#define D18F1xE0_Reserved_15_3_OFFSET                           3
#define D18F1xE0_Reserved_15_3_WIDTH                            13
#define D18F1xE0_Reserved_15_3_MASK                             0xfff8
#define D18F1xE0_BusNumBase_7_0__OFFSET                         16
#define D18F1xE0_BusNumBase_7_0__WIDTH                          8
#define D18F1xE0_BusNumBase_7_0__MASK                           0xff0000
#define D18F1xE0_BusNumLimit_7_0__OFFSET                        24
#define D18F1xE0_BusNumLimit_7_0__WIDTH                         8
#define D18F1xE0_BusNumLimit_7_0__MASK                          0xff000000

/// D18F1xE0
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                                 DevCmpEn:1 ; ///<
    UINT32                                            Reserved_15_3:13; ///<
    UINT32                                          BusNumBase_7_0_:8 ; ///<
    UINT32                                         BusNumLimit_7_0_:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xE0_STRUCT;

// **** D18F1xE4 Register Definition ****
// Address
#define D18F1xE4_ADDRESS                                        0xe4

// Type
#define D18F1xE4_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xE4_RE_OFFSET                                      0
#define D18F1xE4_RE_WIDTH                                       1
#define D18F1xE4_RE_MASK                                        0x1
#define D18F1xE4_WE_OFFSET                                      1
#define D18F1xE4_WE_WIDTH                                       1
#define D18F1xE4_WE_MASK                                        0x2
#define D18F1xE4_DevCmpEn_OFFSET                                2
#define D18F1xE4_DevCmpEn_WIDTH                                 1
#define D18F1xE4_DevCmpEn_MASK                                  0x4
#define D18F1xE4_Reserved_15_3_OFFSET                           3
#define D18F1xE4_Reserved_15_3_WIDTH                            13
#define D18F1xE4_Reserved_15_3_MASK                             0xfff8
#define D18F1xE4_BusNumBase_7_0__OFFSET                         16
#define D18F1xE4_BusNumBase_7_0__WIDTH                          8
#define D18F1xE4_BusNumBase_7_0__MASK                           0xff0000
#define D18F1xE4_BusNumLimit_7_0__OFFSET                        24
#define D18F1xE4_BusNumLimit_7_0__WIDTH                         8
#define D18F1xE4_BusNumLimit_7_0__MASK                          0xff000000

/// D18F1xE4
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                                 DevCmpEn:1 ; ///<
    UINT32                                            Reserved_15_3:13; ///<
    UINT32                                          BusNumBase_7_0_:8 ; ///<
    UINT32                                         BusNumLimit_7_0_:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xE4_STRUCT;

// **** D18F1xE8 Register Definition ****
// Address
#define D18F1xE8_ADDRESS                                        0xe8

// Type
#define D18F1xE8_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xE8_RE_OFFSET                                      0
#define D18F1xE8_RE_WIDTH                                       1
#define D18F1xE8_RE_MASK                                        0x1
#define D18F1xE8_WE_OFFSET                                      1
#define D18F1xE8_WE_WIDTH                                       1
#define D18F1xE8_WE_MASK                                        0x2
#define D18F1xE8_DevCmpEn_OFFSET                                2
#define D18F1xE8_DevCmpEn_WIDTH                                 1
#define D18F1xE8_DevCmpEn_MASK                                  0x4
#define D18F1xE8_Reserved_15_3_OFFSET                           3
#define D18F1xE8_Reserved_15_3_WIDTH                            13
#define D18F1xE8_Reserved_15_3_MASK                             0xfff8
#define D18F1xE8_BusNumBase_7_0__OFFSET                         16
#define D18F1xE8_BusNumBase_7_0__WIDTH                          8
#define D18F1xE8_BusNumBase_7_0__MASK                           0xff0000
#define D18F1xE8_BusNumLimit_7_0__OFFSET                        24
#define D18F1xE8_BusNumLimit_7_0__WIDTH                         8
#define D18F1xE8_BusNumLimit_7_0__MASK                          0xff000000

/// D18F1xE8
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                                 DevCmpEn:1 ; ///<
    UINT32                                            Reserved_15_3:13; ///<
    UINT32                                          BusNumBase_7_0_:8 ; ///<
    UINT32                                         BusNumLimit_7_0_:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xE8_STRUCT;

// **** D18F1xEC Register Definition ****
// Address
#define D18F1xEC_ADDRESS                                        0xec

// Type
#define D18F1xEC_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xEC_RE_OFFSET                                      0
#define D18F1xEC_RE_WIDTH                                       1
#define D18F1xEC_RE_MASK                                        0x1
#define D18F1xEC_WE_OFFSET                                      1
#define D18F1xEC_WE_WIDTH                                       1
#define D18F1xEC_WE_MASK                                        0x2
#define D18F1xEC_DevCmpEn_OFFSET                                2
#define D18F1xEC_DevCmpEn_WIDTH                                 1
#define D18F1xEC_DevCmpEn_MASK                                  0x4
#define D18F1xEC_Reserved_15_3_OFFSET                           3
#define D18F1xEC_Reserved_15_3_WIDTH                            13
#define D18F1xEC_Reserved_15_3_MASK                             0xfff8
#define D18F1xEC_BusNumBase_7_0__OFFSET                         16
#define D18F1xEC_BusNumBase_7_0__WIDTH                          8
#define D18F1xEC_BusNumBase_7_0__MASK                           0xff0000
#define D18F1xEC_BusNumLimit_7_0__OFFSET                        24
#define D18F1xEC_BusNumLimit_7_0__WIDTH                         8
#define D18F1xEC_BusNumLimit_7_0__MASK                          0xff000000

/// D18F1xEC
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                                 DevCmpEn:1 ; ///<
    UINT32                                            Reserved_15_3:13; ///<
    UINT32                                          BusNumBase_7_0_:8 ; ///<
    UINT32                                         BusNumLimit_7_0_:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xEC_STRUCT;

// **** D18F1xF0 Register Definition ****
// Address
#define D18F1xF0_ADDRESS                                        0xf0

// Type
#define D18F1xF0_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xF0_DramHoleValid_OFFSET                           0
#define D18F1xF0_DramHoleValid_WIDTH                            1
#define D18F1xF0_DramHoleValid_MASK                             0x1
#define D18F1xF0_DramMemHoistValid_OFFSET                       1
#define D18F1xF0_DramMemHoistValid_WIDTH                        1
#define D18F1xF0_DramMemHoistValid_MASK                         0x2
#define D18F1xF0_Reserved_2_2_OFFSET                            2
#define D18F1xF0_Reserved_2_2_WIDTH                             1
#define D18F1xF0_Reserved_2_2_MASK                              0x4
#define D18F1xF0_Reserved_6_3_OFFSET                            3
#define D18F1xF0_Reserved_6_3_WIDTH                             4
#define D18F1xF0_Reserved_6_3_MASK                              0x78
#define D18F1xF0_DramHoleOffset_31_23__OFFSET                   7
#define D18F1xF0_DramHoleOffset_31_23__WIDTH                    9
#define D18F1xF0_DramHoleOffset_31_23__MASK                     0xff80
#define D18F1xF0_Reserved_23_16_OFFSET                          16
#define D18F1xF0_Reserved_23_16_WIDTH                           8
#define D18F1xF0_Reserved_23_16_MASK                            0xff0000
#define D18F1xF0_DramHoleBase_31_24__OFFSET                     24
#define D18F1xF0_DramHoleBase_31_24__WIDTH                      8
#define D18F1xF0_DramHoleBase_31_24__MASK                       0xff000000

/// D18F1xF0
typedef union {
  struct {                                                              ///<
    UINT32                                            DramHoleValid:1 ; ///<
    UINT32                                        DramMemHoistValid:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                             Reserved_6_3:4 ; ///<
    UINT32                                    DramHoleOffset_31_23_:9 ; ///<
    UINT32                                           Reserved_23_16:8 ; ///<
    UINT32                                      DramHoleBase_31_24_:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xF0_STRUCT;

// **** D18F1xF4 Register Definition ****
// Address
#define D18F1xF4_ADDRESS                                        0xf4

// Type
#define D18F1xF4_TYPE                                           TYPE_D18F1
// Field Data
#define D18F1xF4_VE_OFFSET                                      0
#define D18F1xF4_VE_WIDTH                                       1
#define D18F1xF4_VE_MASK                                        0x1
#define D18F1xF4_NP_OFFSET                                      1
#define D18F1xF4_NP_WIDTH                                       1
#define D18F1xF4_NP_MASK                                        0x2
#define D18F1xF4_Reserved_2_2_OFFSET                            2
#define D18F1xF4_Reserved_2_2_WIDTH                             1
#define D18F1xF4_Reserved_2_2_MASK                              0x4
#define D18F1xF4_Lock_OFFSET                                    3
#define D18F1xF4_Lock_WIDTH                                     1
#define D18F1xF4_Lock_MASK                                      0x8
#define D18F1xF4_DstNode_OFFSET                                 4
#define D18F1xF4_DstNode_WIDTH                                  3
#define D18F1xF4_DstNode_MASK                                   0x70
#define D18F1xF4_Reserved_11_7_OFFSET                           7
#define D18F1xF4_Reserved_11_7_WIDTH                            5
#define D18F1xF4_Reserved_11_7_MASK                             0xf80
#define D18F1xF4_DstLink_OFFSET                                 12
#define D18F1xF4_DstLink_WIDTH                                  2
#define D18F1xF4_DstLink_MASK                                   0x3000
#define D18F1xF4_DstSubLink_OFFSET                              14
#define D18F1xF4_DstSubLink_WIDTH                               1
#define D18F1xF4_DstSubLink_MASK                                0x4000
#define D18F1xF4_Reserved_31_15_OFFSET                          15
#define D18F1xF4_Reserved_31_15_WIDTH                           17
#define D18F1xF4_Reserved_31_15_MASK                            0xffff8000

/// D18F1xF4
typedef union {
  struct {                                                              ///<
    UINT32                                                       VE:1 ; ///<
    UINT32                                                       NP:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                                     Lock:1 ; ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                            Reserved_11_7:5 ; ///<
    UINT32                                                  DstLink:2 ; ///<
    UINT32                                               DstSubLink:1 ; ///<
    UINT32                                           Reserved_31_15:17; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1xF4_STRUCT;

// **** D18F1x10C Register Definition ****
// Address
#define D18F1x10C_ADDRESS                                       0x10c

// Type
#define D18F1x10C_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x10C_DctCfgSel_OFFSET                              0
#define D18F1x10C_DctCfgSel_WIDTH                               1
#define D18F1x10C_DctCfgSel_MASK                                0x1
#define D18F1x10C_Reserved_2_1_OFFSET                           1
#define D18F1x10C_Reserved_2_1_WIDTH                            2
#define D18F1x10C_Reserved_2_1_MASK                             0x6
#define D18F1x10C_MemPsSel_OFFSET                               3
#define D18F1x10C_MemPsSel_WIDTH                                1
#define D18F1x10C_MemPsSel_MASK                                 0x8
#define D18F1x10C_NbPsSel_OFFSET                                4
#define D18F1x10C_NbPsSel_WIDTH                                 2
#define D18F1x10C_NbPsSel_MASK                                  0x30
#define D18F1x10C_Unused_31_6_OFFSET                            6
#define D18F1x10C_Unused_31_6_WIDTH                             26
#define D18F1x10C_Unused_31_6_MASK                              0xffffffc0

/// D18F1x10C
typedef union {
  struct {                                                              ///<
    UINT32                                                DctCfgSel:1 ; ///<
    UINT32                                             Reserved_2_1:2 ; ///<
    UINT32                                                 MemPsSel:1 ; ///<
    UINT32                                                  NbPsSel:2 ; ///<
    UINT32                                              Unused_31_6:26; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x10C_STRUCT;

// **** D18F1x120 Register Definition ****
// Address
#define D18F1x120_ADDRESS                                       0x120

// Type
#define D18F1x120_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x120_DramBaseAddr_47_27__OFFSET                    0
#define D18F1x120_DramBaseAddr_47_27__WIDTH                     21
#define D18F1x120_DramBaseAddr_47_27__MASK                      0x1fffff
#define D18F1x120_Reserved_31_21_OFFSET                         21
#define D18F1x120_Reserved_31_21_WIDTH                          11
#define D18F1x120_Reserved_31_21_MASK                           0xffe00000

/// D18F1x120
typedef union {
  struct {                                                              ///<
    UINT32                                      DramBaseAddr_47_27_:21; ///<
    UINT32                                           Reserved_31_21:11; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x120_STRUCT;

// **** D18F1x124 Register Definition ****
// Address
#define D18F1x124_ADDRESS                                       0x124

// Type
#define D18F1x124_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x124_DramLimitAddr_47_27__OFFSET                   0
#define D18F1x124_DramLimitAddr_47_27__WIDTH                    21
#define D18F1x124_DramLimitAddr_47_27__MASK                     0x1fffff
#define D18F1x124_Reserved_31_21_OFFSET                         21
#define D18F1x124_Reserved_31_21_WIDTH                          11
#define D18F1x124_Reserved_31_21_MASK                           0xffe00000

/// D18F1x124
typedef union {
  struct {                                                              ///<
    UINT32                                     DramLimitAddr_47_27_:21; ///<
    UINT32                                           Reserved_31_21:11; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x124_STRUCT;

// **** D18F1x140 Register Definition ****
// Address
#define D18F1x140_ADDRESS                                       0x140

// Type
#define D18F1x140_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x140_DramBase_47_40__OFFSET                        0
#define D18F1x140_DramBase_47_40__WIDTH                         8
#define D18F1x140_DramBase_47_40__MASK                          0xff
#define D18F1x140_Reserved_31_8_OFFSET                          8
#define D18F1x140_Reserved_31_8_WIDTH                           24
#define D18F1x140_Reserved_31_8_MASK                            0xffffff00

/// D18F1x140
typedef union {
  struct {                                                              ///<
    UINT32                                          DramBase_47_40_:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x140_STRUCT;

// **** D18F1x144 Register Definition ****
// Address
#define D18F1x144_ADDRESS                                       0x144

// Type
#define D18F1x144_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x144_DramLimit_47_40__OFFSET                       0
#define D18F1x144_DramLimit_47_40__WIDTH                        8
#define D18F1x144_DramLimit_47_40__MASK                         0xff
#define D18F1x144_Reserved_31_8_OFFSET                          8
#define D18F1x144_Reserved_31_8_WIDTH                           24
#define D18F1x144_Reserved_31_8_MASK                            0xffffff00

/// D18F1x144
typedef union {
  struct {                                                              ///<
    UINT32                                         DramLimit_47_40_:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x144_STRUCT;

// **** D18F1x180 Register Definition ****
// Address
#define D18F1x180_ADDRESS                                       0x180

// Type
#define D18F1x180_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x180_MMIOBase_47_40__OFFSET                        0
#define D18F1x180_MMIOBase_47_40__WIDTH                         8
#define D18F1x180_MMIOBase_47_40__MASK                          0xff
#define D18F1x180_Reserved_15_8_OFFSET                          8
#define D18F1x180_Reserved_15_8_WIDTH                           8
#define D18F1x180_Reserved_15_8_MASK                            0xff00
#define D18F1x180_MMIOLimit_47_40__OFFSET                       16
#define D18F1x180_MMIOLimit_47_40__WIDTH                        8
#define D18F1x180_MMIOLimit_47_40__MASK                         0xff0000
#define D18F1x180_Reserved_31_24_OFFSET                         24
#define D18F1x180_Reserved_31_24_WIDTH                          8
#define D18F1x180_Reserved_31_24_MASK                           0xff000000

/// D18F1x180
typedef union {
  struct {                                                              ///<
    UINT32                                          MMIOBase_47_40_:8 ; ///<
    UINT32                                            Reserved_15_8:8 ; ///<
    UINT32                                         MMIOLimit_47_40_:8 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x180_STRUCT;

// **** D18F1x184 Register Definition ****
// Address
#define D18F1x184_ADDRESS                                       0x184

// Type
#define D18F1x184_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x184_MMIOBase_47_40__OFFSET                        0
#define D18F1x184_MMIOBase_47_40__WIDTH                         8
#define D18F1x184_MMIOBase_47_40__MASK                          0xff
#define D18F1x184_Reserved_15_8_OFFSET                          8
#define D18F1x184_Reserved_15_8_WIDTH                           8
#define D18F1x184_Reserved_15_8_MASK                            0xff00
#define D18F1x184_MMIOLimit_47_40__OFFSET                       16
#define D18F1x184_MMIOLimit_47_40__WIDTH                        8
#define D18F1x184_MMIOLimit_47_40__MASK                         0xff0000
#define D18F1x184_Reserved_31_24_OFFSET                         24
#define D18F1x184_Reserved_31_24_WIDTH                          8
#define D18F1x184_Reserved_31_24_MASK                           0xff000000

/// D18F1x184
typedef union {
  struct {                                                              ///<
    UINT32                                          MMIOBase_47_40_:8 ; ///<
    UINT32                                            Reserved_15_8:8 ; ///<
    UINT32                                         MMIOLimit_47_40_:8 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x184_STRUCT;

// **** D18F1x188 Register Definition ****
// Address
#define D18F1x188_ADDRESS                                       0x188

// Type
#define D18F1x188_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x188_MMIOBase_47_40__OFFSET                        0
#define D18F1x188_MMIOBase_47_40__WIDTH                         8
#define D18F1x188_MMIOBase_47_40__MASK                          0xff
#define D18F1x188_Reserved_15_8_OFFSET                          8
#define D18F1x188_Reserved_15_8_WIDTH                           8
#define D18F1x188_Reserved_15_8_MASK                            0xff00
#define D18F1x188_MMIOLimit_47_40__OFFSET                       16
#define D18F1x188_MMIOLimit_47_40__WIDTH                        8
#define D18F1x188_MMIOLimit_47_40__MASK                         0xff0000
#define D18F1x188_Reserved_31_24_OFFSET                         24
#define D18F1x188_Reserved_31_24_WIDTH                          8
#define D18F1x188_Reserved_31_24_MASK                           0xff000000

/// D18F1x188
typedef union {
  struct {                                                              ///<
    UINT32                                          MMIOBase_47_40_:8 ; ///<
    UINT32                                            Reserved_15_8:8 ; ///<
    UINT32                                         MMIOLimit_47_40_:8 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x188_STRUCT;

// **** D18F1x18C Register Definition ****
// Address
#define D18F1x18C_ADDRESS                                       0x18c

// Type
#define D18F1x18C_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x18C_MMIOBase_47_40__OFFSET                        0
#define D18F1x18C_MMIOBase_47_40__WIDTH                         8
#define D18F1x18C_MMIOBase_47_40__MASK                          0xff
#define D18F1x18C_Reserved_15_8_OFFSET                          8
#define D18F1x18C_Reserved_15_8_WIDTH                           8
#define D18F1x18C_Reserved_15_8_MASK                            0xff00
#define D18F1x18C_MMIOLimit_47_40__OFFSET                       16
#define D18F1x18C_MMIOLimit_47_40__WIDTH                        8
#define D18F1x18C_MMIOLimit_47_40__MASK                         0xff0000
#define D18F1x18C_Reserved_31_24_OFFSET                         24
#define D18F1x18C_Reserved_31_24_WIDTH                          8
#define D18F1x18C_Reserved_31_24_MASK                           0xff000000

/// D18F1x18C
typedef union {
  struct {                                                              ///<
    UINT32                                          MMIOBase_47_40_:8 ; ///<
    UINT32                                            Reserved_15_8:8 ; ///<
    UINT32                                         MMIOLimit_47_40_:8 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x18C_STRUCT;

// **** D18F1x190 Register Definition ****
// Address
#define D18F1x190_ADDRESS                                       0x190

// Type
#define D18F1x190_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x190_MMIOBase_47_40__OFFSET                        0
#define D18F1x190_MMIOBase_47_40__WIDTH                         8
#define D18F1x190_MMIOBase_47_40__MASK                          0xff
#define D18F1x190_Reserved_15_8_OFFSET                          8
#define D18F1x190_Reserved_15_8_WIDTH                           8
#define D18F1x190_Reserved_15_8_MASK                            0xff00
#define D18F1x190_MMIOLimit_47_40__OFFSET                       16
#define D18F1x190_MMIOLimit_47_40__WIDTH                        8
#define D18F1x190_MMIOLimit_47_40__MASK                         0xff0000
#define D18F1x190_Reserved_31_24_OFFSET                         24
#define D18F1x190_Reserved_31_24_WIDTH                          8
#define D18F1x190_Reserved_31_24_MASK                           0xff000000

/// D18F1x190
typedef union {
  struct {                                                              ///<
    UINT32                                          MMIOBase_47_40_:8 ; ///<
    UINT32                                            Reserved_15_8:8 ; ///<
    UINT32                                         MMIOLimit_47_40_:8 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x190_STRUCT;

// **** D18F1x194 Register Definition ****
// Address
#define D18F1x194_ADDRESS                                       0x194

// Type
#define D18F1x194_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x194_MMIOBase_47_40__OFFSET                        0
#define D18F1x194_MMIOBase_47_40__WIDTH                         8
#define D18F1x194_MMIOBase_47_40__MASK                          0xff
#define D18F1x194_Reserved_15_8_OFFSET                          8
#define D18F1x194_Reserved_15_8_WIDTH                           8
#define D18F1x194_Reserved_15_8_MASK                            0xff00
#define D18F1x194_MMIOLimit_47_40__OFFSET                       16
#define D18F1x194_MMIOLimit_47_40__WIDTH                        8
#define D18F1x194_MMIOLimit_47_40__MASK                         0xff0000
#define D18F1x194_Reserved_31_24_OFFSET                         24
#define D18F1x194_Reserved_31_24_WIDTH                          8
#define D18F1x194_Reserved_31_24_MASK                           0xff000000

/// D18F1x194
typedef union {
  struct {                                                              ///<
    UINT32                                          MMIOBase_47_40_:8 ; ///<
    UINT32                                            Reserved_15_8:8 ; ///<
    UINT32                                         MMIOLimit_47_40_:8 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x194_STRUCT;

// **** D18F1x198 Register Definition ****
// Address
#define D18F1x198_ADDRESS                                       0x198

// Type
#define D18F1x198_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x198_MMIOBase_47_40__OFFSET                        0
#define D18F1x198_MMIOBase_47_40__WIDTH                         8
#define D18F1x198_MMIOBase_47_40__MASK                          0xff
#define D18F1x198_Reserved_15_8_OFFSET                          8
#define D18F1x198_Reserved_15_8_WIDTH                           8
#define D18F1x198_Reserved_15_8_MASK                            0xff00
#define D18F1x198_MMIOLimit_47_40__OFFSET                       16
#define D18F1x198_MMIOLimit_47_40__WIDTH                        8
#define D18F1x198_MMIOLimit_47_40__MASK                         0xff0000
#define D18F1x198_Reserved_31_24_OFFSET                         24
#define D18F1x198_Reserved_31_24_WIDTH                          8
#define D18F1x198_Reserved_31_24_MASK                           0xff000000

/// D18F1x198
typedef union {
  struct {                                                              ///<
    UINT32                                          MMIOBase_47_40_:8 ; ///<
    UINT32                                            Reserved_15_8:8 ; ///<
    UINT32                                         MMIOLimit_47_40_:8 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x198_STRUCT;

// **** D18F1x19C Register Definition ****
// Address
#define D18F1x19C_ADDRESS                                       0x19c

// Type
#define D18F1x19C_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x19C_MMIOBase_47_40__OFFSET                        0
#define D18F1x19C_MMIOBase_47_40__WIDTH                         8
#define D18F1x19C_MMIOBase_47_40__MASK                          0xff
#define D18F1x19C_Reserved_15_8_OFFSET                          8
#define D18F1x19C_Reserved_15_8_WIDTH                           8
#define D18F1x19C_Reserved_15_8_MASK                            0xff00
#define D18F1x19C_MMIOLimit_47_40__OFFSET                       16
#define D18F1x19C_MMIOLimit_47_40__WIDTH                        8
#define D18F1x19C_MMIOLimit_47_40__MASK                         0xff0000
#define D18F1x19C_Reserved_31_24_OFFSET                         24
#define D18F1x19C_Reserved_31_24_WIDTH                          8
#define D18F1x19C_Reserved_31_24_MASK                           0xff000000

/// D18F1x19C
typedef union {
  struct {                                                              ///<
    UINT32                                          MMIOBase_47_40_:8 ; ///<
    UINT32                                            Reserved_15_8:8 ; ///<
    UINT32                                         MMIOLimit_47_40_:8 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x19C_STRUCT;

// **** D18F1x1A0 Register Definition ****
// Address
#define D18F1x1A0_ADDRESS                                       0x1a0

// Type
#define D18F1x1A0_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x1A0_RE_OFFSET                                     0
#define D18F1x1A0_RE_WIDTH                                      1
#define D18F1x1A0_RE_MASK                                       0x1
#define D18F1x1A0_WE_OFFSET                                     1
#define D18F1x1A0_WE_WIDTH                                      1
#define D18F1x1A0_WE_MASK                                       0x2
#define D18F1x1A0_Reserved_2_2_OFFSET                           2
#define D18F1x1A0_Reserved_2_2_WIDTH                            1
#define D18F1x1A0_Reserved_2_2_MASK                             0x4
#define D18F1x1A0_Lock_OFFSET                                   3
#define D18F1x1A0_Lock_WIDTH                                    1
#define D18F1x1A0_Lock_MASK                                     0x8
#define D18F1x1A0_Reserved_7_4_OFFSET                           4
#define D18F1x1A0_Reserved_7_4_WIDTH                            4
#define D18F1x1A0_Reserved_7_4_MASK                             0xf0
#define D18F1x1A0_MMIOBase_39_16__OFFSET                        8
#define D18F1x1A0_MMIOBase_39_16__WIDTH                         24
#define D18F1x1A0_MMIOBase_39_16__MASK                          0xffffff00

/// D18F1x1A0
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                                     Lock:1 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                          MMIOBase_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x1A0_STRUCT;

// **** D18F1x1A4 Register Definition ****
// Address
#define D18F1x1A4_ADDRESS                                       0x1a4

// Type
#define D18F1x1A4_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x1A4_DstNode_OFFSET                                0
#define D18F1x1A4_DstNode_WIDTH                                 3
#define D18F1x1A4_DstNode_MASK                                  0x7
#define D18F1x1A4_Reserved_3_3_OFFSET                           3
#define D18F1x1A4_Reserved_3_3_WIDTH                            1
#define D18F1x1A4_Reserved_3_3_MASK                             0x8
#define D18F1x1A4_DstLink_OFFSET                                4
#define D18F1x1A4_DstLink_WIDTH                                 2
#define D18F1x1A4_DstLink_MASK                                  0x30
#define D18F1x1A4_DstSubLink_OFFSET                             6
#define D18F1x1A4_DstSubLink_WIDTH                              1
#define D18F1x1A4_DstSubLink_MASK                               0x40
#define D18F1x1A4_NP_OFFSET                                     7
#define D18F1x1A4_NP_WIDTH                                      1
#define D18F1x1A4_NP_MASK                                       0x80
#define D18F1x1A4_MMIOLimit_39_16__OFFSET                       8
#define D18F1x1A4_MMIOLimit_39_16__WIDTH                        24
#define D18F1x1A4_MMIOLimit_39_16__MASK                         0xffffff00

/// D18F1x1A4
typedef union {
  struct {                                                              ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                  DstLink:2 ; ///<
    UINT32                                               DstSubLink:1 ; ///<
    UINT32                                                       NP:1 ; ///<
    UINT32                                         MMIOLimit_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x1A4_STRUCT;

// **** D18F1x1A8 Register Definition ****
// Address
#define D18F1x1A8_ADDRESS                                       0x1a8

// Type
#define D18F1x1A8_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x1A8_RE_OFFSET                                     0
#define D18F1x1A8_RE_WIDTH                                      1
#define D18F1x1A8_RE_MASK                                       0x1
#define D18F1x1A8_WE_OFFSET                                     1
#define D18F1x1A8_WE_WIDTH                                      1
#define D18F1x1A8_WE_MASK                                       0x2
#define D18F1x1A8_Reserved_2_2_OFFSET                           2
#define D18F1x1A8_Reserved_2_2_WIDTH                            1
#define D18F1x1A8_Reserved_2_2_MASK                             0x4
#define D18F1x1A8_Lock_OFFSET                                   3
#define D18F1x1A8_Lock_WIDTH                                    1
#define D18F1x1A8_Lock_MASK                                     0x8
#define D18F1x1A8_Reserved_7_4_OFFSET                           4
#define D18F1x1A8_Reserved_7_4_WIDTH                            4
#define D18F1x1A8_Reserved_7_4_MASK                             0xf0
#define D18F1x1A8_MMIOBase_39_16__OFFSET                        8
#define D18F1x1A8_MMIOBase_39_16__WIDTH                         24
#define D18F1x1A8_MMIOBase_39_16__MASK                          0xffffff00

/// D18F1x1A8
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                                     Lock:1 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                          MMIOBase_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x1A8_STRUCT;

// **** D18F1x1AC Register Definition ****
// Address
#define D18F1x1AC_ADDRESS                                       0x1ac

// Type
#define D18F1x1AC_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x1AC_DstNode_OFFSET                                0
#define D18F1x1AC_DstNode_WIDTH                                 3
#define D18F1x1AC_DstNode_MASK                                  0x7
#define D18F1x1AC_Reserved_3_3_OFFSET                           3
#define D18F1x1AC_Reserved_3_3_WIDTH                            1
#define D18F1x1AC_Reserved_3_3_MASK                             0x8
#define D18F1x1AC_DstLink_OFFSET                                4
#define D18F1x1AC_DstLink_WIDTH                                 2
#define D18F1x1AC_DstLink_MASK                                  0x30
#define D18F1x1AC_DstSubLink_OFFSET                             6
#define D18F1x1AC_DstSubLink_WIDTH                              1
#define D18F1x1AC_DstSubLink_MASK                               0x40
#define D18F1x1AC_NP_OFFSET                                     7
#define D18F1x1AC_NP_WIDTH                                      1
#define D18F1x1AC_NP_MASK                                       0x80
#define D18F1x1AC_MMIOLimit_39_16__OFFSET                       8
#define D18F1x1AC_MMIOLimit_39_16__WIDTH                        24
#define D18F1x1AC_MMIOLimit_39_16__MASK                         0xffffff00

/// D18F1x1AC
typedef union {
  struct {                                                              ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                  DstLink:2 ; ///<
    UINT32                                               DstSubLink:1 ; ///<
    UINT32                                                       NP:1 ; ///<
    UINT32                                         MMIOLimit_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x1AC_STRUCT;

// **** D18F1x1B0 Register Definition ****
// Address
#define D18F1x1B0_ADDRESS                                       0x1b0

// Type
#define D18F1x1B0_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x1B0_RE_OFFSET                                     0
#define D18F1x1B0_RE_WIDTH                                      1
#define D18F1x1B0_RE_MASK                                       0x1
#define D18F1x1B0_WE_OFFSET                                     1
#define D18F1x1B0_WE_WIDTH                                      1
#define D18F1x1B0_WE_MASK                                       0x2
#define D18F1x1B0_Reserved_2_2_OFFSET                           2
#define D18F1x1B0_Reserved_2_2_WIDTH                            1
#define D18F1x1B0_Reserved_2_2_MASK                             0x4
#define D18F1x1B0_Lock_OFFSET                                   3
#define D18F1x1B0_Lock_WIDTH                                    1
#define D18F1x1B0_Lock_MASK                                     0x8
#define D18F1x1B0_Reserved_7_4_OFFSET                           4
#define D18F1x1B0_Reserved_7_4_WIDTH                            4
#define D18F1x1B0_Reserved_7_4_MASK                             0xf0
#define D18F1x1B0_MMIOBase_39_16__OFFSET                        8
#define D18F1x1B0_MMIOBase_39_16__WIDTH                         24
#define D18F1x1B0_MMIOBase_39_16__MASK                          0xffffff00

/// D18F1x1B0
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                                     Lock:1 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                          MMIOBase_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x1B0_STRUCT;

// **** D18F1x1B4 Register Definition ****
// Address
#define D18F1x1B4_ADDRESS                                       0x1b4

// Type
#define D18F1x1B4_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x1B4_DstNode_OFFSET                                0
#define D18F1x1B4_DstNode_WIDTH                                 3
#define D18F1x1B4_DstNode_MASK                                  0x7
#define D18F1x1B4_Reserved_3_3_OFFSET                           3
#define D18F1x1B4_Reserved_3_3_WIDTH                            1
#define D18F1x1B4_Reserved_3_3_MASK                             0x8
#define D18F1x1B4_DstLink_OFFSET                                4
#define D18F1x1B4_DstLink_WIDTH                                 2
#define D18F1x1B4_DstLink_MASK                                  0x30
#define D18F1x1B4_DstSubLink_OFFSET                             6
#define D18F1x1B4_DstSubLink_WIDTH                              1
#define D18F1x1B4_DstSubLink_MASK                               0x40
#define D18F1x1B4_NP_OFFSET                                     7
#define D18F1x1B4_NP_WIDTH                                      1
#define D18F1x1B4_NP_MASK                                       0x80
#define D18F1x1B4_MMIOLimit_39_16__OFFSET                       8
#define D18F1x1B4_MMIOLimit_39_16__WIDTH                        24
#define D18F1x1B4_MMIOLimit_39_16__MASK                         0xffffff00

/// D18F1x1B4
typedef union {
  struct {                                                              ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                  DstLink:2 ; ///<
    UINT32                                               DstSubLink:1 ; ///<
    UINT32                                                       NP:1 ; ///<
    UINT32                                         MMIOLimit_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x1B4_STRUCT;

// **** D18F1x1B8 Register Definition ****
// Address
#define D18F1x1B8_ADDRESS                                       0x1b8

// Type
#define D18F1x1B8_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x1B8_RE_OFFSET                                     0
#define D18F1x1B8_RE_WIDTH                                      1
#define D18F1x1B8_RE_MASK                                       0x1
#define D18F1x1B8_WE_OFFSET                                     1
#define D18F1x1B8_WE_WIDTH                                      1
#define D18F1x1B8_WE_MASK                                       0x2
#define D18F1x1B8_Reserved_2_2_OFFSET                           2
#define D18F1x1B8_Reserved_2_2_WIDTH                            1
#define D18F1x1B8_Reserved_2_2_MASK                             0x4
#define D18F1x1B8_Lock_OFFSET                                   3
#define D18F1x1B8_Lock_WIDTH                                    1
#define D18F1x1B8_Lock_MASK                                     0x8
#define D18F1x1B8_Reserved_7_4_OFFSET                           4
#define D18F1x1B8_Reserved_7_4_WIDTH                            4
#define D18F1x1B8_Reserved_7_4_MASK                             0xf0
#define D18F1x1B8_MMIOBase_39_16__OFFSET                        8
#define D18F1x1B8_MMIOBase_39_16__WIDTH                         24
#define D18F1x1B8_MMIOBase_39_16__MASK                          0xffffff00

/// D18F1x1B8
typedef union {
  struct {                                                              ///<
    UINT32                                                       RE:1 ; ///<
    UINT32                                                       WE:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                                     Lock:1 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                          MMIOBase_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x1B8_STRUCT;

// **** D18F1x1BC Register Definition ****
// Address
#define D18F1x1BC_ADDRESS                                       0x1bc

// Type
#define D18F1x1BC_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x1BC_DstNode_OFFSET                                0
#define D18F1x1BC_DstNode_WIDTH                                 3
#define D18F1x1BC_DstNode_MASK                                  0x7
#define D18F1x1BC_Reserved_3_3_OFFSET                           3
#define D18F1x1BC_Reserved_3_3_WIDTH                            1
#define D18F1x1BC_Reserved_3_3_MASK                             0x8
#define D18F1x1BC_DstLink_OFFSET                                4
#define D18F1x1BC_DstLink_WIDTH                                 2
#define D18F1x1BC_DstLink_MASK                                  0x30
#define D18F1x1BC_DstSubLink_OFFSET                             6
#define D18F1x1BC_DstSubLink_WIDTH                              1
#define D18F1x1BC_DstSubLink_MASK                               0x40
#define D18F1x1BC_NP_OFFSET                                     7
#define D18F1x1BC_NP_WIDTH                                      1
#define D18F1x1BC_NP_MASK                                       0x80
#define D18F1x1BC_MMIOLimit_39_16__OFFSET                       8
#define D18F1x1BC_MMIOLimit_39_16__WIDTH                        24
#define D18F1x1BC_MMIOLimit_39_16__MASK                         0xffffff00

/// D18F1x1BC
typedef union {
  struct {                                                              ///<
    UINT32                                                  DstNode:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                  DstLink:2 ; ///<
    UINT32                                               DstSubLink:1 ; ///<
    UINT32                                                       NP:1 ; ///<
    UINT32                                         MMIOLimit_39_16_:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x1BC_STRUCT;

// **** D18F1x1C0 Register Definition ****
// Address
#define D18F1x1C0_ADDRESS                                       0x1c0

// Type
#define D18F1x1C0_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x1C0_MMIOBase_47_40__OFFSET                        0
#define D18F1x1C0_MMIOBase_47_40__WIDTH                         8
#define D18F1x1C0_MMIOBase_47_40__MASK                          0xff
#define D18F1x1C0_Reserved_15_8_OFFSET                          8
#define D18F1x1C0_Reserved_15_8_WIDTH                           8
#define D18F1x1C0_Reserved_15_8_MASK                            0xff00
#define D18F1x1C0_MMIOLimit_47_40__OFFSET                       16
#define D18F1x1C0_MMIOLimit_47_40__WIDTH                        8
#define D18F1x1C0_MMIOLimit_47_40__MASK                         0xff0000
#define D18F1x1C0_Reserved_31_24_OFFSET                         24
#define D18F1x1C0_Reserved_31_24_WIDTH                          8
#define D18F1x1C0_Reserved_31_24_MASK                           0xff000000

/// D18F1x1C0
typedef union {
  struct {                                                              ///<
    UINT32                                          MMIOBase_47_40_:8 ; ///<
    UINT32                                            Reserved_15_8:8 ; ///<
    UINT32                                         MMIOLimit_47_40_:8 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x1C0_STRUCT;

// **** D18F1x1C4 Register Definition ****
// Address
#define D18F1x1C4_ADDRESS                                       0x1c4

// Type
#define D18F1x1C4_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x1C4_MMIOBase_47_40__OFFSET                        0
#define D18F1x1C4_MMIOBase_47_40__WIDTH                         8
#define D18F1x1C4_MMIOBase_47_40__MASK                          0xff
#define D18F1x1C4_Reserved_15_8_OFFSET                          8
#define D18F1x1C4_Reserved_15_8_WIDTH                           8
#define D18F1x1C4_Reserved_15_8_MASK                            0xff00
#define D18F1x1C4_MMIOLimit_47_40__OFFSET                       16
#define D18F1x1C4_MMIOLimit_47_40__WIDTH                        8
#define D18F1x1C4_MMIOLimit_47_40__MASK                         0xff0000
#define D18F1x1C4_Reserved_31_24_OFFSET                         24
#define D18F1x1C4_Reserved_31_24_WIDTH                          8
#define D18F1x1C4_Reserved_31_24_MASK                           0xff000000

/// D18F1x1C4
typedef union {
  struct {                                                              ///<
    UINT32                                          MMIOBase_47_40_:8 ; ///<
    UINT32                                            Reserved_15_8:8 ; ///<
    UINT32                                         MMIOLimit_47_40_:8 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x1C4_STRUCT;

// **** D18F1x1C8 Register Definition ****
// Address
#define D18F1x1C8_ADDRESS                                       0x1c8

// Type
#define D18F1x1C8_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x1C8_MMIOBase_47_40__OFFSET                        0
#define D18F1x1C8_MMIOBase_47_40__WIDTH                         8
#define D18F1x1C8_MMIOBase_47_40__MASK                          0xff
#define D18F1x1C8_Reserved_15_8_OFFSET                          8
#define D18F1x1C8_Reserved_15_8_WIDTH                           8
#define D18F1x1C8_Reserved_15_8_MASK                            0xff00
#define D18F1x1C8_MMIOLimit_47_40__OFFSET                       16
#define D18F1x1C8_MMIOLimit_47_40__WIDTH                        8
#define D18F1x1C8_MMIOLimit_47_40__MASK                         0xff0000
#define D18F1x1C8_Reserved_31_24_OFFSET                         24
#define D18F1x1C8_Reserved_31_24_WIDTH                          8
#define D18F1x1C8_Reserved_31_24_MASK                           0xff000000

/// D18F1x1C8
typedef union {
  struct {                                                              ///<
    UINT32                                          MMIOBase_47_40_:8 ; ///<
    UINT32                                            Reserved_15_8:8 ; ///<
    UINT32                                         MMIOLimit_47_40_:8 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x1C8_STRUCT;

// **** D18F1x1CC Register Definition ****
// Address
#define D18F1x1CC_ADDRESS                                       0x1cc

// Type
#define D18F1x1CC_TYPE                                          TYPE_D18F1
// Field Data
#define D18F1x1CC_MMIOBase_47_40__OFFSET                        0
#define D18F1x1CC_MMIOBase_47_40__WIDTH                         8
#define D18F1x1CC_MMIOBase_47_40__MASK                          0xff
#define D18F1x1CC_Reserved_15_8_OFFSET                          8
#define D18F1x1CC_Reserved_15_8_WIDTH                           8
#define D18F1x1CC_Reserved_15_8_MASK                            0xff00
#define D18F1x1CC_MMIOLimit_47_40__OFFSET                       16
#define D18F1x1CC_MMIOLimit_47_40__WIDTH                        8
#define D18F1x1CC_MMIOLimit_47_40__MASK                         0xff0000
#define D18F1x1CC_Reserved_31_24_OFFSET                         24
#define D18F1x1CC_Reserved_31_24_WIDTH                          8
#define D18F1x1CC_Reserved_31_24_MASK                           0xff000000

/// D18F1x1CC
typedef union {
  struct {                                                              ///<
    UINT32                                          MMIOBase_47_40_:8 ; ///<
    UINT32                                            Reserved_15_8:8 ; ///<
    UINT32                                         MMIOLimit_47_40_:8 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F1x1CC_STRUCT;

// **** D18F2x00 Register Definition ****
// Address
#define D18F2x00_ADDRESS                                        0x0

// Type
#define D18F2x00_TYPE                                           TYPE_D18F2
// Field Data
#define D18F2x00_VendorID_OFFSET                                0
#define D18F2x00_VendorID_WIDTH                                 16
#define D18F2x00_VendorID_MASK                                  0xffff
#define D18F2x00_DeviceID_OFFSET                                16
#define D18F2x00_DeviceID_WIDTH                                 16
#define D18F2x00_DeviceID_MASK                                  0xffff0000

/// D18F2x00
typedef union {
  struct {                                                              ///<
    UINT32                                                 VendorID:16; ///<
    UINT32                                                 DeviceID:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x00_STRUCT;

// **** D18F2x08 Register Definition ****
// Address
#define D18F2x08_ADDRESS                                        0x8

// Type
#define D18F2x08_TYPE                                           TYPE_D18F2
// Field Data
#define D18F2x08_RevID_OFFSET                                   0
#define D18F2x08_RevID_WIDTH                                    8
#define D18F2x08_RevID_MASK                                     0xff
#define D18F2x08_ClassCode_OFFSET                               8
#define D18F2x08_ClassCode_WIDTH                                24
#define D18F2x08_ClassCode_MASK                                 0xffffff00

/// D18F2x08
typedef union {
  struct {                                                              ///<
    UINT32                                                    RevID:8 ; ///<
    UINT32                                                ClassCode:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x08_STRUCT;

// **** D18F2x0C Register Definition ****
// Address
#define D18F2x0C_ADDRESS                                        0xc

// Type
#define D18F2x0C_TYPE                                           TYPE_D18F2
// Field Data
#define D18F2x0C_HeaderTypeReg_OFFSET                           0
#define D18F2x0C_HeaderTypeReg_WIDTH                            32
#define D18F2x0C_HeaderTypeReg_MASK                             0xffffffff

/// D18F2x0C
typedef union {
  struct {                                                              ///<
    UINT32                                            HeaderTypeReg:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x0C_STRUCT;

// **** D18F2x40_dct1 Register Definition ****
// Address
#define D18F2x40_dct1_ADDRESS                                   0x40

// Type
#define D18F2x40_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x40_dct1_CSEnable_OFFSET                           0
#define D18F2x40_dct1_CSEnable_WIDTH                            1
#define D18F2x40_dct1_CSEnable_MASK                             0x1
#define D18F2x40_dct1_Reserved_1_1_OFFSET                       1
#define D18F2x40_dct1_Reserved_1_1_WIDTH                        1
#define D18F2x40_dct1_Reserved_1_1_MASK                         0x2
#define D18F2x40_dct1_TestFail_OFFSET                           2
#define D18F2x40_dct1_TestFail_WIDTH                            1
#define D18F2x40_dct1_TestFail_MASK                             0x4
#define D18F2x40_dct1_OnDimmMirror_OFFSET                       3
#define D18F2x40_dct1_OnDimmMirror_WIDTH                        1
#define D18F2x40_dct1_OnDimmMirror_MASK                         0x8
#define D18F2x40_dct1_Reserved_4_4_OFFSET                       4
#define D18F2x40_dct1_Reserved_4_4_WIDTH                        1
#define D18F2x40_dct1_Reserved_4_4_MASK                         0x10
#define D18F2x40_dct1_BaseAddr_21_11__OFFSET                    5
#define D18F2x40_dct1_BaseAddr_21_11__WIDTH                     11
#define D18F2x40_dct1_BaseAddr_21_11__MASK                      0xffe0
#define D18F2x40_dct1_Reserved_18_16_OFFSET                     16
#define D18F2x40_dct1_Reserved_18_16_WIDTH                      3
#define D18F2x40_dct1_Reserved_18_16_MASK                       0x70000
#define D18F2x40_dct1_BaseAddr_38_27__OFFSET                    19
#define D18F2x40_dct1_BaseAddr_38_27__WIDTH                     12
#define D18F2x40_dct1_BaseAddr_38_27__MASK                      0x7ff80000
#define D18F2x40_dct1_Reserved_31_31_OFFSET                     31
#define D18F2x40_dct1_Reserved_31_31_WIDTH                      1
#define D18F2x40_dct1_Reserved_31_31_MASK                       0x80000000

/// D18F2x40_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSEnable:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                                 TestFail:1 ; ///<
    UINT32                                             OnDimmMirror:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          BaseAddr_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          BaseAddr_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x40_dct1_STRUCT;

// **** D18F2x40_dct0 Register Definition ****
// Address
#define D18F2x40_dct0_ADDRESS                                   0x40

// Type
#define D18F2x40_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x40_dct0_CSEnable_OFFSET                           0
#define D18F2x40_dct0_CSEnable_WIDTH                            1
#define D18F2x40_dct0_CSEnable_MASK                             0x1
#define D18F2x40_dct0_Reserved_1_1_OFFSET                       1
#define D18F2x40_dct0_Reserved_1_1_WIDTH                        1
#define D18F2x40_dct0_Reserved_1_1_MASK                         0x2
#define D18F2x40_dct0_TestFail_OFFSET                           2
#define D18F2x40_dct0_TestFail_WIDTH                            1
#define D18F2x40_dct0_TestFail_MASK                             0x4
#define D18F2x40_dct0_OnDimmMirror_OFFSET                       3
#define D18F2x40_dct0_OnDimmMirror_WIDTH                        1
#define D18F2x40_dct0_OnDimmMirror_MASK                         0x8
#define D18F2x40_dct0_Reserved_4_4_OFFSET                       4
#define D18F2x40_dct0_Reserved_4_4_WIDTH                        1
#define D18F2x40_dct0_Reserved_4_4_MASK                         0x10
#define D18F2x40_dct0_BaseAddr_21_11__OFFSET                    5
#define D18F2x40_dct0_BaseAddr_21_11__WIDTH                     11
#define D18F2x40_dct0_BaseAddr_21_11__MASK                      0xffe0
#define D18F2x40_dct0_Reserved_18_16_OFFSET                     16
#define D18F2x40_dct0_Reserved_18_16_WIDTH                      3
#define D18F2x40_dct0_Reserved_18_16_MASK                       0x70000
#define D18F2x40_dct0_BaseAddr_38_27__OFFSET                    19
#define D18F2x40_dct0_BaseAddr_38_27__WIDTH                     12
#define D18F2x40_dct0_BaseAddr_38_27__MASK                      0x7ff80000
#define D18F2x40_dct0_Reserved_31_31_OFFSET                     31
#define D18F2x40_dct0_Reserved_31_31_WIDTH                      1
#define D18F2x40_dct0_Reserved_31_31_MASK                       0x80000000

/// D18F2x40_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSEnable:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                                 TestFail:1 ; ///<
    UINT32                                             OnDimmMirror:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          BaseAddr_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          BaseAddr_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x40_dct0_STRUCT;

// **** D18F2x44_dct1 Register Definition ****
// Address
#define D18F2x44_dct1_ADDRESS                                   0x44

// Type
#define D18F2x44_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x44_dct1_CSEnable_OFFSET                           0
#define D18F2x44_dct1_CSEnable_WIDTH                            1
#define D18F2x44_dct1_CSEnable_MASK                             0x1
#define D18F2x44_dct1_Reserved_1_1_OFFSET                       1
#define D18F2x44_dct1_Reserved_1_1_WIDTH                        1
#define D18F2x44_dct1_Reserved_1_1_MASK                         0x2
#define D18F2x44_dct1_TestFail_OFFSET                           2
#define D18F2x44_dct1_TestFail_WIDTH                            1
#define D18F2x44_dct1_TestFail_MASK                             0x4
#define D18F2x44_dct1_OnDimmMirror_OFFSET                       3
#define D18F2x44_dct1_OnDimmMirror_WIDTH                        1
#define D18F2x44_dct1_OnDimmMirror_MASK                         0x8
#define D18F2x44_dct1_Reserved_4_4_OFFSET                       4
#define D18F2x44_dct1_Reserved_4_4_WIDTH                        1
#define D18F2x44_dct1_Reserved_4_4_MASK                         0x10
#define D18F2x44_dct1_BaseAddr_21_11__OFFSET                    5
#define D18F2x44_dct1_BaseAddr_21_11__WIDTH                     11
#define D18F2x44_dct1_BaseAddr_21_11__MASK                      0xffe0
#define D18F2x44_dct1_Reserved_18_16_OFFSET                     16
#define D18F2x44_dct1_Reserved_18_16_WIDTH                      3
#define D18F2x44_dct1_Reserved_18_16_MASK                       0x70000
#define D18F2x44_dct1_BaseAddr_38_27__OFFSET                    19
#define D18F2x44_dct1_BaseAddr_38_27__WIDTH                     12
#define D18F2x44_dct1_BaseAddr_38_27__MASK                      0x7ff80000
#define D18F2x44_dct1_Reserved_31_31_OFFSET                     31
#define D18F2x44_dct1_Reserved_31_31_WIDTH                      1
#define D18F2x44_dct1_Reserved_31_31_MASK                       0x80000000

/// D18F2x44_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSEnable:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                                 TestFail:1 ; ///<
    UINT32                                             OnDimmMirror:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          BaseAddr_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          BaseAddr_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x44_dct1_STRUCT;

// **** D18F2x44_dct0 Register Definition ****
// Address
#define D18F2x44_dct0_ADDRESS                                   0x44

// Type
#define D18F2x44_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x44_dct0_CSEnable_OFFSET                           0
#define D18F2x44_dct0_CSEnable_WIDTH                            1
#define D18F2x44_dct0_CSEnable_MASK                             0x1
#define D18F2x44_dct0_Reserved_1_1_OFFSET                       1
#define D18F2x44_dct0_Reserved_1_1_WIDTH                        1
#define D18F2x44_dct0_Reserved_1_1_MASK                         0x2
#define D18F2x44_dct0_TestFail_OFFSET                           2
#define D18F2x44_dct0_TestFail_WIDTH                            1
#define D18F2x44_dct0_TestFail_MASK                             0x4
#define D18F2x44_dct0_OnDimmMirror_OFFSET                       3
#define D18F2x44_dct0_OnDimmMirror_WIDTH                        1
#define D18F2x44_dct0_OnDimmMirror_MASK                         0x8
#define D18F2x44_dct0_Reserved_4_4_OFFSET                       4
#define D18F2x44_dct0_Reserved_4_4_WIDTH                        1
#define D18F2x44_dct0_Reserved_4_4_MASK                         0x10
#define D18F2x44_dct0_BaseAddr_21_11__OFFSET                    5
#define D18F2x44_dct0_BaseAddr_21_11__WIDTH                     11
#define D18F2x44_dct0_BaseAddr_21_11__MASK                      0xffe0
#define D18F2x44_dct0_Reserved_18_16_OFFSET                     16
#define D18F2x44_dct0_Reserved_18_16_WIDTH                      3
#define D18F2x44_dct0_Reserved_18_16_MASK                       0x70000
#define D18F2x44_dct0_BaseAddr_38_27__OFFSET                    19
#define D18F2x44_dct0_BaseAddr_38_27__WIDTH                     12
#define D18F2x44_dct0_BaseAddr_38_27__MASK                      0x7ff80000
#define D18F2x44_dct0_Reserved_31_31_OFFSET                     31
#define D18F2x44_dct0_Reserved_31_31_WIDTH                      1
#define D18F2x44_dct0_Reserved_31_31_MASK                       0x80000000

/// D18F2x44_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSEnable:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                                 TestFail:1 ; ///<
    UINT32                                             OnDimmMirror:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          BaseAddr_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          BaseAddr_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x44_dct0_STRUCT;

// **** D18F2x48_dct1 Register Definition ****
// Address
#define D18F2x48_dct1_ADDRESS                                   0x48

// Type
#define D18F2x48_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x48_dct1_CSEnable_OFFSET                           0
#define D18F2x48_dct1_CSEnable_WIDTH                            1
#define D18F2x48_dct1_CSEnable_MASK                             0x1
#define D18F2x48_dct1_Reserved_1_1_OFFSET                       1
#define D18F2x48_dct1_Reserved_1_1_WIDTH                        1
#define D18F2x48_dct1_Reserved_1_1_MASK                         0x2
#define D18F2x48_dct1_TestFail_OFFSET                           2
#define D18F2x48_dct1_TestFail_WIDTH                            1
#define D18F2x48_dct1_TestFail_MASK                             0x4
#define D18F2x48_dct1_OnDimmMirror_OFFSET                       3
#define D18F2x48_dct1_OnDimmMirror_WIDTH                        1
#define D18F2x48_dct1_OnDimmMirror_MASK                         0x8
#define D18F2x48_dct1_Reserved_4_4_OFFSET                       4
#define D18F2x48_dct1_Reserved_4_4_WIDTH                        1
#define D18F2x48_dct1_Reserved_4_4_MASK                         0x10
#define D18F2x48_dct1_BaseAddr_21_11__OFFSET                    5
#define D18F2x48_dct1_BaseAddr_21_11__WIDTH                     11
#define D18F2x48_dct1_BaseAddr_21_11__MASK                      0xffe0
#define D18F2x48_dct1_Reserved_18_16_OFFSET                     16
#define D18F2x48_dct1_Reserved_18_16_WIDTH                      3
#define D18F2x48_dct1_Reserved_18_16_MASK                       0x70000
#define D18F2x48_dct1_BaseAddr_38_27__OFFSET                    19
#define D18F2x48_dct1_BaseAddr_38_27__WIDTH                     12
#define D18F2x48_dct1_BaseAddr_38_27__MASK                      0x7ff80000
#define D18F2x48_dct1_Reserved_31_31_OFFSET                     31
#define D18F2x48_dct1_Reserved_31_31_WIDTH                      1
#define D18F2x48_dct1_Reserved_31_31_MASK                       0x80000000

/// D18F2x48_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSEnable:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                                 TestFail:1 ; ///<
    UINT32                                             OnDimmMirror:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          BaseAddr_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          BaseAddr_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x48_dct1_STRUCT;

// **** D18F2x48_dct0 Register Definition ****
// Address
#define D18F2x48_dct0_ADDRESS                                   0x48

// Type
#define D18F2x48_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x48_dct0_CSEnable_OFFSET                           0
#define D18F2x48_dct0_CSEnable_WIDTH                            1
#define D18F2x48_dct0_CSEnable_MASK                             0x1
#define D18F2x48_dct0_Reserved_1_1_OFFSET                       1
#define D18F2x48_dct0_Reserved_1_1_WIDTH                        1
#define D18F2x48_dct0_Reserved_1_1_MASK                         0x2
#define D18F2x48_dct0_TestFail_OFFSET                           2
#define D18F2x48_dct0_TestFail_WIDTH                            1
#define D18F2x48_dct0_TestFail_MASK                             0x4
#define D18F2x48_dct0_OnDimmMirror_OFFSET                       3
#define D18F2x48_dct0_OnDimmMirror_WIDTH                        1
#define D18F2x48_dct0_OnDimmMirror_MASK                         0x8
#define D18F2x48_dct0_Reserved_4_4_OFFSET                       4
#define D18F2x48_dct0_Reserved_4_4_WIDTH                        1
#define D18F2x48_dct0_Reserved_4_4_MASK                         0x10
#define D18F2x48_dct0_BaseAddr_21_11__OFFSET                    5
#define D18F2x48_dct0_BaseAddr_21_11__WIDTH                     11
#define D18F2x48_dct0_BaseAddr_21_11__MASK                      0xffe0
#define D18F2x48_dct0_Reserved_18_16_OFFSET                     16
#define D18F2x48_dct0_Reserved_18_16_WIDTH                      3
#define D18F2x48_dct0_Reserved_18_16_MASK                       0x70000
#define D18F2x48_dct0_BaseAddr_38_27__OFFSET                    19
#define D18F2x48_dct0_BaseAddr_38_27__WIDTH                     12
#define D18F2x48_dct0_BaseAddr_38_27__MASK                      0x7ff80000
#define D18F2x48_dct0_Reserved_31_31_OFFSET                     31
#define D18F2x48_dct0_Reserved_31_31_WIDTH                      1
#define D18F2x48_dct0_Reserved_31_31_MASK                       0x80000000

/// D18F2x48_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSEnable:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                                 TestFail:1 ; ///<
    UINT32                                             OnDimmMirror:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          BaseAddr_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          BaseAddr_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x48_dct0_STRUCT;

// **** D18F2x4C_dct1 Register Definition ****
// Address
#define D18F2x4C_dct1_ADDRESS                                   0x4c

// Type
#define D18F2x4C_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x4C_dct1_CSEnable_OFFSET                           0
#define D18F2x4C_dct1_CSEnable_WIDTH                            1
#define D18F2x4C_dct1_CSEnable_MASK                             0x1
#define D18F2x4C_dct1_Reserved_1_1_OFFSET                       1
#define D18F2x4C_dct1_Reserved_1_1_WIDTH                        1
#define D18F2x4C_dct1_Reserved_1_1_MASK                         0x2
#define D18F2x4C_dct1_TestFail_OFFSET                           2
#define D18F2x4C_dct1_TestFail_WIDTH                            1
#define D18F2x4C_dct1_TestFail_MASK                             0x4
#define D18F2x4C_dct1_OnDimmMirror_OFFSET                       3
#define D18F2x4C_dct1_OnDimmMirror_WIDTH                        1
#define D18F2x4C_dct1_OnDimmMirror_MASK                         0x8
#define D18F2x4C_dct1_Reserved_4_4_OFFSET                       4
#define D18F2x4C_dct1_Reserved_4_4_WIDTH                        1
#define D18F2x4C_dct1_Reserved_4_4_MASK                         0x10
#define D18F2x4C_dct1_BaseAddr_21_11__OFFSET                    5
#define D18F2x4C_dct1_BaseAddr_21_11__WIDTH                     11
#define D18F2x4C_dct1_BaseAddr_21_11__MASK                      0xffe0
#define D18F2x4C_dct1_Reserved_18_16_OFFSET                     16
#define D18F2x4C_dct1_Reserved_18_16_WIDTH                      3
#define D18F2x4C_dct1_Reserved_18_16_MASK                       0x70000
#define D18F2x4C_dct1_BaseAddr_38_27__OFFSET                    19
#define D18F2x4C_dct1_BaseAddr_38_27__WIDTH                     12
#define D18F2x4C_dct1_BaseAddr_38_27__MASK                      0x7ff80000
#define D18F2x4C_dct1_Reserved_31_31_OFFSET                     31
#define D18F2x4C_dct1_Reserved_31_31_WIDTH                      1
#define D18F2x4C_dct1_Reserved_31_31_MASK                       0x80000000

/// D18F2x4C_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSEnable:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                                 TestFail:1 ; ///<
    UINT32                                             OnDimmMirror:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          BaseAddr_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          BaseAddr_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x4C_dct1_STRUCT;

// **** D18F2x4C_dct0 Register Definition ****
// Address
#define D18F2x4C_dct0_ADDRESS                                   0x4c

// Type
#define D18F2x4C_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x4C_dct0_CSEnable_OFFSET                           0
#define D18F2x4C_dct0_CSEnable_WIDTH                            1
#define D18F2x4C_dct0_CSEnable_MASK                             0x1
#define D18F2x4C_dct0_Reserved_1_1_OFFSET                       1
#define D18F2x4C_dct0_Reserved_1_1_WIDTH                        1
#define D18F2x4C_dct0_Reserved_1_1_MASK                         0x2
#define D18F2x4C_dct0_TestFail_OFFSET                           2
#define D18F2x4C_dct0_TestFail_WIDTH                            1
#define D18F2x4C_dct0_TestFail_MASK                             0x4
#define D18F2x4C_dct0_OnDimmMirror_OFFSET                       3
#define D18F2x4C_dct0_OnDimmMirror_WIDTH                        1
#define D18F2x4C_dct0_OnDimmMirror_MASK                         0x8
#define D18F2x4C_dct0_Reserved_4_4_OFFSET                       4
#define D18F2x4C_dct0_Reserved_4_4_WIDTH                        1
#define D18F2x4C_dct0_Reserved_4_4_MASK                         0x10
#define D18F2x4C_dct0_BaseAddr_21_11__OFFSET                    5
#define D18F2x4C_dct0_BaseAddr_21_11__WIDTH                     11
#define D18F2x4C_dct0_BaseAddr_21_11__MASK                      0xffe0
#define D18F2x4C_dct0_Reserved_18_16_OFFSET                     16
#define D18F2x4C_dct0_Reserved_18_16_WIDTH                      3
#define D18F2x4C_dct0_Reserved_18_16_MASK                       0x70000
#define D18F2x4C_dct0_BaseAddr_38_27__OFFSET                    19
#define D18F2x4C_dct0_BaseAddr_38_27__WIDTH                     12
#define D18F2x4C_dct0_BaseAddr_38_27__MASK                      0x7ff80000
#define D18F2x4C_dct0_Reserved_31_31_OFFSET                     31
#define D18F2x4C_dct0_Reserved_31_31_WIDTH                      1
#define D18F2x4C_dct0_Reserved_31_31_MASK                       0x80000000

/// D18F2x4C_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSEnable:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                                 TestFail:1 ; ///<
    UINT32                                             OnDimmMirror:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          BaseAddr_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          BaseAddr_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x4C_dct0_STRUCT;

// **** D18F2x50_dct1 Register Definition ****
// Address
#define D18F2x50_dct1_ADDRESS                                   0x50

// Type
#define D18F2x50_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x50_dct1_CSEnable_OFFSET                           0
#define D18F2x50_dct1_CSEnable_WIDTH                            1
#define D18F2x50_dct1_CSEnable_MASK                             0x1
#define D18F2x50_dct1_Reserved_1_1_OFFSET                       1
#define D18F2x50_dct1_Reserved_1_1_WIDTH                        1
#define D18F2x50_dct1_Reserved_1_1_MASK                         0x2
#define D18F2x50_dct1_TestFail_OFFSET                           2
#define D18F2x50_dct1_TestFail_WIDTH                            1
#define D18F2x50_dct1_TestFail_MASK                             0x4
#define D18F2x50_dct1_OnDimmMirror_OFFSET                       3
#define D18F2x50_dct1_OnDimmMirror_WIDTH                        1
#define D18F2x50_dct1_OnDimmMirror_MASK                         0x8
#define D18F2x50_dct1_Reserved_4_4_OFFSET                       4
#define D18F2x50_dct1_Reserved_4_4_WIDTH                        1
#define D18F2x50_dct1_Reserved_4_4_MASK                         0x10
#define D18F2x50_dct1_BaseAddr_21_11__OFFSET                    5
#define D18F2x50_dct1_BaseAddr_21_11__WIDTH                     11
#define D18F2x50_dct1_BaseAddr_21_11__MASK                      0xffe0
#define D18F2x50_dct1_Reserved_18_16_OFFSET                     16
#define D18F2x50_dct1_Reserved_18_16_WIDTH                      3
#define D18F2x50_dct1_Reserved_18_16_MASK                       0x70000
#define D18F2x50_dct1_BaseAddr_38_27__OFFSET                    19
#define D18F2x50_dct1_BaseAddr_38_27__WIDTH                     12
#define D18F2x50_dct1_BaseAddr_38_27__MASK                      0x7ff80000
#define D18F2x50_dct1_Reserved_31_31_OFFSET                     31
#define D18F2x50_dct1_Reserved_31_31_WIDTH                      1
#define D18F2x50_dct1_Reserved_31_31_MASK                       0x80000000

/// D18F2x50_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSEnable:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                                 TestFail:1 ; ///<
    UINT32                                             OnDimmMirror:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          BaseAddr_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          BaseAddr_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x50_dct1_STRUCT;

// **** D18F2x50_dct0 Register Definition ****
// Address
#define D18F2x50_dct0_ADDRESS                                   0x50

// Type
#define D18F2x50_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x50_dct0_CSEnable_OFFSET                           0
#define D18F2x50_dct0_CSEnable_WIDTH                            1
#define D18F2x50_dct0_CSEnable_MASK                             0x1
#define D18F2x50_dct0_Reserved_1_1_OFFSET                       1
#define D18F2x50_dct0_Reserved_1_1_WIDTH                        1
#define D18F2x50_dct0_Reserved_1_1_MASK                         0x2
#define D18F2x50_dct0_TestFail_OFFSET                           2
#define D18F2x50_dct0_TestFail_WIDTH                            1
#define D18F2x50_dct0_TestFail_MASK                             0x4
#define D18F2x50_dct0_OnDimmMirror_OFFSET                       3
#define D18F2x50_dct0_OnDimmMirror_WIDTH                        1
#define D18F2x50_dct0_OnDimmMirror_MASK                         0x8
#define D18F2x50_dct0_Reserved_4_4_OFFSET                       4
#define D18F2x50_dct0_Reserved_4_4_WIDTH                        1
#define D18F2x50_dct0_Reserved_4_4_MASK                         0x10
#define D18F2x50_dct0_BaseAddr_21_11__OFFSET                    5
#define D18F2x50_dct0_BaseAddr_21_11__WIDTH                     11
#define D18F2x50_dct0_BaseAddr_21_11__MASK                      0xffe0
#define D18F2x50_dct0_Reserved_18_16_OFFSET                     16
#define D18F2x50_dct0_Reserved_18_16_WIDTH                      3
#define D18F2x50_dct0_Reserved_18_16_MASK                       0x70000
#define D18F2x50_dct0_BaseAddr_38_27__OFFSET                    19
#define D18F2x50_dct0_BaseAddr_38_27__WIDTH                     12
#define D18F2x50_dct0_BaseAddr_38_27__MASK                      0x7ff80000
#define D18F2x50_dct0_Reserved_31_31_OFFSET                     31
#define D18F2x50_dct0_Reserved_31_31_WIDTH                      1
#define D18F2x50_dct0_Reserved_31_31_MASK                       0x80000000

/// D18F2x50_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSEnable:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                                 TestFail:1 ; ///<
    UINT32                                             OnDimmMirror:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          BaseAddr_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          BaseAddr_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x50_dct0_STRUCT;

// **** D18F2x54_dct0 Register Definition ****
// Address
#define D18F2x54_dct0_ADDRESS                                   0x54

// Type
#define D18F2x54_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x54_dct0_CSEnable_OFFSET                           0
#define D18F2x54_dct0_CSEnable_WIDTH                            1
#define D18F2x54_dct0_CSEnable_MASK                             0x1
#define D18F2x54_dct0_Reserved_1_1_OFFSET                       1
#define D18F2x54_dct0_Reserved_1_1_WIDTH                        1
#define D18F2x54_dct0_Reserved_1_1_MASK                         0x2
#define D18F2x54_dct0_TestFail_OFFSET                           2
#define D18F2x54_dct0_TestFail_WIDTH                            1
#define D18F2x54_dct0_TestFail_MASK                             0x4
#define D18F2x54_dct0_OnDimmMirror_OFFSET                       3
#define D18F2x54_dct0_OnDimmMirror_WIDTH                        1
#define D18F2x54_dct0_OnDimmMirror_MASK                         0x8
#define D18F2x54_dct0_Reserved_4_4_OFFSET                       4
#define D18F2x54_dct0_Reserved_4_4_WIDTH                        1
#define D18F2x54_dct0_Reserved_4_4_MASK                         0x10
#define D18F2x54_dct0_BaseAddr_21_11__OFFSET                    5
#define D18F2x54_dct0_BaseAddr_21_11__WIDTH                     11
#define D18F2x54_dct0_BaseAddr_21_11__MASK                      0xffe0
#define D18F2x54_dct0_Reserved_18_16_OFFSET                     16
#define D18F2x54_dct0_Reserved_18_16_WIDTH                      3
#define D18F2x54_dct0_Reserved_18_16_MASK                       0x70000
#define D18F2x54_dct0_BaseAddr_38_27__OFFSET                    19
#define D18F2x54_dct0_BaseAddr_38_27__WIDTH                     12
#define D18F2x54_dct0_BaseAddr_38_27__MASK                      0x7ff80000
#define D18F2x54_dct0_Reserved_31_31_OFFSET                     31
#define D18F2x54_dct0_Reserved_31_31_WIDTH                      1
#define D18F2x54_dct0_Reserved_31_31_MASK                       0x80000000

/// D18F2x54_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSEnable:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                                 TestFail:1 ; ///<
    UINT32                                             OnDimmMirror:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          BaseAddr_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          BaseAddr_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x54_dct0_STRUCT;

// **** D18F2x54_dct1 Register Definition ****
// Address
#define D18F2x54_dct1_ADDRESS                                   0x54

// Type
#define D18F2x54_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x54_dct1_CSEnable_OFFSET                           0
#define D18F2x54_dct1_CSEnable_WIDTH                            1
#define D18F2x54_dct1_CSEnable_MASK                             0x1
#define D18F2x54_dct1_Reserved_1_1_OFFSET                       1
#define D18F2x54_dct1_Reserved_1_1_WIDTH                        1
#define D18F2x54_dct1_Reserved_1_1_MASK                         0x2
#define D18F2x54_dct1_TestFail_OFFSET                           2
#define D18F2x54_dct1_TestFail_WIDTH                            1
#define D18F2x54_dct1_TestFail_MASK                             0x4
#define D18F2x54_dct1_OnDimmMirror_OFFSET                       3
#define D18F2x54_dct1_OnDimmMirror_WIDTH                        1
#define D18F2x54_dct1_OnDimmMirror_MASK                         0x8
#define D18F2x54_dct1_Reserved_4_4_OFFSET                       4
#define D18F2x54_dct1_Reserved_4_4_WIDTH                        1
#define D18F2x54_dct1_Reserved_4_4_MASK                         0x10
#define D18F2x54_dct1_BaseAddr_21_11__OFFSET                    5
#define D18F2x54_dct1_BaseAddr_21_11__WIDTH                     11
#define D18F2x54_dct1_BaseAddr_21_11__MASK                      0xffe0
#define D18F2x54_dct1_Reserved_18_16_OFFSET                     16
#define D18F2x54_dct1_Reserved_18_16_WIDTH                      3
#define D18F2x54_dct1_Reserved_18_16_MASK                       0x70000
#define D18F2x54_dct1_BaseAddr_38_27__OFFSET                    19
#define D18F2x54_dct1_BaseAddr_38_27__WIDTH                     12
#define D18F2x54_dct1_BaseAddr_38_27__MASK                      0x7ff80000
#define D18F2x54_dct1_Reserved_31_31_OFFSET                     31
#define D18F2x54_dct1_Reserved_31_31_WIDTH                      1
#define D18F2x54_dct1_Reserved_31_31_MASK                       0x80000000

/// D18F2x54_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSEnable:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                                 TestFail:1 ; ///<
    UINT32                                             OnDimmMirror:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          BaseAddr_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          BaseAddr_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x54_dct1_STRUCT;

// **** D18F2x58_dct1 Register Definition ****
// Address
#define D18F2x58_dct1_ADDRESS                                   0x58

// Type
#define D18F2x58_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x58_dct1_CSEnable_OFFSET                           0
#define D18F2x58_dct1_CSEnable_WIDTH                            1
#define D18F2x58_dct1_CSEnable_MASK                             0x1
#define D18F2x58_dct1_Reserved_1_1_OFFSET                       1
#define D18F2x58_dct1_Reserved_1_1_WIDTH                        1
#define D18F2x58_dct1_Reserved_1_1_MASK                         0x2
#define D18F2x58_dct1_TestFail_OFFSET                           2
#define D18F2x58_dct1_TestFail_WIDTH                            1
#define D18F2x58_dct1_TestFail_MASK                             0x4
#define D18F2x58_dct1_OnDimmMirror_OFFSET                       3
#define D18F2x58_dct1_OnDimmMirror_WIDTH                        1
#define D18F2x58_dct1_OnDimmMirror_MASK                         0x8
#define D18F2x58_dct1_Reserved_4_4_OFFSET                       4
#define D18F2x58_dct1_Reserved_4_4_WIDTH                        1
#define D18F2x58_dct1_Reserved_4_4_MASK                         0x10
#define D18F2x58_dct1_BaseAddr_21_11__OFFSET                    5
#define D18F2x58_dct1_BaseAddr_21_11__WIDTH                     11
#define D18F2x58_dct1_BaseAddr_21_11__MASK                      0xffe0
#define D18F2x58_dct1_Reserved_18_16_OFFSET                     16
#define D18F2x58_dct1_Reserved_18_16_WIDTH                      3
#define D18F2x58_dct1_Reserved_18_16_MASK                       0x70000
#define D18F2x58_dct1_BaseAddr_38_27__OFFSET                    19
#define D18F2x58_dct1_BaseAddr_38_27__WIDTH                     12
#define D18F2x58_dct1_BaseAddr_38_27__MASK                      0x7ff80000
#define D18F2x58_dct1_Reserved_31_31_OFFSET                     31
#define D18F2x58_dct1_Reserved_31_31_WIDTH                      1
#define D18F2x58_dct1_Reserved_31_31_MASK                       0x80000000

/// D18F2x58_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSEnable:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                                 TestFail:1 ; ///<
    UINT32                                             OnDimmMirror:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          BaseAddr_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          BaseAddr_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x58_dct1_STRUCT;

// **** D18F2x58_dct0 Register Definition ****
// Address
#define D18F2x58_dct0_ADDRESS                                   0x58

// Type
#define D18F2x58_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x58_dct0_CSEnable_OFFSET                           0
#define D18F2x58_dct0_CSEnable_WIDTH                            1
#define D18F2x58_dct0_CSEnable_MASK                             0x1
#define D18F2x58_dct0_Reserved_1_1_OFFSET                       1
#define D18F2x58_dct0_Reserved_1_1_WIDTH                        1
#define D18F2x58_dct0_Reserved_1_1_MASK                         0x2
#define D18F2x58_dct0_TestFail_OFFSET                           2
#define D18F2x58_dct0_TestFail_WIDTH                            1
#define D18F2x58_dct0_TestFail_MASK                             0x4
#define D18F2x58_dct0_OnDimmMirror_OFFSET                       3
#define D18F2x58_dct0_OnDimmMirror_WIDTH                        1
#define D18F2x58_dct0_OnDimmMirror_MASK                         0x8
#define D18F2x58_dct0_Reserved_4_4_OFFSET                       4
#define D18F2x58_dct0_Reserved_4_4_WIDTH                        1
#define D18F2x58_dct0_Reserved_4_4_MASK                         0x10
#define D18F2x58_dct0_BaseAddr_21_11__OFFSET                    5
#define D18F2x58_dct0_BaseAddr_21_11__WIDTH                     11
#define D18F2x58_dct0_BaseAddr_21_11__MASK                      0xffe0
#define D18F2x58_dct0_Reserved_18_16_OFFSET                     16
#define D18F2x58_dct0_Reserved_18_16_WIDTH                      3
#define D18F2x58_dct0_Reserved_18_16_MASK                       0x70000
#define D18F2x58_dct0_BaseAddr_38_27__OFFSET                    19
#define D18F2x58_dct0_BaseAddr_38_27__WIDTH                     12
#define D18F2x58_dct0_BaseAddr_38_27__MASK                      0x7ff80000
#define D18F2x58_dct0_Reserved_31_31_OFFSET                     31
#define D18F2x58_dct0_Reserved_31_31_WIDTH                      1
#define D18F2x58_dct0_Reserved_31_31_MASK                       0x80000000

/// D18F2x58_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSEnable:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                                 TestFail:1 ; ///<
    UINT32                                             OnDimmMirror:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          BaseAddr_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          BaseAddr_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x58_dct0_STRUCT;

// **** D18F2x5C_dct1 Register Definition ****
// Address
#define D18F2x5C_dct1_ADDRESS                                   0x5c

// Type
#define D18F2x5C_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x5C_dct1_CSEnable_OFFSET                           0
#define D18F2x5C_dct1_CSEnable_WIDTH                            1
#define D18F2x5C_dct1_CSEnable_MASK                             0x1
#define D18F2x5C_dct1_Reserved_1_1_OFFSET                       1
#define D18F2x5C_dct1_Reserved_1_1_WIDTH                        1
#define D18F2x5C_dct1_Reserved_1_1_MASK                         0x2
#define D18F2x5C_dct1_TestFail_OFFSET                           2
#define D18F2x5C_dct1_TestFail_WIDTH                            1
#define D18F2x5C_dct1_TestFail_MASK                             0x4
#define D18F2x5C_dct1_OnDimmMirror_OFFSET                       3
#define D18F2x5C_dct1_OnDimmMirror_WIDTH                        1
#define D18F2x5C_dct1_OnDimmMirror_MASK                         0x8
#define D18F2x5C_dct1_Reserved_4_4_OFFSET                       4
#define D18F2x5C_dct1_Reserved_4_4_WIDTH                        1
#define D18F2x5C_dct1_Reserved_4_4_MASK                         0x10
#define D18F2x5C_dct1_BaseAddr_21_11__OFFSET                    5
#define D18F2x5C_dct1_BaseAddr_21_11__WIDTH                     11
#define D18F2x5C_dct1_BaseAddr_21_11__MASK                      0xffe0
#define D18F2x5C_dct1_Reserved_18_16_OFFSET                     16
#define D18F2x5C_dct1_Reserved_18_16_WIDTH                      3
#define D18F2x5C_dct1_Reserved_18_16_MASK                       0x70000
#define D18F2x5C_dct1_BaseAddr_38_27__OFFSET                    19
#define D18F2x5C_dct1_BaseAddr_38_27__WIDTH                     12
#define D18F2x5C_dct1_BaseAddr_38_27__MASK                      0x7ff80000
#define D18F2x5C_dct1_Reserved_31_31_OFFSET                     31
#define D18F2x5C_dct1_Reserved_31_31_WIDTH                      1
#define D18F2x5C_dct1_Reserved_31_31_MASK                       0x80000000

/// D18F2x5C_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSEnable:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                                 TestFail:1 ; ///<
    UINT32                                             OnDimmMirror:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          BaseAddr_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          BaseAddr_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x5C_dct1_STRUCT;

// **** D18F2x5C_dct0 Register Definition ****
// Address
#define D18F2x5C_dct0_ADDRESS                                   0x5c

// Type
#define D18F2x5C_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x5C_dct0_CSEnable_OFFSET                           0
#define D18F2x5C_dct0_CSEnable_WIDTH                            1
#define D18F2x5C_dct0_CSEnable_MASK                             0x1
#define D18F2x5C_dct0_Reserved_1_1_OFFSET                       1
#define D18F2x5C_dct0_Reserved_1_1_WIDTH                        1
#define D18F2x5C_dct0_Reserved_1_1_MASK                         0x2
#define D18F2x5C_dct0_TestFail_OFFSET                           2
#define D18F2x5C_dct0_TestFail_WIDTH                            1
#define D18F2x5C_dct0_TestFail_MASK                             0x4
#define D18F2x5C_dct0_OnDimmMirror_OFFSET                       3
#define D18F2x5C_dct0_OnDimmMirror_WIDTH                        1
#define D18F2x5C_dct0_OnDimmMirror_MASK                         0x8
#define D18F2x5C_dct0_Reserved_4_4_OFFSET                       4
#define D18F2x5C_dct0_Reserved_4_4_WIDTH                        1
#define D18F2x5C_dct0_Reserved_4_4_MASK                         0x10
#define D18F2x5C_dct0_BaseAddr_21_11__OFFSET                    5
#define D18F2x5C_dct0_BaseAddr_21_11__WIDTH                     11
#define D18F2x5C_dct0_BaseAddr_21_11__MASK                      0xffe0
#define D18F2x5C_dct0_Reserved_18_16_OFFSET                     16
#define D18F2x5C_dct0_Reserved_18_16_WIDTH                      3
#define D18F2x5C_dct0_Reserved_18_16_MASK                       0x70000
#define D18F2x5C_dct0_BaseAddr_38_27__OFFSET                    19
#define D18F2x5C_dct0_BaseAddr_38_27__WIDTH                     12
#define D18F2x5C_dct0_BaseAddr_38_27__MASK                      0x7ff80000
#define D18F2x5C_dct0_Reserved_31_31_OFFSET                     31
#define D18F2x5C_dct0_Reserved_31_31_WIDTH                      1
#define D18F2x5C_dct0_Reserved_31_31_MASK                       0x80000000

/// D18F2x5C_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSEnable:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                                 TestFail:1 ; ///<
    UINT32                                             OnDimmMirror:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          BaseAddr_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          BaseAddr_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x5C_dct0_STRUCT;

// **** D18F2x60_dct1 Register Definition ****
// Address
#define D18F2x60_dct1_ADDRESS                                   0x60

// Type
#define D18F2x60_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x60_dct1_Reserved_4_0_OFFSET                       0
#define D18F2x60_dct1_Reserved_4_0_WIDTH                        5
#define D18F2x60_dct1_Reserved_4_0_MASK                         0x1f
#define D18F2x60_dct1_AddrMask_21_11__OFFSET                    5
#define D18F2x60_dct1_AddrMask_21_11__WIDTH                     11
#define D18F2x60_dct1_AddrMask_21_11__MASK                      0xffe0
#define D18F2x60_dct1_Reserved_18_16_OFFSET                     16
#define D18F2x60_dct1_Reserved_18_16_WIDTH                      3
#define D18F2x60_dct1_Reserved_18_16_MASK                       0x70000
#define D18F2x60_dct1_AddrMask_38_27__OFFSET                    19
#define D18F2x60_dct1_AddrMask_38_27__WIDTH                     12
#define D18F2x60_dct1_AddrMask_38_27__MASK                      0x7ff80000
#define D18F2x60_dct1_Reserved_31_31_OFFSET                     31
#define D18F2x60_dct1_Reserved_31_31_WIDTH                      1
#define D18F2x60_dct1_Reserved_31_31_MASK                       0x80000000

/// D18F2x60_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_4_0:5 ; ///<
    UINT32                                          AddrMask_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          AddrMask_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x60_dct1_STRUCT;

// **** D18F2x60_dct0 Register Definition ****
// Address
#define D18F2x60_dct0_ADDRESS                                   0x60

// Type
#define D18F2x60_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x60_dct0_Reserved_4_0_OFFSET                       0
#define D18F2x60_dct0_Reserved_4_0_WIDTH                        5
#define D18F2x60_dct0_Reserved_4_0_MASK                         0x1f
#define D18F2x60_dct0_AddrMask_21_11__OFFSET                    5
#define D18F2x60_dct0_AddrMask_21_11__WIDTH                     11
#define D18F2x60_dct0_AddrMask_21_11__MASK                      0xffe0
#define D18F2x60_dct0_Reserved_18_16_OFFSET                     16
#define D18F2x60_dct0_Reserved_18_16_WIDTH                      3
#define D18F2x60_dct0_Reserved_18_16_MASK                       0x70000
#define D18F2x60_dct0_AddrMask_38_27__OFFSET                    19
#define D18F2x60_dct0_AddrMask_38_27__WIDTH                     12
#define D18F2x60_dct0_AddrMask_38_27__MASK                      0x7ff80000
#define D18F2x60_dct0_Reserved_31_31_OFFSET                     31
#define D18F2x60_dct0_Reserved_31_31_WIDTH                      1
#define D18F2x60_dct0_Reserved_31_31_MASK                       0x80000000

/// D18F2x60_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_4_0:5 ; ///<
    UINT32                                          AddrMask_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          AddrMask_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x60_dct0_STRUCT;

// **** D18F2x64_dct0 Register Definition ****
// Address
#define D18F2x64_dct0_ADDRESS                                   0x64

// Type
#define D18F2x64_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x64_dct0_Reserved_4_0_OFFSET                       0
#define D18F2x64_dct0_Reserved_4_0_WIDTH                        5
#define D18F2x64_dct0_Reserved_4_0_MASK                         0x1f
#define D18F2x64_dct0_AddrMask_21_11__OFFSET                    5
#define D18F2x64_dct0_AddrMask_21_11__WIDTH                     11
#define D18F2x64_dct0_AddrMask_21_11__MASK                      0xffe0
#define D18F2x64_dct0_Reserved_18_16_OFFSET                     16
#define D18F2x64_dct0_Reserved_18_16_WIDTH                      3
#define D18F2x64_dct0_Reserved_18_16_MASK                       0x70000
#define D18F2x64_dct0_AddrMask_38_27__OFFSET                    19
#define D18F2x64_dct0_AddrMask_38_27__WIDTH                     12
#define D18F2x64_dct0_AddrMask_38_27__MASK                      0x7ff80000
#define D18F2x64_dct0_Reserved_31_31_OFFSET                     31
#define D18F2x64_dct0_Reserved_31_31_WIDTH                      1
#define D18F2x64_dct0_Reserved_31_31_MASK                       0x80000000

/// D18F2x64_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_4_0:5 ; ///<
    UINT32                                          AddrMask_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          AddrMask_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x64_dct0_STRUCT;

// **** D18F2x64_dct1 Register Definition ****
// Address
#define D18F2x64_dct1_ADDRESS                                   0x64

// Type
#define D18F2x64_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x64_dct1_Reserved_4_0_OFFSET                       0
#define D18F2x64_dct1_Reserved_4_0_WIDTH                        5
#define D18F2x64_dct1_Reserved_4_0_MASK                         0x1f
#define D18F2x64_dct1_AddrMask_21_11__OFFSET                    5
#define D18F2x64_dct1_AddrMask_21_11__WIDTH                     11
#define D18F2x64_dct1_AddrMask_21_11__MASK                      0xffe0
#define D18F2x64_dct1_Reserved_18_16_OFFSET                     16
#define D18F2x64_dct1_Reserved_18_16_WIDTH                      3
#define D18F2x64_dct1_Reserved_18_16_MASK                       0x70000
#define D18F2x64_dct1_AddrMask_38_27__OFFSET                    19
#define D18F2x64_dct1_AddrMask_38_27__WIDTH                     12
#define D18F2x64_dct1_AddrMask_38_27__MASK                      0x7ff80000
#define D18F2x64_dct1_Reserved_31_31_OFFSET                     31
#define D18F2x64_dct1_Reserved_31_31_WIDTH                      1
#define D18F2x64_dct1_Reserved_31_31_MASK                       0x80000000

/// D18F2x64_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_4_0:5 ; ///<
    UINT32                                          AddrMask_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          AddrMask_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x64_dct1_STRUCT;

// **** D18F2x68_dct1 Register Definition ****
// Address
#define D18F2x68_dct1_ADDRESS                                   0x68

// Type
#define D18F2x68_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x68_dct1_Reserved_4_0_OFFSET                       0
#define D18F2x68_dct1_Reserved_4_0_WIDTH                        5
#define D18F2x68_dct1_Reserved_4_0_MASK                         0x1f
#define D18F2x68_dct1_AddrMask_21_11__OFFSET                    5
#define D18F2x68_dct1_AddrMask_21_11__WIDTH                     11
#define D18F2x68_dct1_AddrMask_21_11__MASK                      0xffe0
#define D18F2x68_dct1_Reserved_18_16_OFFSET                     16
#define D18F2x68_dct1_Reserved_18_16_WIDTH                      3
#define D18F2x68_dct1_Reserved_18_16_MASK                       0x70000
#define D18F2x68_dct1_AddrMask_38_27__OFFSET                    19
#define D18F2x68_dct1_AddrMask_38_27__WIDTH                     12
#define D18F2x68_dct1_AddrMask_38_27__MASK                      0x7ff80000
#define D18F2x68_dct1_Reserved_31_31_OFFSET                     31
#define D18F2x68_dct1_Reserved_31_31_WIDTH                      1
#define D18F2x68_dct1_Reserved_31_31_MASK                       0x80000000

/// D18F2x68_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_4_0:5 ; ///<
    UINT32                                          AddrMask_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          AddrMask_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x68_dct1_STRUCT;

// **** D18F2x68_dct0 Register Definition ****
// Address
#define D18F2x68_dct0_ADDRESS                                   0x68

// Type
#define D18F2x68_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x68_dct0_Reserved_4_0_OFFSET                       0
#define D18F2x68_dct0_Reserved_4_0_WIDTH                        5
#define D18F2x68_dct0_Reserved_4_0_MASK                         0x1f
#define D18F2x68_dct0_AddrMask_21_11__OFFSET                    5
#define D18F2x68_dct0_AddrMask_21_11__WIDTH                     11
#define D18F2x68_dct0_AddrMask_21_11__MASK                      0xffe0
#define D18F2x68_dct0_Reserved_18_16_OFFSET                     16
#define D18F2x68_dct0_Reserved_18_16_WIDTH                      3
#define D18F2x68_dct0_Reserved_18_16_MASK                       0x70000
#define D18F2x68_dct0_AddrMask_38_27__OFFSET                    19
#define D18F2x68_dct0_AddrMask_38_27__WIDTH                     12
#define D18F2x68_dct0_AddrMask_38_27__MASK                      0x7ff80000
#define D18F2x68_dct0_Reserved_31_31_OFFSET                     31
#define D18F2x68_dct0_Reserved_31_31_WIDTH                      1
#define D18F2x68_dct0_Reserved_31_31_MASK                       0x80000000

/// D18F2x68_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_4_0:5 ; ///<
    UINT32                                          AddrMask_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          AddrMask_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x68_dct0_STRUCT;

// **** D18F2x6C_dct1 Register Definition ****
// Address
#define D18F2x6C_dct1_ADDRESS                                   0x6c

// Type
#define D18F2x6C_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x6C_dct1_Reserved_4_0_OFFSET                       0
#define D18F2x6C_dct1_Reserved_4_0_WIDTH                        5
#define D18F2x6C_dct1_Reserved_4_0_MASK                         0x1f
#define D18F2x6C_dct1_AddrMask_21_11__OFFSET                    5
#define D18F2x6C_dct1_AddrMask_21_11__WIDTH                     11
#define D18F2x6C_dct1_AddrMask_21_11__MASK                      0xffe0
#define D18F2x6C_dct1_Reserved_18_16_OFFSET                     16
#define D18F2x6C_dct1_Reserved_18_16_WIDTH                      3
#define D18F2x6C_dct1_Reserved_18_16_MASK                       0x70000
#define D18F2x6C_dct1_AddrMask_38_27__OFFSET                    19
#define D18F2x6C_dct1_AddrMask_38_27__WIDTH                     12
#define D18F2x6C_dct1_AddrMask_38_27__MASK                      0x7ff80000
#define D18F2x6C_dct1_Reserved_31_31_OFFSET                     31
#define D18F2x6C_dct1_Reserved_31_31_WIDTH                      1
#define D18F2x6C_dct1_Reserved_31_31_MASK                       0x80000000

/// D18F2x6C_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_4_0:5 ; ///<
    UINT32                                          AddrMask_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          AddrMask_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x6C_dct1_STRUCT;

// **** D18F2x6C_dct0 Register Definition ****
// Address
#define D18F2x6C_dct0_ADDRESS                                   0x6c

// Type
#define D18F2x6C_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x6C_dct0_Reserved_4_0_OFFSET                       0
#define D18F2x6C_dct0_Reserved_4_0_WIDTH                        5
#define D18F2x6C_dct0_Reserved_4_0_MASK                         0x1f
#define D18F2x6C_dct0_AddrMask_21_11__OFFSET                    5
#define D18F2x6C_dct0_AddrMask_21_11__WIDTH                     11
#define D18F2x6C_dct0_AddrMask_21_11__MASK                      0xffe0
#define D18F2x6C_dct0_Reserved_18_16_OFFSET                     16
#define D18F2x6C_dct0_Reserved_18_16_WIDTH                      3
#define D18F2x6C_dct0_Reserved_18_16_MASK                       0x70000
#define D18F2x6C_dct0_AddrMask_38_27__OFFSET                    19
#define D18F2x6C_dct0_AddrMask_38_27__WIDTH                     12
#define D18F2x6C_dct0_AddrMask_38_27__MASK                      0x7ff80000
#define D18F2x6C_dct0_Reserved_31_31_OFFSET                     31
#define D18F2x6C_dct0_Reserved_31_31_WIDTH                      1
#define D18F2x6C_dct0_Reserved_31_31_MASK                       0x80000000

/// D18F2x6C_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_4_0:5 ; ///<
    UINT32                                          AddrMask_21_11_:11; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                          AddrMask_38_27_:12; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x6C_dct0_STRUCT;

// **** D18F2x78_dct0 Register Definition ****
// Address
#define D18F2x78_dct0_ADDRESS                                   0x78

// Type
#define D18F2x78_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x78_dct0_Reserved_16_0_OFFSET                      0
#define D18F2x78_dct0_Reserved_16_0_WIDTH                       17
#define D18F2x78_dct0_Reserved_16_0_MASK                        0x1ffff
#define D18F2x78_dct0_AddrCmdTriEn_OFFSET                       17
#define D18F2x78_dct0_AddrCmdTriEn_WIDTH                        1
#define D18F2x78_dct0_AddrCmdTriEn_MASK                         0x20000
#define D18F2x78_dct0_Reserved_31_18_OFFSET                     18
#define D18F2x78_dct0_Reserved_31_18_WIDTH                      14
#define D18F2x78_dct0_Reserved_31_18_MASK                       0xfffc0000

/// D18F2x78_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_16_0:17; ///<
    UINT32                                             AddrCmdTriEn:1 ; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x78_dct0_STRUCT;

// **** D18F2x78_dct1 Register Definition ****
// Address
#define D18F2x78_dct1_ADDRESS                                   0x78

// Type
#define D18F2x78_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x78_dct1_Reserved_16_0_OFFSET                      0
#define D18F2x78_dct1_Reserved_16_0_WIDTH                       17
#define D18F2x78_dct1_Reserved_16_0_MASK                        0x1ffff
#define D18F2x78_dct1_AddrCmdTriEn_OFFSET                       17
#define D18F2x78_dct1_AddrCmdTriEn_WIDTH                        1
#define D18F2x78_dct1_AddrCmdTriEn_MASK                         0x20000
#define D18F2x78_dct1_Reserved_31_18_OFFSET                     18
#define D18F2x78_dct1_Reserved_31_18_WIDTH                      14
#define D18F2x78_dct1_Reserved_31_18_MASK                       0xfffc0000

/// D18F2x78_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_16_0:17; ///<
    UINT32                                             AddrCmdTriEn:1 ; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x78_dct1_STRUCT;

// **** D18F2x7C_dct1 Register Definition ****
// Address
#define D18F2x7C_dct1_ADDRESS                                   0x7c

// Type
#define D18F2x7C_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x7C_dct1_MrsAddress_17_0__OFFSET                   0
#define D18F2x7C_dct1_MrsAddress_17_0__WIDTH                    18
#define D18F2x7C_dct1_MrsAddress_17_0__MASK                     0x3ffff
#define D18F2x7C_dct1_MrsBank_2_0__OFFSET                       18
#define D18F2x7C_dct1_MrsBank_2_0__WIDTH                        3
#define D18F2x7C_dct1_MrsBank_2_0__MASK                         0x1c0000
#define D18F2x7C_dct1_MrsChipSel_OFFSET                         21
#define D18F2x7C_dct1_MrsChipSel_WIDTH                          3
#define D18F2x7C_dct1_MrsChipSel_MASK                           0xe00000
#define D18F2x7C_dct1_Reserved_24_24_OFFSET                     24
#define D18F2x7C_dct1_Reserved_24_24_WIDTH                      1
#define D18F2x7C_dct1_Reserved_24_24_MASK                       0x1000000
#define D18F2x7C_dct1_SendAutoRefresh_OFFSET                    25
#define D18F2x7C_dct1_SendAutoRefresh_WIDTH                     1
#define D18F2x7C_dct1_SendAutoRefresh_MASK                      0x2000000
#define D18F2x7C_dct1_SendMrsCmd_OFFSET                         26
#define D18F2x7C_dct1_SendMrsCmd_WIDTH                          1
#define D18F2x7C_dct1_SendMrsCmd_MASK                           0x4000000
#define D18F2x7C_dct1_DeassertMemRstX_OFFSET                    27
#define D18F2x7C_dct1_DeassertMemRstX_WIDTH                     1
#define D18F2x7C_dct1_DeassertMemRstX_MASK                      0x8000000
#define D18F2x7C_dct1_AssertCke_OFFSET                          28
#define D18F2x7C_dct1_AssertCke_WIDTH                           1
#define D18F2x7C_dct1_AssertCke_MASK                            0x10000000
#define D18F2x7C_dct1_SendZQCmd_OFFSET                          29
#define D18F2x7C_dct1_SendZQCmd_WIDTH                           1
#define D18F2x7C_dct1_SendZQCmd_MASK                            0x20000000
#define D18F2x7C_dct1_SendControlWord_OFFSET                    30
#define D18F2x7C_dct1_SendControlWord_WIDTH                     1
#define D18F2x7C_dct1_SendControlWord_MASK                      0x40000000
#define D18F2x7C_dct1_EnDramInit_OFFSET                         31
#define D18F2x7C_dct1_EnDramInit_WIDTH                          1
#define D18F2x7C_dct1_EnDramInit_MASK                           0x80000000

/// D18F2x7C_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                         MrsAddress_17_0_:18; ///<
    UINT32                                             MrsBank_2_0_:3 ; ///<
    UINT32                                               MrsChipSel:3 ; ///<
    UINT32                                           Reserved_24_24:1 ; ///<
    UINT32                                          SendAutoRefresh:1 ; ///<
    UINT32                                               SendMrsCmd:1 ; ///<
    UINT32                                          DeassertMemRstX:1 ; ///<
    UINT32                                                AssertCke:1 ; ///<
    UINT32                                                SendZQCmd:1 ; ///<
    UINT32                                          SendControlWord:1 ; ///<
    UINT32                                               EnDramInit:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x7C_dct1_STRUCT;

// **** D18F2x7C_dct0 Register Definition ****
// Address
#define D18F2x7C_dct0_ADDRESS                                   0x7c

// Type
#define D18F2x7C_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x7C_dct0_MrsAddress_17_0__OFFSET                   0
#define D18F2x7C_dct0_MrsAddress_17_0__WIDTH                    18
#define D18F2x7C_dct0_MrsAddress_17_0__MASK                     0x3ffff
#define D18F2x7C_dct0_MrsBank_2_0__OFFSET                       18
#define D18F2x7C_dct0_MrsBank_2_0__WIDTH                        3
#define D18F2x7C_dct0_MrsBank_2_0__MASK                         0x1c0000
#define D18F2x7C_dct0_MrsChipSel_OFFSET                         21
#define D18F2x7C_dct0_MrsChipSel_WIDTH                          3
#define D18F2x7C_dct0_MrsChipSel_MASK                           0xe00000
#define D18F2x7C_dct0_Reserved_24_24_OFFSET                     24
#define D18F2x7C_dct0_Reserved_24_24_WIDTH                      1
#define D18F2x7C_dct0_Reserved_24_24_MASK                       0x1000000
#define D18F2x7C_dct0_SendAutoRefresh_OFFSET                    25
#define D18F2x7C_dct0_SendAutoRefresh_WIDTH                     1
#define D18F2x7C_dct0_SendAutoRefresh_MASK                      0x2000000
#define D18F2x7C_dct0_SendMrsCmd_OFFSET                         26
#define D18F2x7C_dct0_SendMrsCmd_WIDTH                          1
#define D18F2x7C_dct0_SendMrsCmd_MASK                           0x4000000
#define D18F2x7C_dct0_DeassertMemRstX_OFFSET                    27
#define D18F2x7C_dct0_DeassertMemRstX_WIDTH                     1
#define D18F2x7C_dct0_DeassertMemRstX_MASK                      0x8000000
#define D18F2x7C_dct0_AssertCke_OFFSET                          28
#define D18F2x7C_dct0_AssertCke_WIDTH                           1
#define D18F2x7C_dct0_AssertCke_MASK                            0x10000000
#define D18F2x7C_dct0_SendZQCmd_OFFSET                          29
#define D18F2x7C_dct0_SendZQCmd_WIDTH                           1
#define D18F2x7C_dct0_SendZQCmd_MASK                            0x20000000
#define D18F2x7C_dct0_SendControlWord_OFFSET                    30
#define D18F2x7C_dct0_SendControlWord_WIDTH                     1
#define D18F2x7C_dct0_SendControlWord_MASK                      0x40000000
#define D18F2x7C_dct0_EnDramInit_OFFSET                         31
#define D18F2x7C_dct0_EnDramInit_WIDTH                          1
#define D18F2x7C_dct0_EnDramInit_MASK                           0x80000000

/// D18F2x7C_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                         MrsAddress_17_0_:18; ///<
    UINT32                                             MrsBank_2_0_:3 ; ///<
    UINT32                                               MrsChipSel:3 ; ///<
    UINT32                                           Reserved_24_24:1 ; ///<
    UINT32                                          SendAutoRefresh:1 ; ///<
    UINT32                                               SendMrsCmd:1 ; ///<
    UINT32                                          DeassertMemRstX:1 ; ///<
    UINT32                                                AssertCke:1 ; ///<
    UINT32                                                SendZQCmd:1 ; ///<
    UINT32                                          SendControlWord:1 ; ///<
    UINT32                                               EnDramInit:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x7C_dct0_STRUCT;

// **** D18F2x80_dct1 Register Definition ****
// Address
#define D18F2x80_dct1_ADDRESS                                   0x80

// Type
#define D18F2x80_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x80_dct1_DimmAddrMap0_OFFSET                       0
#define D18F2x80_dct1_DimmAddrMap0_WIDTH                        4
#define D18F2x80_dct1_DimmAddrMap0_MASK                         0xf
#define D18F2x80_dct1_DimmAddrMap1_OFFSET                       4
#define D18F2x80_dct1_DimmAddrMap1_WIDTH                        4
#define D18F2x80_dct1_DimmAddrMap1_MASK                         0xf0
#define D18F2x80_dct1_DimmAddrMap2_OFFSET                       8
#define D18F2x80_dct1_DimmAddrMap2_WIDTH                        4
#define D18F2x80_dct1_DimmAddrMap2_MASK                         0xf00
#define D18F2x80_dct1_DimmAddrMap3_OFFSET                       12
#define D18F2x80_dct1_DimmAddrMap3_WIDTH                        4
#define D18F2x80_dct1_DimmAddrMap3_MASK                         0xf000
#define D18F2x80_dct1_Reserved_31_16_OFFSET                     16
#define D18F2x80_dct1_Reserved_31_16_WIDTH                      16
#define D18F2x80_dct1_Reserved_31_16_MASK                       0xffff0000

/// D18F2x80_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             DimmAddrMap0:4 ; ///<
    UINT32                                             DimmAddrMap1:4 ; ///<
    UINT32                                             DimmAddrMap2:4 ; ///<
    UINT32                                             DimmAddrMap3:4 ; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x80_dct1_STRUCT;

// **** D18F2x80_dct0 Register Definition ****
// Address
#define D18F2x80_dct0_ADDRESS                                   0x80

// Type
#define D18F2x80_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x80_dct0_DimmAddrMap0_OFFSET                       0
#define D18F2x80_dct0_DimmAddrMap0_WIDTH                        4
#define D18F2x80_dct0_DimmAddrMap0_MASK                         0xf
#define D18F2x80_dct0_DimmAddrMap1_OFFSET                       4
#define D18F2x80_dct0_DimmAddrMap1_WIDTH                        4
#define D18F2x80_dct0_DimmAddrMap1_MASK                         0xf0
#define D18F2x80_dct0_DimmAddrMap2_OFFSET                       8
#define D18F2x80_dct0_DimmAddrMap2_WIDTH                        4
#define D18F2x80_dct0_DimmAddrMap2_MASK                         0xf00
#define D18F2x80_dct0_DimmAddrMap3_OFFSET                       12
#define D18F2x80_dct0_DimmAddrMap3_WIDTH                        4
#define D18F2x80_dct0_DimmAddrMap3_MASK                         0xf000
#define D18F2x80_dct0_Reserved_31_16_OFFSET                     16
#define D18F2x80_dct0_Reserved_31_16_WIDTH                      16
#define D18F2x80_dct0_Reserved_31_16_MASK                       0xffff0000

/// D18F2x80_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             DimmAddrMap0:4 ; ///<
    UINT32                                             DimmAddrMap1:4 ; ///<
    UINT32                                             DimmAddrMap2:4 ; ///<
    UINT32                                             DimmAddrMap3:4 ; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x80_dct0_STRUCT;

// **** D18F2x84_dct1 Register Definition ****
// Address
#define D18F2x84_dct1_ADDRESS                                   0x84

// Type
#define D18F2x84_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x84_dct1_BurstCtrl_OFFSET                          0
#define D18F2x84_dct1_BurstCtrl_WIDTH                           2
#define D18F2x84_dct1_BurstCtrl_MASK                            0x3
#define D18F2x84_dct1_Reserved_22_2_OFFSET                      2
#define D18F2x84_dct1_Reserved_22_2_WIDTH                       21
#define D18F2x84_dct1_Reserved_22_2_MASK                        0x7ffffc
#define D18F2x84_dct1_PchgPDModeSel_OFFSET                      23
#define D18F2x84_dct1_PchgPDModeSel_WIDTH                       1
#define D18F2x84_dct1_PchgPDModeSel_MASK                        0x800000
#define D18F2x84_dct1_Reserved_31_24_OFFSET                     24
#define D18F2x84_dct1_Reserved_31_24_WIDTH                      8
#define D18F2x84_dct1_Reserved_31_24_MASK                       0xff000000

/// D18F2x84_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                BurstCtrl:2 ; ///<
    UINT32                                            Reserved_22_2:21; ///<
    UINT32                                            PchgPDModeSel:1 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x84_dct1_STRUCT;

// **** D18F2x84_dct0 Register Definition ****
// Address
#define D18F2x84_dct0_ADDRESS                                   0x84

// Type
#define D18F2x84_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x84_dct0_BurstCtrl_OFFSET                          0
#define D18F2x84_dct0_BurstCtrl_WIDTH                           2
#define D18F2x84_dct0_BurstCtrl_MASK                            0x3
#define D18F2x84_dct0_Reserved_22_2_OFFSET                      2
#define D18F2x84_dct0_Reserved_22_2_WIDTH                       21
#define D18F2x84_dct0_Reserved_22_2_MASK                        0x7ffffc
#define D18F2x84_dct0_PchgPDModeSel_OFFSET                      23
#define D18F2x84_dct0_PchgPDModeSel_WIDTH                       1
#define D18F2x84_dct0_PchgPDModeSel_MASK                        0x800000
#define D18F2x84_dct0_Reserved_31_24_OFFSET                     24
#define D18F2x84_dct0_Reserved_31_24_WIDTH                      8
#define D18F2x84_dct0_Reserved_31_24_MASK                       0xff000000

/// D18F2x84_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                BurstCtrl:2 ; ///<
    UINT32                                            Reserved_22_2:21; ///<
    UINT32                                            PchgPDModeSel:1 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x84_dct0_STRUCT;

// **** D18F2x88_dct1 Register Definition ****
// Address
#define D18F2x88_dct1_ADDRESS                                   0x88

// Type
#define D18F2x88_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x88_dct1_Reserved_23_0_OFFSET                      0
#define D18F2x88_dct1_Reserved_23_0_WIDTH                       24
#define D18F2x88_dct1_Reserved_23_0_MASK                        0xffffff
#define D18F2x88_dct1_MemClkDis_OFFSET                          24
#define D18F2x88_dct1_MemClkDis_WIDTH                           6
#define D18F2x88_dct1_MemClkDis_MASK                            0x3f000000
#define D18F2x88_dct1_Reserved_31_30_OFFSET                     30
#define D18F2x88_dct1_Reserved_31_30_WIDTH                      2
#define D18F2x88_dct1_Reserved_31_30_MASK                       0xc0000000

/// D18F2x88_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_23_0:24; ///<
    UINT32                                                MemClkDis:6 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x88_dct1_STRUCT;

// **** D18F2x88_dct0 Register Definition ****
// Address
#define D18F2x88_dct0_ADDRESS                                   0x88

// Type
#define D18F2x88_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x88_dct0_Reserved_23_0_OFFSET                      0
#define D18F2x88_dct0_Reserved_23_0_WIDTH                       24
#define D18F2x88_dct0_Reserved_23_0_MASK                        0xffffff
#define D18F2x88_dct0_MemClkDis_OFFSET                          24
#define D18F2x88_dct0_MemClkDis_WIDTH                           6
#define D18F2x88_dct0_MemClkDis_MASK                            0x3f000000
#define D18F2x88_dct0_Reserved_31_30_OFFSET                     30
#define D18F2x88_dct0_Reserved_31_30_WIDTH                      2
#define D18F2x88_dct0_Reserved_31_30_MASK                       0xc0000000

/// D18F2x88_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_23_0:24; ///<
    UINT32                                                MemClkDis:6 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x88_dct0_STRUCT;

// **** D18F2x8C_dct1 Register Definition ****
// Address
#define D18F2x8C_dct1_ADDRESS                                   0x8c

// Type
#define D18F2x8C_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x8C_dct1_Reserved_15_0_OFFSET                      0
#define D18F2x8C_dct1_Reserved_15_0_WIDTH                       16
#define D18F2x8C_dct1_Reserved_15_0_MASK                        0xffff
#define D18F2x8C_dct1_Tref_OFFSET                               16
#define D18F2x8C_dct1_Tref_WIDTH                                2
#define D18F2x8C_dct1_Tref_MASK                                 0x30000
#define D18F2x8C_dct1_DisAutoRefresh_OFFSET                     18
#define D18F2x8C_dct1_DisAutoRefresh_WIDTH                      1
#define D18F2x8C_dct1_DisAutoRefresh_MASK                       0x40000
#define D18F2x8C_dct1_Reserved_31_19_OFFSET                     19
#define D18F2x8C_dct1_Reserved_31_19_WIDTH                      13
#define D18F2x8C_dct1_Reserved_31_19_MASK                       0xfff80000

/// D18F2x8C_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_15_0:16; ///<
    UINT32                                                     Tref:2 ; ///<
    UINT32                                           DisAutoRefresh:1 ; ///<
    UINT32                                           Reserved_31_19:13; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x8C_dct1_STRUCT;

// **** D18F2x8C_dct0 Register Definition ****
// Address
#define D18F2x8C_dct0_ADDRESS                                   0x8c

// Type
#define D18F2x8C_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x8C_dct0_Reserved_15_0_OFFSET                      0
#define D18F2x8C_dct0_Reserved_15_0_WIDTH                       16
#define D18F2x8C_dct0_Reserved_15_0_MASK                        0xffff
#define D18F2x8C_dct0_Tref_OFFSET                               16
#define D18F2x8C_dct0_Tref_WIDTH                                2
#define D18F2x8C_dct0_Tref_MASK                                 0x30000
#define D18F2x8C_dct0_DisAutoRefresh_OFFSET                     18
#define D18F2x8C_dct0_DisAutoRefresh_WIDTH                      1
#define D18F2x8C_dct0_DisAutoRefresh_MASK                       0x40000
#define D18F2x8C_dct0_Reserved_31_19_OFFSET                     19
#define D18F2x8C_dct0_Reserved_31_19_WIDTH                      13
#define D18F2x8C_dct0_Reserved_31_19_MASK                       0xfff80000

/// D18F2x8C_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_15_0:16; ///<
    UINT32                                                     Tref:2 ; ///<
    UINT32                                           DisAutoRefresh:1 ; ///<
    UINT32                                           Reserved_31_19:13; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x8C_dct0_STRUCT;

// **** D18F2x90_dct0 Register Definition ****
// Address
#define D18F2x90_dct0_ADDRESS                                   0x90

// Type
#define D18F2x90_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x90_dct0_Reserved_0_0_OFFSET                       0
#define D18F2x90_dct0_Reserved_0_0_WIDTH                        1
#define D18F2x90_dct0_Reserved_0_0_MASK                         0x1
#define D18F2x90_dct0_ExitSelfRef_OFFSET                        1
#define D18F2x90_dct0_ExitSelfRef_WIDTH                         1
#define D18F2x90_dct0_ExitSelfRef_MASK                          0x2
#define D18F2x90_dct0_Reserved_7_2_OFFSET                       2
#define D18F2x90_dct0_Reserved_7_2_WIDTH                        6
#define D18F2x90_dct0_Reserved_7_2_MASK                         0xfc
#define D18F2x90_dct0_Reserved_8_8_OFFSET                       8
#define D18F2x90_dct0_Reserved_8_8_WIDTH                        1
#define D18F2x90_dct0_Reserved_8_8_MASK                         0x100
#define D18F2x90_dct0_Reserved_11_9_OFFSET                      9
#define D18F2x90_dct0_Reserved_11_9_WIDTH                       3
#define D18F2x90_dct0_Reserved_11_9_MASK                        0xe00
#define D18F2x90_dct0_Reserved_15_12_OFFSET                     12
#define D18F2x90_dct0_Reserved_15_12_WIDTH                      4
#define D18F2x90_dct0_Reserved_15_12_MASK                       0xf000
#define D18F2x90_dct0_UnbuffDimm_OFFSET                         16
#define D18F2x90_dct0_UnbuffDimm_WIDTH                          1
#define D18F2x90_dct0_UnbuffDimm_MASK                           0x10000
#define D18F2x90_dct0_EnterSelfRef_OFFSET                       17
#define D18F2x90_dct0_EnterSelfRef_WIDTH                        1
#define D18F2x90_dct0_EnterSelfRef_MASK                         0x20000
#define D18F2x90_dct0_PendRefPayback_OFFSET                     18
#define D18F2x90_dct0_PendRefPayback_WIDTH                      1
#define D18F2x90_dct0_PendRefPayback_MASK                       0x40000
#define D18F2x90_dct0_Reserved_19_19_OFFSET                     19
#define D18F2x90_dct0_Reserved_19_19_WIDTH                      1
#define D18F2x90_dct0_Reserved_19_19_MASK                       0x80000
#define D18F2x90_dct0_DynPageCloseEn_OFFSET                     20
#define D18F2x90_dct0_DynPageCloseEn_WIDTH                      1
#define D18F2x90_dct0_DynPageCloseEn_MASK                       0x100000
#define D18F2x90_dct0_IdleCycLowLimit_OFFSET                    21
#define D18F2x90_dct0_IdleCycLowLimit_WIDTH                     2
#define D18F2x90_dct0_IdleCycLowLimit_MASK                      0x600000
#define D18F2x90_dct0_ForceAutoPchg_OFFSET                      23
#define D18F2x90_dct0_ForceAutoPchg_WIDTH                       1
#define D18F2x90_dct0_ForceAutoPchg_MASK                        0x800000
#define D18F2x90_dct0_StagRefEn_OFFSET                          24
#define D18F2x90_dct0_StagRefEn_WIDTH                           1
#define D18F2x90_dct0_StagRefEn_MASK                            0x1000000
#define D18F2x90_dct0_PendRefPaybackS3En_OFFSET                 25
#define D18F2x90_dct0_PendRefPaybackS3En_WIDTH                  1
#define D18F2x90_dct0_PendRefPaybackS3En_MASK                   0x2000000
#define D18F2x90_dct0_Reserved_26_26_OFFSET                     26
#define D18F2x90_dct0_Reserved_26_26_WIDTH                      1
#define D18F2x90_dct0_Reserved_26_26_MASK                       0x4000000
#define D18F2x90_dct0_DisDllShutdownSR_OFFSET                   27
#define D18F2x90_dct0_DisDllShutdownSR_WIDTH                    1
#define D18F2x90_dct0_DisDllShutdownSR_MASK                     0x8000000
#define D18F2x90_dct0_Reserved_31_28_OFFSET                     28
#define D18F2x90_dct0_Reserved_31_28_WIDTH                      4
#define D18F2x90_dct0_Reserved_31_28_MASK                       0xf0000000

/// D18F2x90_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                              ExitSelfRef:1 ; ///<
    UINT32                                             Reserved_7_2:6 ; ///<
    UINT32                                             Reserved_8_8:1 ; ///<
    UINT32                                            Reserved_11_9:3 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                               UnbuffDimm:1 ; ///<
    UINT32                                             EnterSelfRef:1 ; ///<
    UINT32                                           PendRefPayback:1 ; ///<
    UINT32                                           Reserved_19_19:1 ; ///<
    UINT32                                           DynPageCloseEn:1 ; ///<
    UINT32                                          IdleCycLowLimit:2 ; ///<
    UINT32                                            ForceAutoPchg:1 ; ///<
    UINT32                                                StagRefEn:1 ; ///<
    UINT32                                       PendRefPaybackS3En:1 ; ///<
    UINT32                                           Reserved_26_26:1 ; ///<
    UINT32                                         DisDllShutdownSR:1 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x90_dct0_STRUCT;

// **** D18F2x90_dct1 Register Definition ****
// Address
#define D18F2x90_dct1_ADDRESS                                   0x90

// Type
#define D18F2x90_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x90_dct1_Reserved_0_0_OFFSET                       0
#define D18F2x90_dct1_Reserved_0_0_WIDTH                        1
#define D18F2x90_dct1_Reserved_0_0_MASK                         0x1
#define D18F2x90_dct1_ExitSelfRef_OFFSET                        1
#define D18F2x90_dct1_ExitSelfRef_WIDTH                         1
#define D18F2x90_dct1_ExitSelfRef_MASK                          0x2
#define D18F2x90_dct1_Reserved_7_2_OFFSET                       2
#define D18F2x90_dct1_Reserved_7_2_WIDTH                        6
#define D18F2x90_dct1_Reserved_7_2_MASK                         0xfc
#define D18F2x90_dct1_Reserved_8_8_OFFSET                       8
#define D18F2x90_dct1_Reserved_8_8_WIDTH                        1
#define D18F2x90_dct1_Reserved_8_8_MASK                         0x100
#define D18F2x90_dct1_Reserved_11_9_OFFSET                      9
#define D18F2x90_dct1_Reserved_11_9_WIDTH                       3
#define D18F2x90_dct1_Reserved_11_9_MASK                        0xe00
#define D18F2x90_dct1_Reserved_15_12_OFFSET                     12
#define D18F2x90_dct1_Reserved_15_12_WIDTH                      4
#define D18F2x90_dct1_Reserved_15_12_MASK                       0xf000
#define D18F2x90_dct1_UnbuffDimm_OFFSET                         16
#define D18F2x90_dct1_UnbuffDimm_WIDTH                          1
#define D18F2x90_dct1_UnbuffDimm_MASK                           0x10000
#define D18F2x90_dct1_EnterSelfRef_OFFSET                       17
#define D18F2x90_dct1_EnterSelfRef_WIDTH                        1
#define D18F2x90_dct1_EnterSelfRef_MASK                         0x20000
#define D18F2x90_dct1_PendRefPayback_OFFSET                     18
#define D18F2x90_dct1_PendRefPayback_WIDTH                      1
#define D18F2x90_dct1_PendRefPayback_MASK                       0x40000
#define D18F2x90_dct1_Reserved_19_19_OFFSET                     19
#define D18F2x90_dct1_Reserved_19_19_WIDTH                      1
#define D18F2x90_dct1_Reserved_19_19_MASK                       0x80000
#define D18F2x90_dct1_DynPageCloseEn_OFFSET                     20
#define D18F2x90_dct1_DynPageCloseEn_WIDTH                      1
#define D18F2x90_dct1_DynPageCloseEn_MASK                       0x100000
#define D18F2x90_dct1_IdleCycLowLimit_OFFSET                    21
#define D18F2x90_dct1_IdleCycLowLimit_WIDTH                     2
#define D18F2x90_dct1_IdleCycLowLimit_MASK                      0x600000
#define D18F2x90_dct1_ForceAutoPchg_OFFSET                      23
#define D18F2x90_dct1_ForceAutoPchg_WIDTH                       1
#define D18F2x90_dct1_ForceAutoPchg_MASK                        0x800000
#define D18F2x90_dct1_StagRefEn_OFFSET                          24
#define D18F2x90_dct1_StagRefEn_WIDTH                           1
#define D18F2x90_dct1_StagRefEn_MASK                            0x1000000
#define D18F2x90_dct1_PendRefPaybackS3En_OFFSET                 25
#define D18F2x90_dct1_PendRefPaybackS3En_WIDTH                  1
#define D18F2x90_dct1_PendRefPaybackS3En_MASK                   0x2000000
#define D18F2x90_dct1_Reserved_26_26_OFFSET                     26
#define D18F2x90_dct1_Reserved_26_26_WIDTH                      1
#define D18F2x90_dct1_Reserved_26_26_MASK                       0x4000000
#define D18F2x90_dct1_DisDllShutdownSR_OFFSET                   27
#define D18F2x90_dct1_DisDllShutdownSR_WIDTH                    1
#define D18F2x90_dct1_DisDllShutdownSR_MASK                     0x8000000
#define D18F2x90_dct1_Reserved_31_28_OFFSET                     28
#define D18F2x90_dct1_Reserved_31_28_WIDTH                      4
#define D18F2x90_dct1_Reserved_31_28_MASK                       0xf0000000

/// D18F2x90_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                              ExitSelfRef:1 ; ///<
    UINT32                                             Reserved_7_2:6 ; ///<
    UINT32                                             Reserved_8_8:1 ; ///<
    UINT32                                            Reserved_11_9:3 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                               UnbuffDimm:1 ; ///<
    UINT32                                             EnterSelfRef:1 ; ///<
    UINT32                                           PendRefPayback:1 ; ///<
    UINT32                                           Reserved_19_19:1 ; ///<
    UINT32                                           DynPageCloseEn:1 ; ///<
    UINT32                                          IdleCycLowLimit:2 ; ///<
    UINT32                                            ForceAutoPchg:1 ; ///<
    UINT32                                                StagRefEn:1 ; ///<
    UINT32                                       PendRefPaybackS3En:1 ; ///<
    UINT32                                           Reserved_26_26:1 ; ///<
    UINT32                                         DisDllShutdownSR:1 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x90_dct1_STRUCT;

// **** D18F2x94_dct1 Register Definition ****
// Address
#define D18F2x94_dct1_ADDRESS                                   0x94

// Type
#define D18F2x94_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x94_dct1_MemClkFreq_OFFSET                         0
#define D18F2x94_dct1_MemClkFreq_WIDTH                          5
#define D18F2x94_dct1_MemClkFreq_MASK                           0x1f
#define D18F2x94_dct1_Reserved_6_5_OFFSET                       5
#define D18F2x94_dct1_Reserved_6_5_WIDTH                        2
#define D18F2x94_dct1_Reserved_6_5_MASK                         0x60
#define D18F2x94_dct1_MemClkFreqVal_OFFSET                      7
#define D18F2x94_dct1_MemClkFreqVal_WIDTH                       1
#define D18F2x94_dct1_MemClkFreqVal_MASK                        0x80
#define D18F2x94_dct1_Reserved_9_8_OFFSET                       8
#define D18F2x94_dct1_Reserved_9_8_WIDTH                        2
#define D18F2x94_dct1_Reserved_9_8_MASK                         0x300
#define D18F2x94_dct1_ZqcsInterval_OFFSET                       10
#define D18F2x94_dct1_ZqcsInterval_WIDTH                        2
#define D18F2x94_dct1_ZqcsInterval_MASK                         0xc00
#define D18F2x94_dct1_Reserved_12_12_OFFSET                     12
#define D18F2x94_dct1_Reserved_12_12_WIDTH                      1
#define D18F2x94_dct1_Reserved_12_12_MASK                       0x1000
#define D18F2x94_dct1_Reserved_13_13_OFFSET                     13
#define D18F2x94_dct1_Reserved_13_13_WIDTH                      1
#define D18F2x94_dct1_Reserved_13_13_MASK                       0x2000
#define D18F2x94_dct1_DisDramInterface_OFFSET                   14
#define D18F2x94_dct1_DisDramInterface_WIDTH                    1
#define D18F2x94_dct1_DisDramInterface_MASK                     0x4000
#define D18F2x94_dct1_PowerDownEn_OFFSET                        15
#define D18F2x94_dct1_PowerDownEn_WIDTH                         1
#define D18F2x94_dct1_PowerDownEn_MASK                          0x8000
#define D18F2x94_dct1_PowerDownMode_OFFSET                      16
#define D18F2x94_dct1_PowerDownMode_WIDTH                       1
#define D18F2x94_dct1_PowerDownMode_MASK                        0x10000
#define D18F2x94_dct1_Reserved_18_17_OFFSET                     17
#define D18F2x94_dct1_Reserved_18_17_WIDTH                      2
#define D18F2x94_dct1_Reserved_18_17_MASK                       0x60000
#define D18F2x94_dct1_SlowAccessMode_OFFSET                     20
#define D18F2x94_dct1_SlowAccessMode_WIDTH                      1
#define D18F2x94_dct1_SlowAccessMode_MASK                       0x100000
#define D18F2x94_dct1_FreqChgInProg_OFFSET                      21
#define D18F2x94_dct1_FreqChgInProg_WIDTH                       1
#define D18F2x94_dct1_FreqChgInProg_MASK                        0x200000
#define D18F2x94_dct1_BankSwizzleMode_OFFSET                    22
#define D18F2x94_dct1_BankSwizzleMode_WIDTH                     1
#define D18F2x94_dct1_BankSwizzleMode_MASK                      0x400000
#define D18F2x94_dct1_ProcOdtDis_OFFSET                         23
#define D18F2x94_dct1_ProcOdtDis_WIDTH                          1
#define D18F2x94_dct1_ProcOdtDis_MASK                           0x800000
#define D18F2x94_dct1_DcqBypassMax_OFFSET                       24
#define D18F2x94_dct1_DcqBypassMax_WIDTH                        5
#define D18F2x94_dct1_DcqBypassMax_MASK                         0x1f000000
#define D18F2x94_dct1_Reserved_30_29_OFFSET                     29
#define D18F2x94_dct1_Reserved_30_29_WIDTH                      2
#define D18F2x94_dct1_Reserved_30_29_MASK                       0x60000000
#define D18F2x94_dct1_DphyMemPsSelEn_OFFSET                     31
#define D18F2x94_dct1_DphyMemPsSelEn_WIDTH                      1
#define D18F2x94_dct1_DphyMemPsSelEn_MASK                       0x80000000

/// D18F2x94_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                               MemClkFreq:5 ; ///<
    UINT32                                             Reserved_6_5:2 ; ///<
    UINT32                                            MemClkFreqVal:1 ; ///<
    UINT32                                             Reserved_9_8:2 ; ///<
    UINT32                                             ZqcsInterval:2 ; ///<
    UINT32                                           Reserved_12_12:1 ; ///<
    UINT32                                           Reserved_13_13:1 ; ///<
    UINT32                                         DisDramInterface:1 ; ///<
    UINT32                                              PowerDownEn:1 ; ///<
    UINT32                                            PowerDownMode:1 ; ///<
    UINT32                                           Reserved_18_17:2 ; ///<
    UINT32                                           DcqArbBypassEn:1 ; ///<
    UINT32                                           SlowAccessMode:1 ; ///<
    UINT32                                            FreqChgInProg:1 ; ///<
    UINT32                                          BankSwizzleMode:1 ; ///<
    UINT32                                               ProcOdtDis:1 ; ///<
    UINT32                                             DcqBypassMax:5 ; ///<
    UINT32                                           Reserved_30_29:2 ; ///<
    UINT32                                           DphyMemPsSelEn:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x94_dct1_STRUCT;

// **** D18F2x94_dct0 Register Definition ****
// Address
#define D18F2x94_dct0_ADDRESS                                   0x94

// Type
#define D18F2x94_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x94_dct0_MemClkFreq_OFFSET                         0
#define D18F2x94_dct0_MemClkFreq_WIDTH                          5
#define D18F2x94_dct0_MemClkFreq_MASK                           0x1f
#define D18F2x94_dct0_Reserved_6_5_OFFSET                       5
#define D18F2x94_dct0_Reserved_6_5_WIDTH                        2
#define D18F2x94_dct0_Reserved_6_5_MASK                         0x60
#define D18F2x94_dct0_MemClkFreqVal_OFFSET                      7
#define D18F2x94_dct0_MemClkFreqVal_WIDTH                       1
#define D18F2x94_dct0_MemClkFreqVal_MASK                        0x80
#define D18F2x94_dct0_Reserved_9_8_OFFSET                       8
#define D18F2x94_dct0_Reserved_9_8_WIDTH                        2
#define D18F2x94_dct0_Reserved_9_8_MASK                         0x300
#define D18F2x94_dct0_ZqcsInterval_OFFSET                       10
#define D18F2x94_dct0_ZqcsInterval_WIDTH                        2
#define D18F2x94_dct0_ZqcsInterval_MASK                         0xc00
#define D18F2x94_dct0_Reserved_12_12_OFFSET                     12
#define D18F2x94_dct0_Reserved_12_12_WIDTH                      1
#define D18F2x94_dct0_Reserved_12_12_MASK                       0x1000
#define D18F2x94_dct0_Reserved_13_13_OFFSET                     13
#define D18F2x94_dct0_Reserved_13_13_WIDTH                      1
#define D18F2x94_dct0_Reserved_13_13_MASK                       0x2000
#define D18F2x94_dct0_DisDramInterface_OFFSET                   14
#define D18F2x94_dct0_DisDramInterface_WIDTH                    1
#define D18F2x94_dct0_DisDramInterface_MASK                     0x4000
#define D18F2x94_dct0_PowerDownEn_OFFSET                        15
#define D18F2x94_dct0_PowerDownEn_WIDTH                         1
#define D18F2x94_dct0_PowerDownEn_MASK                          0x8000
#define D18F2x94_dct0_PowerDownMode_OFFSET                      16
#define D18F2x94_dct0_PowerDownMode_WIDTH                       1
#define D18F2x94_dct0_PowerDownMode_MASK                        0x10000
#define D18F2x94_dct0_Reserved_18_17_OFFSET                     17
#define D18F2x94_dct0_Reserved_18_17_WIDTH                      2
#define D18F2x94_dct0_Reserved_18_17_MASK                       0x60000
#define D18F2x94_dct0_SlowAccessMode_OFFSET                     20
#define D18F2x94_dct0_SlowAccessMode_WIDTH                      1
#define D18F2x94_dct0_SlowAccessMode_MASK                       0x100000
#define D18F2x94_dct0_FreqChgInProg_OFFSET                      21
#define D18F2x94_dct0_FreqChgInProg_WIDTH                       1
#define D18F2x94_dct0_FreqChgInProg_MASK                        0x200000
#define D18F2x94_dct0_BankSwizzleMode_OFFSET                    22
#define D18F2x94_dct0_BankSwizzleMode_WIDTH                     1
#define D18F2x94_dct0_BankSwizzleMode_MASK                      0x400000
#define D18F2x94_dct0_ProcOdtDis_OFFSET                         23
#define D18F2x94_dct0_ProcOdtDis_WIDTH                          1
#define D18F2x94_dct0_ProcOdtDis_MASK                           0x800000
#define D18F2x94_dct0_DcqBypassMax_OFFSET                       24
#define D18F2x94_dct0_DcqBypassMax_WIDTH                        5
#define D18F2x94_dct0_DcqBypassMax_MASK                         0x1f000000
#define D18F2x94_dct0_Reserved_30_29_OFFSET                     29
#define D18F2x94_dct0_Reserved_30_29_WIDTH                      2
#define D18F2x94_dct0_Reserved_30_29_MASK                       0x60000000
#define D18F2x94_dct0_DphyMemPsSelEn_OFFSET                     31
#define D18F2x94_dct0_DphyMemPsSelEn_WIDTH                      1
#define D18F2x94_dct0_DphyMemPsSelEn_MASK                       0x80000000

/// D18F2x94_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                               MemClkFreq:5 ; ///<
    UINT32                                             Reserved_6_5:2 ; ///<
    UINT32                                            MemClkFreqVal:1 ; ///<
    UINT32                                             Reserved_9_8:2 ; ///<
    UINT32                                             ZqcsInterval:2 ; ///<
    UINT32                                           Reserved_12_12:1 ; ///<
    UINT32                                           Reserved_13_13:1 ; ///<
    UINT32                                         DisDramInterface:1 ; ///<
    UINT32                                              PowerDownEn:1 ; ///<
    UINT32                                            PowerDownMode:1 ; ///<
    UINT32                                           Reserved_18_17:2 ; ///<
    UINT32                                           DcqArbBypassEn:1 ; ///<
    UINT32                                           SlowAccessMode:1 ; ///<
    UINT32                                            FreqChgInProg:1 ; ///<
    UINT32                                          BankSwizzleMode:1 ; ///<
    UINT32                                               ProcOdtDis:1 ; ///<
    UINT32                                             DcqBypassMax:5 ; ///<
    UINT32                                           Reserved_30_29:2 ; ///<
    UINT32                                           DphyMemPsSelEn:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x94_dct0_STRUCT;

// **** D18F2x98_dct0 Register Definition ****
// Address
#define D18F2x98_dct0_ADDRESS                                   0x98

// Type
#define D18F2x98_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x98_dct0_DctOffset_OFFSET                          0
#define D18F2x98_dct0_DctOffset_WIDTH                           30
#define D18F2x98_dct0_DctOffset_MASK                            0x3fffffff
#define D18F2x98_dct0_DctAccessWrite_OFFSET                     30
#define D18F2x98_dct0_DctAccessWrite_WIDTH                      1
#define D18F2x98_dct0_DctAccessWrite_MASK                       0x40000000
#define D18F2x98_dct0_Reserved_31_31_OFFSET                     31
#define D18F2x98_dct0_Reserved_31_31_WIDTH                      1
#define D18F2x98_dct0_Reserved_31_31_MASK                       0x80000000

/// D18F2x98_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                DctOffset:30; ///<
    UINT32                                           DctAccessWrite:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x98_dct0_STRUCT;

// **** D18F2x98_dct1 Register Definition ****
// Address
#define D18F2x98_dct1_ADDRESS                                   0x98

// Type
#define D18F2x98_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x98_dct1_DctOffset_OFFSET                          0
#define D18F2x98_dct1_DctOffset_WIDTH                           30
#define D18F2x98_dct1_DctOffset_MASK                            0x3fffffff
#define D18F2x98_dct1_DctAccessWrite_OFFSET                     30
#define D18F2x98_dct1_DctAccessWrite_WIDTH                      1
#define D18F2x98_dct1_DctAccessWrite_MASK                       0x40000000
#define D18F2x98_dct1_Reserved_31_31_OFFSET                     31
#define D18F2x98_dct1_Reserved_31_31_WIDTH                      1
#define D18F2x98_dct1_Reserved_31_31_MASK                       0x80000000

/// D18F2x98_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                DctOffset:30; ///<
    UINT32                                           DctAccessWrite:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x98_dct1_STRUCT;

// **** D18F2x9C_dct1 Register Definition ****
// Address
#define D18F2x9C_dct1_ADDRESS                                   0x9c

// Type
#define D18F2x9C_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2x9C_dct1_Data_OFFSET                               0
#define D18F2x9C_dct1_Data_WIDTH                                32
#define D18F2x9C_dct1_Data_MASK                                 0xffffffff

/// D18F2x9C_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                     Data:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_dct1_STRUCT;

// **** D18F2x9C_dct0 Register Definition ****
// Address
#define D18F2x9C_dct0_ADDRESS                                   0x9c

// Type
#define D18F2x9C_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2x9C_dct0_Data_OFFSET                               0
#define D18F2x9C_dct0_Data_WIDTH                                32
#define D18F2x9C_dct0_Data_MASK                                 0xffffffff

/// D18F2x9C_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                     Data:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_dct0_STRUCT;

// **** D18F2xA4 Register Definition ****
// Address
#define D18F2xA4_ADDRESS                                        0xa4

// Type
#define D18F2xA4_TYPE                                           TYPE_D18F2
// Field Data
#define D18F2xA4_Reserved_7_0_OFFSET                            0
#define D18F2xA4_Reserved_7_0_WIDTH                             8
#define D18F2xA4_Reserved_7_0_MASK                              0xff
#define D18F2xA4_ODTSEn_OFFSET                                  8
#define D18F2xA4_ODTSEn_WIDTH                                   1
#define D18F2xA4_ODTSEn_MASK                                    0x100
#define D18F2xA4_Reserved_10_9_OFFSET                           9
#define D18F2xA4_Reserved_10_9_WIDTH                            2
#define D18F2xA4_Reserved_10_9_MASK                             0x600
#define D18F2xA4_BwCapEn_OFFSET                                 11
#define D18F2xA4_BwCapEn_WIDTH                                  1
#define D18F2xA4_BwCapEn_MASK                                   0x800
#define D18F2xA4_CmdThrottleMode_OFFSET                         12
#define D18F2xA4_CmdThrottleMode_WIDTH                          3
#define D18F2xA4_CmdThrottleMode_MASK                           0x7000
#define D18F2xA4_Reserved_19_15_OFFSET                          15
#define D18F2xA4_Reserved_19_15_WIDTH                           5
#define D18F2xA4_Reserved_19_15_MASK                            0xf8000
#define D18F2xA4_BwCapCmdThrottleMode_OFFSET                    20
#define D18F2xA4_BwCapCmdThrottleMode_WIDTH                     4
#define D18F2xA4_BwCapCmdThrottleMode_MASK                      0xf00000
#define D18F2xA4_Reserved_31_24_OFFSET                          24
#define D18F2xA4_Reserved_31_24_WIDTH                           8
#define D18F2xA4_Reserved_31_24_MASK                            0xff000000

/// D18F2xA4
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_7_0:8 ; ///<
    UINT32                                                   ODTSEn:1 ; ///<
    UINT32                                            Reserved_10_9:2 ; ///<
    UINT32                                                  BwCapEn:1 ; ///<
    UINT32                                          CmdThrottleMode:3 ; ///<
    UINT32                                           Reserved_19_15:5 ; ///<
    UINT32                                     BwCapCmdThrottleMode:4 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2xA4_STRUCT;

// **** D18F2xA8_dct0 Register Definition ****
// Address
#define D18F2xA8_dct0_ADDRESS                                   0xa8

// Type
#define D18F2xA8_dct0_TYPE                                      TYPE_D18F2_dct0
// Field Data
#define D18F2xA8_dct0_Reserved_1_0_OFFSET                       0
#define D18F2xA8_dct0_Reserved_1_0_WIDTH                        2
#define D18F2xA8_dct0_Reserved_1_0_MASK                         0x3
#define D18F2xA8_dct0_CSTimingMux67_OFFSET                      2
#define D18F2xA8_dct0_CSTimingMux67_WIDTH                       1
#define D18F2xA8_dct0_CSTimingMux67_MASK                        0x4
#define D18F2xA8_dct0_Reserved_3_3_OFFSET                       3
#define D18F2xA8_dct0_Reserved_3_3_WIDTH                        1
#define D18F2xA8_dct0_Reserved_3_3_MASK                         0x8
#define D18F2xA8_dct0_Reserved_4_4_OFFSET                       4
#define D18F2xA8_dct0_Reserved_4_4_WIDTH                        1
#define D18F2xA8_dct0_Reserved_4_4_MASK                         0x10
#define D18F2xA8_dct0_SubMemclkRegDly_OFFSET                    5
#define D18F2xA8_dct0_SubMemclkRegDly_WIDTH                     1
#define D18F2xA8_dct0_SubMemclkRegDly_MASK                      0x20
#define D18F2xA8_dct0_Reserved_7_6_OFFSET                       6
#define D18F2xA8_dct0_Reserved_7_6_WIDTH                        2
#define D18F2xA8_dct0_Reserved_7_6_MASK                         0xc0
#define D18F2xA8_dct0_CtrlWordCS_7_0__OFFSET                    8
#define D18F2xA8_dct0_CtrlWordCS_7_0__WIDTH                     8
#define D18F2xA8_dct0_CtrlWordCS_7_0__MASK                      0xff00
#define D18F2xA8_dct0_MemPhyPllPdMode_OFFSET                    16
#define D18F2xA8_dct0_MemPhyPllPdMode_WIDTH                     2
#define D18F2xA8_dct0_MemPhyPllPdMode_MASK                      0x30000
#define D18F2xA8_dct0_Reserved_19_18_OFFSET                     18
#define D18F2xA8_dct0_Reserved_19_18_WIDTH                      2
#define D18F2xA8_dct0_Reserved_19_18_MASK                       0xc0000
#define D18F2xA8_dct0_BankSwap_OFFSET                           20
#define D18F2xA8_dct0_BankSwap_WIDTH                            1
#define D18F2xA8_dct0_BankSwap_MASK                             0x100000
#define D18F2xA8_dct0_AggrPDEn_OFFSET                           21
#define D18F2xA8_dct0_AggrPDEn_WIDTH                            1
#define D18F2xA8_dct0_AggrPDEn_MASK                             0x200000
#define D18F2xA8_dct0_PrtlChPDEnhEn_OFFSET                      22
#define D18F2xA8_dct0_PrtlChPDEnhEn_WIDTH                       1
#define D18F2xA8_dct0_PrtlChPDEnhEn_MASK                        0x400000
#define D18F2xA8_dct0_Reserved_23_23_OFFSET                     23
#define D18F2xA8_dct0_Reserved_23_23_WIDTH                      1
#define D18F2xA8_dct0_Reserved_23_23_MASK                       0x800000
#define D18F2xA8_dct0_Reserved_25_24_OFFSET                     24
#define D18F2xA8_dct0_Reserved_25_24_WIDTH                      2
#define D18F2xA8_dct0_Reserved_25_24_MASK                       0x3000000
#define D18F2xA8_dct0_CsMux45_OFFSET                            26
#define D18F2xA8_dct0_CsMux45_WIDTH                             1
#define D18F2xA8_dct0_CsMux45_MASK                              0x4000000
#define D18F2xA8_dct0_CsMux67_OFFSET                            27
#define D18F2xA8_dct0_CsMux67_WIDTH                             1
#define D18F2xA8_dct0_CsMux67_MASK                              0x8000000
#define D18F2xA8_dct0_FastSelfRefEntryDis_OFFSET                28
#define D18F2xA8_dct0_FastSelfRefEntryDis_WIDTH                 1
#define D18F2xA8_dct0_FastSelfRefEntryDis_MASK                  0x10000000
#define D18F2xA8_dct0_RefChCmdMgtDis_OFFSET                     29
#define D18F2xA8_dct0_RefChCmdMgtDis_WIDTH                      1
#define D18F2xA8_dct0_RefChCmdMgtDis_MASK                       0x20000000
#define D18F2xA8_dct0_Reserved_30_30_OFFSET                     30
#define D18F2xA8_dct0_Reserved_30_30_WIDTH                      1
#define D18F2xA8_dct0_Reserved_30_30_MASK                       0x40000000
#define D18F2xA8_dct0_PerRankTimingEn_OFFSET                    31
#define D18F2xA8_dct0_PerRankTimingEn_WIDTH                     1
#define D18F2xA8_dct0_PerRankTimingEn_MASK                      0x80000000

/// D18F2xA8_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_1_0:2 ; ///<
    UINT32                                            CSTimingMux67:1 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          SubMemclkRegDly:1 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                          CtrlWordCS_7_0_:8 ; ///<
    UINT32                                          MemPhyPllPdMode:2 ; ///<
    UINT32                                           Reserved_19_18:2 ; ///<
    UINT32                                                 BankSwap:1 ; ///<
    UINT32                                                 AggrPDEn:1 ; ///<
    UINT32                                            PrtlChPDEnhEn:1 ; ///<
    UINT32                                           Reserved_23_23:1 ; ///<
    UINT32                                           Reserved_25_24:2 ; ///<
    UINT32                                                  CsMux45:1 ; ///<
    UINT32                                                  CsMux67:1 ; ///<
    UINT32                                      FastSelfRefEntryDis:1 ; ///<
    UINT32                                           RefChCmdMgtDis:1 ; ///<
    UINT32                                           Reserved_30_30:1 ; ///<
    UINT32                                          PerRankTimingEn:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2xA8_dct0_STRUCT;

// **** D18F2xA8_dct1 Register Definition ****
// Address
#define D18F2xA8_dct1_ADDRESS                                   0xa8

// Type
#define D18F2xA8_dct1_TYPE                                      TYPE_D18F2_dct1
// Field Data
#define D18F2xA8_dct1_Reserved_1_0_OFFSET                       0
#define D18F2xA8_dct1_Reserved_1_0_WIDTH                        2
#define D18F2xA8_dct1_Reserved_1_0_MASK                         0x3
#define D18F2xA8_dct1_CSTimingMux67_OFFSET                      2
#define D18F2xA8_dct1_CSTimingMux67_WIDTH                       1
#define D18F2xA8_dct1_CSTimingMux67_MASK                        0x4
#define D18F2xA8_dct1_Reserved_3_3_OFFSET                       3
#define D18F2xA8_dct1_Reserved_3_3_WIDTH                        1
#define D18F2xA8_dct1_Reserved_3_3_MASK                         0x8
#define D18F2xA8_dct1_Reserved_4_4_OFFSET                       4
#define D18F2xA8_dct1_Reserved_4_4_WIDTH                        1
#define D18F2xA8_dct1_Reserved_4_4_MASK                         0x10
#define D18F2xA8_dct1_SubMemclkRegDly_OFFSET                    5
#define D18F2xA8_dct1_SubMemclkRegDly_WIDTH                     1
#define D18F2xA8_dct1_SubMemclkRegDly_MASK                      0x20
#define D18F2xA8_dct1_Reserved_7_6_OFFSET                       6
#define D18F2xA8_dct1_Reserved_7_6_WIDTH                        2
#define D18F2xA8_dct1_Reserved_7_6_MASK                         0xc0
#define D18F2xA8_dct1_CtrlWordCS_7_0__OFFSET                    8
#define D18F2xA8_dct1_CtrlWordCS_7_0__WIDTH                     8
#define D18F2xA8_dct1_CtrlWordCS_7_0__MASK                      0xff00
#define D18F2xA8_dct1_MemPhyPllPdMode_OFFSET                    16
#define D18F2xA8_dct1_MemPhyPllPdMode_WIDTH                     2
#define D18F2xA8_dct1_MemPhyPllPdMode_MASK                      0x30000
#define D18F2xA8_dct1_Reserved_19_18_OFFSET                     18
#define D18F2xA8_dct1_Reserved_19_18_WIDTH                      2
#define D18F2xA8_dct1_Reserved_19_18_MASK                       0xc0000
#define D18F2xA8_dct1_BankSwap_OFFSET                           20
#define D18F2xA8_dct1_BankSwap_WIDTH                            1
#define D18F2xA8_dct1_BankSwap_MASK                             0x100000
#define D18F2xA8_dct1_AggrPDEn_OFFSET                           21
#define D18F2xA8_dct1_AggrPDEn_WIDTH                            1
#define D18F2xA8_dct1_AggrPDEn_MASK                             0x200000
#define D18F2xA8_dct1_PrtlChPDEnhEn_OFFSET                      22
#define D18F2xA8_dct1_PrtlChPDEnhEn_WIDTH                       1
#define D18F2xA8_dct1_PrtlChPDEnhEn_MASK                        0x400000
#define D18F2xA8_dct1_Reserved_23_23_OFFSET                     23
#define D18F2xA8_dct1_Reserved_23_23_WIDTH                      1
#define D18F2xA8_dct1_Reserved_23_23_MASK                       0x800000
#define D18F2xA8_dct1_Reserved_25_24_OFFSET                     24
#define D18F2xA8_dct1_Reserved_25_24_WIDTH                      2
#define D18F2xA8_dct1_Reserved_25_24_MASK                       0x3000000
#define D18F2xA8_dct1_CsMux45_OFFSET                            26
#define D18F2xA8_dct1_CsMux45_WIDTH                             1
#define D18F2xA8_dct1_CsMux45_MASK                              0x4000000
#define D18F2xA8_dct1_CsMux67_OFFSET                            27
#define D18F2xA8_dct1_CsMux67_WIDTH                             1
#define D18F2xA8_dct1_CsMux67_MASK                              0x8000000
#define D18F2xA8_dct1_FastSelfRefEntryDis_OFFSET                28
#define D18F2xA8_dct1_FastSelfRefEntryDis_WIDTH                 1
#define D18F2xA8_dct1_FastSelfRefEntryDis_MASK                  0x10000000
#define D18F2xA8_dct1_RefChCmdMgtDis_OFFSET                     29
#define D18F2xA8_dct1_RefChCmdMgtDis_WIDTH                      1
#define D18F2xA8_dct1_RefChCmdMgtDis_MASK                       0x20000000
#define D18F2xA8_dct1_Reserved_30_30_OFFSET                     30
#define D18F2xA8_dct1_Reserved_30_30_WIDTH                      1
#define D18F2xA8_dct1_Reserved_30_30_MASK                       0x40000000
#define D18F2xA8_dct1_PerRankTimingEn_OFFSET                    31
#define D18F2xA8_dct1_PerRankTimingEn_WIDTH                     1
#define D18F2xA8_dct1_PerRankTimingEn_MASK                      0x80000000

/// D18F2xA8_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_1_0:2 ; ///<
    UINT32                                            CSTimingMux67:1 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                          SubMemclkRegDly:1 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                          CtrlWordCS_7_0_:8 ; ///<
    UINT32                                          MemPhyPllPdMode:2 ; ///<
    UINT32                                           Reserved_19_18:2 ; ///<
    UINT32                                                 BankSwap:1 ; ///<
    UINT32                                                 AggrPDEn:1 ; ///<
    UINT32                                            PrtlChPDEnhEn:1 ; ///<
    UINT32                                           Reserved_23_23:1 ; ///<
    UINT32                                           Reserved_25_24:2 ; ///<
    UINT32                                                  CsMux45:1 ; ///<
    UINT32                                                  CsMux67:1 ; ///<
    UINT32                                      FastSelfRefEntryDis:1 ; ///<
    UINT32                                           RefChCmdMgtDis:1 ; ///<
    UINT32                                           Reserved_30_30:1 ; ///<
    UINT32                                          PerRankTimingEn:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2xA8_dct1_STRUCT;

// **** D18F2xAC Register Definition ****
// Address
#define D18F2xAC_ADDRESS                                        0xac

// Type
#define D18F2xAC_TYPE                                           TYPE_D18F2
// Field Data
#define D18F2xAC_MemTempHot0_OFFSET                             0
#define D18F2xAC_MemTempHot0_WIDTH                              1
#define D18F2xAC_MemTempHot0_MASK                               0x1
#define D18F2xAC_Reserved_1_1_OFFSET                            1
#define D18F2xAC_Reserved_1_1_WIDTH                             1
#define D18F2xAC_Reserved_1_1_MASK                              0x2
#define D18F2xAC_MemTempHot1_OFFSET                             2
#define D18F2xAC_MemTempHot1_WIDTH                              1
#define D18F2xAC_MemTempHot1_MASK                               0x4
#define D18F2xAC_Reserved_31_3_OFFSET                           3
#define D18F2xAC_Reserved_31_3_WIDTH                            29
#define D18F2xAC_Reserved_31_3_MASK                             0xfffffff8

/// D18F2xAC
typedef union {
  struct {                                                              ///<
    UINT32                                              MemTempHot0:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                              MemTempHot1:1 ; ///<
    UINT32                                            Reserved_31_3:29; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2xAC_STRUCT;



// **** D18F2xC4 Register Definition ****
// Address











// **** D18F2xF8 Register Definition ****
// Address
#define D18F2xF8_ADDRESS                                        0xf8

// Type
#define D18F2xF8_TYPE                                           TYPE_D18F2
// Field Data
#define D18F2xF8_PwrValue0_OFFSET                               0
#define D18F2xF8_PwrValue0_WIDTH                                8
#define D18F2xF8_PwrValue0_MASK                                 0xff
#define D18F2xF8_PwrValue1_OFFSET                               8
#define D18F2xF8_PwrValue1_WIDTH                                8
#define D18F2xF8_PwrValue1_MASK                                 0xff00
#define D18F2xF8_PwrValue2_OFFSET                               16
#define D18F2xF8_PwrValue2_WIDTH                                8
#define D18F2xF8_PwrValue2_MASK                                 0xff0000
#define D18F2xF8_PwrValue3_OFFSET                               24
#define D18F2xF8_PwrValue3_WIDTH                                8
#define D18F2xF8_PwrValue3_MASK                                 0xff000000

/// D18F2xF8
typedef union {
  struct {                                                              ///<
    UINT32                                                PwrValue0:8 ; ///<
    UINT32                                                PwrValue1:8 ; ///<
    UINT32                                                PwrValue2:8 ; ///<
    UINT32                                                PwrValue3:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2xF8_STRUCT;


// **** D18F2x104 Register Definition ****
// Address
#define D18F2x104_ADDRESS                                       0x104

// Type
#define D18F2x104_TYPE                                          TYPE_D18F2
// Field Data
#define D18F2x104_PwrValue5_OFFSET                              0
#define D18F2x104_PwrValue5_WIDTH                               8
#define D18F2x104_PwrValue5_MASK                                0xff
#define D18F2x104_PwrValue6_OFFSET                              8
#define D18F2x104_PwrValue6_WIDTH                               8
#define D18F2x104_PwrValue6_MASK                                0xff00
#define D18F2x104_PwrValue7_OFFSET                              16
#define D18F2x104_PwrValue7_WIDTH                               8
#define D18F2x104_PwrValue7_MASK                                0xff0000
#define D18F2x104_Reserved_31_24_OFFSET                         24
#define D18F2x104_Reserved_31_24_WIDTH                          8
#define D18F2x104_Reserved_31_24_MASK                           0xff000000

/// D18F2x104
typedef union {
  struct {                                                              ///<
    UINT32                                                PwrValue5:8 ; ///<
    UINT32                                                PwrValue6:8 ; ///<
    UINT32                                                PwrValue7:8 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x104_STRUCT;

// **** D18F2x10C Register Definition ****
// Address
#define D18F2x10C_ADDRESS                                       0x10c

// Type
#define D18F2x10C_TYPE                                          TYPE_D18F2
// Field Data
#define D18F2x10C_IntLvRgnSwapEn_OFFSET                         0
#define D18F2x10C_IntLvRgnSwapEn_WIDTH                          1
#define D18F2x10C_IntLvRgnSwapEn_MASK                           0x1
#define D18F2x10C_Reserved_2_1_OFFSET                           1
#define D18F2x10C_Reserved_2_1_WIDTH                            2
#define D18F2x10C_Reserved_2_1_MASK                             0x6
#define D18F2x10C_IntLvRgnBaseAddr_33_27__OFFSET                3
#define D18F2x10C_IntLvRgnBaseAddr_33_27__WIDTH                 7
#define D18F2x10C_IntLvRgnBaseAddr_33_27__MASK                  0x3f8
#define D18F2x10C_Reserved_10_10_OFFSET                         10
#define D18F2x10C_Reserved_10_10_WIDTH                          1
#define D18F2x10C_Reserved_10_10_MASK                           0x400
#define D18F2x10C_IntLvRgnLmtAddr_33_27__OFFSET                 11
#define D18F2x10C_IntLvRgnLmtAddr_33_27__WIDTH                  7
#define D18F2x10C_IntLvRgnLmtAddr_33_27__MASK                   0x3f800
#define D18F2x10C_Reserved_19_18_OFFSET                         18
#define D18F2x10C_Reserved_19_18_WIDTH                          2
#define D18F2x10C_Reserved_19_18_MASK                           0xc0000
#define D18F2x10C_IntLvRgnSize_33_27__OFFSET                    20
#define D18F2x10C_IntLvRgnSize_33_27__WIDTH                     7
#define D18F2x10C_IntLvRgnSize_33_27__MASK                      0x7f00000
#define D18F2x10C_Reserved_31_27_OFFSET                         27
#define D18F2x10C_Reserved_31_27_WIDTH                          5
#define D18F2x10C_Reserved_31_27_MASK                           0xf8000000

/// D18F2x10C
typedef union {
  struct {                                                              ///<
    UINT32                                           IntLvRgnSwapEn:1 ; ///<
    UINT32                                             Reserved_2_1:2 ; ///<
    UINT32                                  IntLvRgnBaseAddr_33_27_:7 ; ///<
    UINT32                                           Reserved_10_10:1 ; ///<
    UINT32                                   IntLvRgnLmtAddr_33_27_:7 ; ///<
    UINT32                                           Reserved_19_18:2 ; ///<
    UINT32                                      IntLvRgnSize_33_27_:7 ; ///<
    UINT32                                           Reserved_31_27:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x10C_STRUCT;

// **** D18F2x110 Register Definition ****
// Address
#define D18F2x110_ADDRESS                                       0x110

// Type
#define D18F2x110_TYPE                                          TYPE_D18F2
// Field Data
#define D18F2x110_DctSelHiRngEn_OFFSET                          0
#define D18F2x110_DctSelHiRngEn_WIDTH                           1
#define D18F2x110_DctSelHiRngEn_MASK                            0x1
#define D18F2x110_DctSelHi_OFFSET                               1
#define D18F2x110_DctSelHi_WIDTH                                1
#define D18F2x110_DctSelHi_MASK                                 0x2
#define D18F2x110_DctSelIntLvEn_OFFSET                          2
#define D18F2x110_DctSelIntLvEn_WIDTH                           1
#define D18F2x110_DctSelIntLvEn_MASK                            0x4
#define D18F2x110_MemClrInit_OFFSET                             3
#define D18F2x110_MemClrInit_WIDTH                              1
#define D18F2x110_MemClrInit_MASK                               0x8
#define D18F2x110_Reserved_4_4_OFFSET                           4
#define D18F2x110_Reserved_4_4_WIDTH                            1
#define D18F2x110_Reserved_4_4_MASK                             0x10
#define D18F2x110_DctDatIntLv_OFFSET                            5
#define D18F2x110_DctDatIntLv_WIDTH                             1
#define D18F2x110_DctDatIntLv_MASK                              0x20
#define D18F2x110_DctSelIntLvAddr_1_0__OFFSET                   6
#define D18F2x110_DctSelIntLvAddr_1_0__WIDTH                    2
#define D18F2x110_DctSelIntLvAddr_1_0__MASK                     0xc0
#define D18F2x110_DramEnable_OFFSET                             8
#define D18F2x110_DramEnable_WIDTH                              1
#define D18F2x110_DramEnable_MASK                               0x100
#define D18F2x110_MemClrBusy_OFFSET                             9
#define D18F2x110_MemClrBusy_WIDTH                              1
#define D18F2x110_MemClrBusy_MASK                               0x200
#define D18F2x110_MemCleared_OFFSET                             10
#define D18F2x110_MemCleared_WIDTH                              1
#define D18F2x110_MemCleared_MASK                               0x400
#define D18F2x110_DctSelBaseAddr_47_27__OFFSET                  11
#define D18F2x110_DctSelBaseAddr_47_27__WIDTH                   21
#define D18F2x110_DctSelBaseAddr_47_27__MASK                    0xfffff800

/// D18F2x110
typedef union {
  struct {                                                              ///<
    UINT32                                            DctSelHiRngEn:1 ; ///<
    UINT32                                                 DctSelHi:1 ; ///<
    UINT32                                            DctSelIntLvEn:1 ; ///<
    UINT32                                               MemClrInit:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                              DctDatIntLv:1 ; ///<
    UINT32                                     DctSelIntLvAddr_1_0_:2 ; ///<
    UINT32                                               DramEnable:1 ; ///<
    UINT32                                               MemClrBusy:1 ; ///<
    UINT32                                               MemCleared:1 ; ///<
    UINT32                                    DctSelBaseAddr_47_27_:21; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x110_STRUCT;

// **** D18F2x114 Register Definition ****
// Address
#define D18F2x114_ADDRESS                                       0x114

// Type
#define D18F2x114_TYPE                                          TYPE_D18F2
// Field Data
#define D18F2x114_Reserved_8_0_OFFSET                           0
#define D18F2x114_Reserved_8_0_WIDTH                            9
#define D18F2x114_Reserved_8_0_MASK                             0x1ff
#define D18F2x114_DctSelIntLvAddr_2__OFFSET                     9
#define D18F2x114_DctSelIntLvAddr_2__WIDTH                      1
#define D18F2x114_DctSelIntLvAddr_2__MASK                       0x200
#define D18F2x114_DctSelBaseOffset_47_26__OFFSET                10
#define D18F2x114_DctSelBaseOffset_47_26__WIDTH                 22
#define D18F2x114_DctSelBaseOffset_47_26__MASK                  0xfffffc00

/// D18F2x114
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_8_0:9 ; ///<
    UINT32                                       DctSelIntLvAddr_2_:1 ; ///<
    UINT32                                  DctSelBaseOffset_47_26_:22; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x114_STRUCT;

// **** D18F2x118 Register Definition ****
// Address
#define D18F2x118_ADDRESS                                       0x118

// Type
#define D18F2x118_TYPE                                          TYPE_D18F2
// Field Data
#define D18F2x118_MctPriCpuRd_OFFSET                            0
#define D18F2x118_MctPriCpuRd_WIDTH                             2
#define D18F2x118_MctPriCpuRd_MASK                              0x3
#define D18F2x118_MctPriCpuWr_OFFSET                            2
#define D18F2x118_MctPriCpuWr_WIDTH                             2
#define D18F2x118_MctPriCpuWr_MASK                              0xc
#define D18F2x118_MctPriIsocRd_OFFSET                           4
#define D18F2x118_MctPriIsocRd_WIDTH                            2
#define D18F2x118_MctPriIsocRd_MASK                             0x30
#define D18F2x118_MctPriIsocWr_OFFSET                           6
#define D18F2x118_MctPriIsocWr_WIDTH                            2
#define D18F2x118_MctPriIsocWr_MASK                             0xc0
#define D18F2x118_MctPriDefault_OFFSET                          8
#define D18F2x118_MctPriDefault_WIDTH                           2
#define D18F2x118_MctPriDefault_MASK                            0x300
#define D18F2x118_MctPriWr_OFFSET                               10
#define D18F2x118_MctPriWr_WIDTH                                2
#define D18F2x118_MctPriWr_MASK                                 0xc00
#define D18F2x118_MctPriIsoc_OFFSET                             12
#define D18F2x118_MctPriIsoc_WIDTH                              2
#define D18F2x118_MctPriIsoc_MASK                               0x3000
#define D18F2x118_MctPriTrace_OFFSET                            14
#define D18F2x118_MctPriTrace_WIDTH                             2
#define D18F2x118_MctPriTrace_MASK                              0xc000
#define D18F2x118_MctPriScrub_OFFSET                            16
#define D18F2x118_MctPriScrub_WIDTH                             2
#define D18F2x118_MctPriScrub_MASK                              0x30000
#define D18F2x118_CC6SaveEn_OFFSET                              18
#define D18F2x118_CC6SaveEn_WIDTH                               1
#define D18F2x118_CC6SaveEn_MASK                                0x40000
#define D18F2x118_LockDramCfg_OFFSET                            19
#define D18F2x118_LockDramCfg_WIDTH                             1
#define D18F2x118_LockDramCfg_MASK                              0x80000
#define D18F2x118_McqMedPriByPassMax_OFFSET                     20
#define D18F2x118_McqMedPriByPassMax_WIDTH                      3
#define D18F2x118_McqMedPriByPassMax_MASK                       0x700000
#define D18F2x118_Reserved_23_23_OFFSET                         23
#define D18F2x118_Reserved_23_23_WIDTH                          1
#define D18F2x118_Reserved_23_23_MASK                           0x800000
#define D18F2x118_McqHiPriByPassMax_OFFSET                      24
#define D18F2x118_McqHiPriByPassMax_WIDTH                       3
#define D18F2x118_McqHiPriByPassMax_MASK                        0x7000000
#define D18F2x118_MctEccDisLatOptEn_OFFSET                      27
#define D18F2x118_MctEccDisLatOptEn_WIDTH                       1
#define D18F2x118_MctEccDisLatOptEn_MASK                        0x8000000
#define D18F2x118_MctVarPriCntLmt_OFFSET                        28
#define D18F2x118_MctVarPriCntLmt_WIDTH                         4
#define D18F2x118_MctVarPriCntLmt_MASK                          0xf0000000

/// D18F2x118
typedef union {
  struct {                                                              ///<
    UINT32                                              MctPriCpuRd:2 ; ///<
    UINT32                                              MctPriCpuWr:2 ; ///<
    UINT32                                             MctPriIsocRd:2 ; ///<
    UINT32                                             MctPriIsocWr:2 ; ///<
    UINT32                                            MctPriDefault:2 ; ///<
    UINT32                                                 MctPriWr:2 ; ///<
    UINT32                                               MctPriIsoc:2 ; ///<
    UINT32                                              MctPriTrace:2 ; ///<
    UINT32                                              MctPriScrub:2 ; ///<
    UINT32                                                CC6SaveEn:1 ; ///<
    UINT32                                              LockDramCfg:1 ; ///<
    UINT32                                       McqMedPriByPassMax:3 ; ///<
    UINT32                                           Reserved_23_23:1 ; ///<
    UINT32                                        McqHiPriByPassMax:3 ; ///<
    UINT32                                        MctEccDisLatOptEn:1 ; ///<
    UINT32                                          MctVarPriCntLmt:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x118_STRUCT;

// **** D18F2x11C Register Definition ****
// Address
#define D18F2x11C_ADDRESS                                       0x11c

// Type
#define D18F2x11C_TYPE                                          TYPE_D18F2
// Field Data
#define D18F2x11C_DctWrLimit_OFFSET                             0
#define D18F2x11C_DctWrLimit_WIDTH                              2
#define D18F2x11C_DctWrLimit_MASK                               0x3
#define D18F2x11C_MctWrLimit_OFFSET                             2
#define D18F2x11C_MctWrLimit_WIDTH                              5
#define D18F2x11C_MctWrLimit_MASK                               0x7c
#define D18F2x11C_MctPrefReqLimit_OFFSET                        7
#define D18F2x11C_MctPrefReqLimit_WIDTH                         5
#define D18F2x11C_MctPrefReqLimit_MASK                          0xf80
#define D18F2x11C_PrefCpuDis_OFFSET                             12
#define D18F2x11C_PrefCpuDis_WIDTH                              1
#define D18F2x11C_PrefCpuDis_MASK                               0x1000
#define D18F2x11C_PrefIoDis_OFFSET                              13
#define D18F2x11C_PrefIoDis_WIDTH                               1
#define D18F2x11C_PrefIoDis_MASK                                0x2000
#define D18F2x11C_PrefIoFixStrideEn_OFFSET                      14
#define D18F2x11C_PrefIoFixStrideEn_WIDTH                       1
#define D18F2x11C_PrefIoFixStrideEn_MASK                        0x4000
#define D18F2x11C_PrefFixStrideEn_OFFSET                        15
#define D18F2x11C_PrefFixStrideEn_WIDTH                         1
#define D18F2x11C_PrefFixStrideEn_MASK                          0x8000
#define D18F2x11C_PrefFixDist_OFFSET                            16
#define D18F2x11C_PrefFixDist_WIDTH                             2
#define D18F2x11C_PrefFixDist_MASK                              0x30000
#define D18F2x11C_PrefConfSat_OFFSET                            18
#define D18F2x11C_PrefConfSat_WIDTH                             2
#define D18F2x11C_PrefConfSat_MASK                              0xc0000
#define D18F2x11C_PrefOneConf_OFFSET                            20
#define D18F2x11C_PrefOneConf_WIDTH                             2
#define D18F2x11C_PrefOneConf_MASK                              0x300000
#define D18F2x11C_PrefTwoConf_OFFSET                            22
#define D18F2x11C_PrefTwoConf_WIDTH                             3
#define D18F2x11C_PrefTwoConf_MASK                              0x1c00000
#define D18F2x11C_PrefThreeConf_OFFSET                          25
#define D18F2x11C_PrefThreeConf_WIDTH                           3
#define D18F2x11C_PrefThreeConf_MASK                            0xe000000
#define D18F2x11C_PrefDramTrainMode_OFFSET                      28
#define D18F2x11C_PrefDramTrainMode_WIDTH                       1
#define D18F2x11C_PrefDramTrainMode_MASK                        0x10000000
#define D18F2x11C_FlushWrOnStpGnt_OFFSET                        29
#define D18F2x11C_FlushWrOnStpGnt_WIDTH                         1
#define D18F2x11C_FlushWrOnStpGnt_MASK                          0x20000000
#define D18F2x11C_FlushWr_OFFSET                                30
#define D18F2x11C_FlushWr_WIDTH                                 1
#define D18F2x11C_FlushWr_MASK                                  0x40000000
#define D18F2x11C_Reserved_31_31_OFFSET                         31
#define D18F2x11C_Reserved_31_31_WIDTH                          1
#define D18F2x11C_Reserved_31_31_MASK                           0x80000000

/// D18F2x11C
typedef union {
  struct {                                                              ///<
    UINT32                                               DctWrLimit:2 ; ///<
    UINT32                                               MctWrLimit:5 ; ///<
    UINT32                                          MctPrefReqLimit:5 ; ///<
    UINT32                                               PrefCpuDis:1 ; ///<
    UINT32                                                PrefIoDis:1 ; ///<
    UINT32                                        PrefIoFixStrideEn:1 ; ///<
    UINT32                                          PrefFixStrideEn:1 ; ///<
    UINT32                                              PrefFixDist:2 ; ///<
    UINT32                                              PrefConfSat:2 ; ///<
    UINT32                                              PrefOneConf:2 ; ///<
    UINT32                                              PrefTwoConf:3 ; ///<
    UINT32                                            PrefThreeConf:3 ; ///<
    UINT32                                        PrefDramTrainMode:1 ; ///<
    UINT32                                          FlushWrOnStpGnt:1 ; ///<
    UINT32                                                  FlushWr:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x11C_STRUCT;






// **** D18F2x1B0 Register Definition ****
// Address
#define D18F2x1B0_ADDRESS                                       0x1b0

// Type
#define D18F2x1B0_TYPE                                          TYPE_D18F2
// Field Data
#define D18F2x1B0_AdapPrefMissRatio_OFFSET                      0
#define D18F2x1B0_AdapPrefMissRatio_WIDTH                       2
#define D18F2x1B0_AdapPrefMissRatio_MASK                        0x3
#define D18F2x1B0_AdapPrefPositiveStep_OFFSET                   2
#define D18F2x1B0_AdapPrefPositiveStep_WIDTH                    2
#define D18F2x1B0_AdapPrefPositiveStep_MASK                     0xc
#define D18F2x1B0_AdapPrefNegativeStep_OFFSET                   4
#define D18F2x1B0_AdapPrefNegativeStep_WIDTH                    2
#define D18F2x1B0_AdapPrefNegativeStep_MASK                     0x30
#define D18F2x1B0_Reserved_7_6_OFFSET                           6
#define D18F2x1B0_Reserved_7_6_WIDTH                            2
#define D18F2x1B0_Reserved_7_6_MASK                             0xc0
#define D18F2x1B0_CohPrefPrbLmt_OFFSET                          8
#define D18F2x1B0_CohPrefPrbLmt_WIDTH                           3
#define D18F2x1B0_CohPrefPrbLmt_MASK                            0x700
#define D18F2x1B0_DisIoCohPref_OFFSET                           11
#define D18F2x1B0_DisIoCohPref_WIDTH                            1
#define D18F2x1B0_DisIoCohPref_MASK                             0x800
#define D18F2x1B0_EnSplitDctLimits_OFFSET                       12
#define D18F2x1B0_EnSplitDctLimits_WIDTH                        1
#define D18F2x1B0_EnSplitDctLimits_MASK                         0x1000
#define D18F2x1B0_Reserved_17_13_OFFSET                         13
#define D18F2x1B0_Reserved_17_13_WIDTH                          5
#define D18F2x1B0_Reserved_17_13_MASK                           0x3e000
#define D18F2x1B0_Reserved_19_18_OFFSET                         18
#define D18F2x1B0_Reserved_19_18_WIDTH                          2
#define D18F2x1B0_Reserved_19_18_MASK                           0xc0000
#define D18F2x1B0_DblPrefEn_OFFSET                              20
#define D18F2x1B0_DblPrefEn_WIDTH                               1
#define D18F2x1B0_DblPrefEn_MASK                                0x100000
#define D18F2x1B0_Reserved_21_21_OFFSET                         21
#define D18F2x1B0_Reserved_21_21_WIDTH                          1
#define D18F2x1B0_Reserved_21_21_MASK                           0x200000
#define D18F2x1B0_PrefFourConf_OFFSET                           22
#define D18F2x1B0_PrefFourConf_WIDTH                            3
#define D18F2x1B0_PrefFourConf_MASK                             0x1c00000
#define D18F2x1B0_PrefFiveConf_OFFSET                           25
#define D18F2x1B0_PrefFiveConf_WIDTH                            3
#define D18F2x1B0_PrefFiveConf_MASK                             0xe000000
#define D18F2x1B0_DcqBwThrotWm_OFFSET                           28
#define D18F2x1B0_DcqBwThrotWm_WIDTH                            4
#define D18F2x1B0_DcqBwThrotWm_MASK                             0xf0000000

/// D18F2x1B0
typedef union {
  struct {                                                              ///<
    UINT32                                        AdapPrefMissRatio:2 ; ///<
    UINT32                                     AdapPrefPositiveStep:2 ; ///<
    UINT32                                     AdapPrefNegativeStep:2 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                            CohPrefPrbLmt:3 ; ///<
    UINT32                                             DisIoCohPref:1 ; ///<
    UINT32                                         EnSplitDctLimits:1 ; ///<
    UINT32                                           Reserved_17_13:5 ; ///<
    UINT32                                           Reserved_19_18:2 ; ///<
    UINT32                                                DblPrefEn:1 ; ///<
    UINT32                                           Reserved_21_21:1 ; ///<
    UINT32                                             PrefFourConf:3 ; ///<
    UINT32                                             PrefFiveConf:3 ; ///<
    UINT32                                             DcqBwThrotWm:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x1B0_STRUCT;

// **** D18F2x1B4 Register Definition ****
// Address
#define D18F2x1B4_ADDRESS                                       0x1b4

// Type
#define D18F2x1B4_TYPE                                          TYPE_D18F2
// Field Data
#define D18F2x1B4_DcqBwThrotWm1_OFFSET                          0
#define D18F2x1B4_DcqBwThrotWm1_WIDTH                           5
#define D18F2x1B4_DcqBwThrotWm1_MASK                            0x1f
#define D18F2x1B4_DcqBwThrotWm2_OFFSET                          5
#define D18F2x1B4_DcqBwThrotWm2_WIDTH                           5
#define D18F2x1B4_DcqBwThrotWm2_MASK                            0x3e0
#define D18F2x1B4_DemandPropWm1_OFFSET                          10
#define D18F2x1B4_DemandPropWm1_WIDTH                           1
#define D18F2x1B4_DemandPropWm1_MASK                            0x400
#define D18F2x1B4_DemandAlloWm1_OFFSET                          11
#define D18F2x1B4_DemandAlloWm1_WIDTH                           1
#define D18F2x1B4_DemandAlloWm1_MASK                            0x800
#define D18F2x1B4_StridePropWm1_OFFSET                          12
#define D18F2x1B4_StridePropWm1_WIDTH                           1
#define D18F2x1B4_StridePropWm1_MASK                            0x1000
#define D18F2x1B4_StrideAlloWm1_OFFSET                          13
#define D18F2x1B4_StrideAlloWm1_WIDTH                           1
#define D18F2x1B4_StrideAlloWm1_MASK                            0x2000
#define D18F2x1B4_RegionPropWm1_OFFSET                          14
#define D18F2x1B4_RegionPropWm1_WIDTH                           1
#define D18F2x1B4_RegionPropWm1_MASK                            0x4000
#define D18F2x1B4_RegionAlloWm1_OFFSET                          15
#define D18F2x1B4_RegionAlloWm1_WIDTH                           1
#define D18F2x1B4_RegionAlloWm1_MASK                            0x8000
#define D18F2x1B4_DemandPropWm2_OFFSET                          16
#define D18F2x1B4_DemandPropWm2_WIDTH                           1
#define D18F2x1B4_DemandPropWm2_MASK                            0x10000
#define D18F2x1B4_DemandAlloWm2_OFFSET                          17
#define D18F2x1B4_DemandAlloWm2_WIDTH                           1
#define D18F2x1B4_DemandAlloWm2_MASK                            0x20000
#define D18F2x1B4_StridePropWm2_OFFSET                          18
#define D18F2x1B4_StridePropWm2_WIDTH                           1
#define D18F2x1B4_StridePropWm2_MASK                            0x40000
#define D18F2x1B4_StrideAlloWm2_OFFSET                          19
#define D18F2x1B4_StrideAlloWm2_WIDTH                           1
#define D18F2x1B4_StrideAlloWm2_MASK                            0x80000
#define D18F2x1B4_RegionPropWm2_OFFSET                          20
#define D18F2x1B4_RegionPropWm2_WIDTH                           1
#define D18F2x1B4_RegionPropWm2_MASK                            0x100000
#define D18F2x1B4_RegionAlloWm2_OFFSET                          21
#define D18F2x1B4_RegionAlloWm2_WIDTH                           1
#define D18F2x1B4_RegionAlloWm2_MASK                            0x200000
#define D18F2x1B4_SpecPrefDisWm1_OFFSET                         22
#define D18F2x1B4_SpecPrefDisWm1_WIDTH                          1
#define D18F2x1B4_SpecPrefDisWm1_MASK                           0x400000
#define D18F2x1B4_Reserved_25_23_OFFSET                         23
#define D18F2x1B4_Reserved_25_23_WIDTH                          3
#define D18F2x1B4_Reserved_25_23_MASK                           0x3800000
#define D18F2x1B4_EnSplitMctDatBuffers_OFFSET                   26
#define D18F2x1B4_EnSplitMctDatBuffers_WIDTH                    1
#define D18F2x1B4_EnSplitMctDatBuffers_MASK                     0x4000000
#define D18F2x1B4_FlushWrOnS3StpGnt_OFFSET                      27
#define D18F2x1B4_FlushWrOnS3StpGnt_WIDTH                       1
#define D18F2x1B4_FlushWrOnS3StpGnt_MASK                        0x8000000
#define D18F2x1B4_S3SmafId_OFFSET                               28
#define D18F2x1B4_S3SmafId_WIDTH                                3
#define D18F2x1B4_S3SmafId_MASK                                 0x70000000
#define D18F2x1B4_FlushOnMmioWrEn_OFFSET                        31
#define D18F2x1B4_FlushOnMmioWrEn_WIDTH                         1
#define D18F2x1B4_FlushOnMmioWrEn_MASK                          0x80000000

/// D18F2x1B4
typedef union {
  struct {                                                              ///<
    UINT32                                            DcqBwThrotWm1:5 ; ///<
    UINT32                                            DcqBwThrotWm2:5 ; ///<
    UINT32                                            DemandPropWm1:1 ; ///<
    UINT32                                            DemandAlloWm1:1 ; ///<
    UINT32                                            StridePropWm1:1 ; ///<
    UINT32                                            StrideAlloWm1:1 ; ///<
    UINT32                                            RegionPropWm1:1 ; ///<
    UINT32                                            RegionAlloWm1:1 ; ///<
    UINT32                                            DemandPropWm2:1 ; ///<
    UINT32                                            DemandAlloWm2:1 ; ///<
    UINT32                                            StridePropWm2:1 ; ///<
    UINT32                                            StrideAlloWm2:1 ; ///<
    UINT32                                            RegionPropWm2:1 ; ///<
    UINT32                                            RegionAlloWm2:1 ; ///<
    UINT32                                           SpecPrefDisWm1:1 ; ///<
    UINT32                                           Reserved_25_23:3 ; ///<
    UINT32                                     EnSplitMctDatBuffers:1 ; ///<
    UINT32                                        FlushWrOnS3StpGnt:1 ; ///<
    UINT32                                                 S3SmafId:3 ; ///<
    UINT32                                          FlushOnMmioWrEn:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x1B4_STRUCT;

// **** D18F2x200_dct0_mp1 Register Definition ****
// Address
#define D18F2x200_dct0_mp1_ADDRESS                              0x200

// Type
#define D18F2x200_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
// Field Data
#define D18F2x200_dct0_mp1_Tcl_OFFSET                           0
#define D18F2x200_dct0_mp1_Tcl_WIDTH                            5
#define D18F2x200_dct0_mp1_Tcl_MASK                             0x1f
#define D18F2x200_dct0_mp1_Reserved_7_5_OFFSET                  5
#define D18F2x200_dct0_mp1_Reserved_7_5_WIDTH                   3
#define D18F2x200_dct0_mp1_Reserved_7_5_MASK                    0xe0
#define D18F2x200_dct0_mp1_Trcd_OFFSET                          8
#define D18F2x200_dct0_mp1_Trcd_WIDTH                           5
#define D18F2x200_dct0_mp1_Trcd_MASK                            0x1f00
#define D18F2x200_dct0_mp1_Reserved_15_13_OFFSET                13
#define D18F2x200_dct0_mp1_Reserved_15_13_WIDTH                 3
#define D18F2x200_dct0_mp1_Reserved_15_13_MASK                  0xe000
#define D18F2x200_dct0_mp1_Trp_OFFSET                           16
#define D18F2x200_dct0_mp1_Trp_WIDTH                            5
#define D18F2x200_dct0_mp1_Trp_MASK                             0x1f0000
#define D18F2x200_dct0_mp1_Reserved_23_21_OFFSET                21
#define D18F2x200_dct0_mp1_Reserved_23_21_WIDTH                 3
#define D18F2x200_dct0_mp1_Reserved_23_21_MASK                  0xe00000
#define D18F2x200_dct0_mp1_Tras_OFFSET                          24
#define D18F2x200_dct0_mp1_Tras_WIDTH                           6
#define D18F2x200_dct0_mp1_Tras_MASK                            0x3f000000
#define D18F2x200_dct0_mp1_Reserved_31_30_OFFSET                30
#define D18F2x200_dct0_mp1_Reserved_31_30_WIDTH                 2
#define D18F2x200_dct0_mp1_Reserved_31_30_MASK                  0xc0000000

/// D18F2x200_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                      Tcl:5 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                                     Trcd:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                                      Trp:5 ; ///<
    UINT32                                           Reserved_23_21:3 ; ///<
    UINT32                                                     Tras:6 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x200_dct0_mp1_STRUCT;

// **** D18F2x200_dct0_mp0 Register Definition ****
// Address
#define D18F2x200_dct0_mp0_ADDRESS                              0x200

// Type
#define D18F2x200_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
// Field Data
#define D18F2x200_dct0_mp0_Tcl_OFFSET                           0
#define D18F2x200_dct0_mp0_Tcl_WIDTH                            5
#define D18F2x200_dct0_mp0_Tcl_MASK                             0x1f
#define D18F2x200_dct0_mp0_Reserved_7_5_OFFSET                  5
#define D18F2x200_dct0_mp0_Reserved_7_5_WIDTH                   3
#define D18F2x200_dct0_mp0_Reserved_7_5_MASK                    0xe0
#define D18F2x200_dct0_mp0_Trcd_OFFSET                          8
#define D18F2x200_dct0_mp0_Trcd_WIDTH                           5
#define D18F2x200_dct0_mp0_Trcd_MASK                            0x1f00
#define D18F2x200_dct0_mp0_Reserved_15_13_OFFSET                13
#define D18F2x200_dct0_mp0_Reserved_15_13_WIDTH                 3
#define D18F2x200_dct0_mp0_Reserved_15_13_MASK                  0xe000
#define D18F2x200_dct0_mp0_Trp_OFFSET                           16
#define D18F2x200_dct0_mp0_Trp_WIDTH                            5
#define D18F2x200_dct0_mp0_Trp_MASK                             0x1f0000
#define D18F2x200_dct0_mp0_Reserved_23_21_OFFSET                21
#define D18F2x200_dct0_mp0_Reserved_23_21_WIDTH                 3
#define D18F2x200_dct0_mp0_Reserved_23_21_MASK                  0xe00000
#define D18F2x200_dct0_mp0_Tras_OFFSET                          24
#define D18F2x200_dct0_mp0_Tras_WIDTH                           6
#define D18F2x200_dct0_mp0_Tras_MASK                            0x3f000000
#define D18F2x200_dct0_mp0_Reserved_31_30_OFFSET                30
#define D18F2x200_dct0_mp0_Reserved_31_30_WIDTH                 2
#define D18F2x200_dct0_mp0_Reserved_31_30_MASK                  0xc0000000

/// D18F2x200_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                      Tcl:5 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                                     Trcd:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                                      Trp:5 ; ///<
    UINT32                                           Reserved_23_21:3 ; ///<
    UINT32                                                     Tras:6 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x200_dct0_mp0_STRUCT;

// **** D18F2x200_dct1_mp1 Register Definition ****
// Address
#define D18F2x200_dct1_mp1_ADDRESS                              0x200

// Type
#define D18F2x200_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
// Field Data
#define D18F2x200_dct1_mp1_Tcl_OFFSET                           0
#define D18F2x200_dct1_mp1_Tcl_WIDTH                            5
#define D18F2x200_dct1_mp1_Tcl_MASK                             0x1f
#define D18F2x200_dct1_mp1_Reserved_7_5_OFFSET                  5
#define D18F2x200_dct1_mp1_Reserved_7_5_WIDTH                   3
#define D18F2x200_dct1_mp1_Reserved_7_5_MASK                    0xe0
#define D18F2x200_dct1_mp1_Trcd_OFFSET                          8
#define D18F2x200_dct1_mp1_Trcd_WIDTH                           5
#define D18F2x200_dct1_mp1_Trcd_MASK                            0x1f00
#define D18F2x200_dct1_mp1_Reserved_15_13_OFFSET                13
#define D18F2x200_dct1_mp1_Reserved_15_13_WIDTH                 3
#define D18F2x200_dct1_mp1_Reserved_15_13_MASK                  0xe000
#define D18F2x200_dct1_mp1_Trp_OFFSET                           16
#define D18F2x200_dct1_mp1_Trp_WIDTH                            5
#define D18F2x200_dct1_mp1_Trp_MASK                             0x1f0000
#define D18F2x200_dct1_mp1_Reserved_23_21_OFFSET                21
#define D18F2x200_dct1_mp1_Reserved_23_21_WIDTH                 3
#define D18F2x200_dct1_mp1_Reserved_23_21_MASK                  0xe00000
#define D18F2x200_dct1_mp1_Tras_OFFSET                          24
#define D18F2x200_dct1_mp1_Tras_WIDTH                           6
#define D18F2x200_dct1_mp1_Tras_MASK                            0x3f000000
#define D18F2x200_dct1_mp1_Reserved_31_30_OFFSET                30
#define D18F2x200_dct1_mp1_Reserved_31_30_WIDTH                 2
#define D18F2x200_dct1_mp1_Reserved_31_30_MASK                  0xc0000000

/// D18F2x200_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                      Tcl:5 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                                     Trcd:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                                      Trp:5 ; ///<
    UINT32                                           Reserved_23_21:3 ; ///<
    UINT32                                                     Tras:6 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x200_dct1_mp1_STRUCT;

// **** D18F2x200_dct1_mp0 Register Definition ****
// Address
#define D18F2x200_dct1_mp0_ADDRESS                              0x200

// Type
#define D18F2x200_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
// Field Data
#define D18F2x200_dct1_mp0_Tcl_OFFSET                           0
#define D18F2x200_dct1_mp0_Tcl_WIDTH                            5
#define D18F2x200_dct1_mp0_Tcl_MASK                             0x1f
#define D18F2x200_dct1_mp0_Reserved_7_5_OFFSET                  5
#define D18F2x200_dct1_mp0_Reserved_7_5_WIDTH                   3
#define D18F2x200_dct1_mp0_Reserved_7_5_MASK                    0xe0
#define D18F2x200_dct1_mp0_Trcd_OFFSET                          8
#define D18F2x200_dct1_mp0_Trcd_WIDTH                           5
#define D18F2x200_dct1_mp0_Trcd_MASK                            0x1f00
#define D18F2x200_dct1_mp0_Reserved_15_13_OFFSET                13
#define D18F2x200_dct1_mp0_Reserved_15_13_WIDTH                 3
#define D18F2x200_dct1_mp0_Reserved_15_13_MASK                  0xe000
#define D18F2x200_dct1_mp0_Trp_OFFSET                           16
#define D18F2x200_dct1_mp0_Trp_WIDTH                            5
#define D18F2x200_dct1_mp0_Trp_MASK                             0x1f0000
#define D18F2x200_dct1_mp0_Reserved_23_21_OFFSET                21
#define D18F2x200_dct1_mp0_Reserved_23_21_WIDTH                 3
#define D18F2x200_dct1_mp0_Reserved_23_21_MASK                  0xe00000
#define D18F2x200_dct1_mp0_Tras_OFFSET                          24
#define D18F2x200_dct1_mp0_Tras_WIDTH                           6
#define D18F2x200_dct1_mp0_Tras_MASK                            0x3f000000
#define D18F2x200_dct1_mp0_Reserved_31_30_OFFSET                30
#define D18F2x200_dct1_mp0_Reserved_31_30_WIDTH                 2
#define D18F2x200_dct1_mp0_Reserved_31_30_MASK                  0xc0000000

/// D18F2x200_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                      Tcl:5 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                                     Trcd:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                                      Trp:5 ; ///<
    UINT32                                           Reserved_23_21:3 ; ///<
    UINT32                                                     Tras:6 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x200_dct1_mp0_STRUCT;

// **** D18F2x204_dct0_mp0 Register Definition ****
// Address
#define D18F2x204_dct0_mp0_ADDRESS                              0x204

// Type
#define D18F2x204_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
// Field Data
#define D18F2x204_dct0_mp0_Trc_OFFSET                           0
#define D18F2x204_dct0_mp0_Trc_WIDTH                            6
#define D18F2x204_dct0_mp0_Trc_MASK                             0x3f
#define D18F2x204_dct0_mp0_Reserved_7_6_OFFSET                  6
#define D18F2x204_dct0_mp0_Reserved_7_6_WIDTH                   2
#define D18F2x204_dct0_mp0_Reserved_7_6_MASK                    0xc0
#define D18F2x204_dct0_mp0_Trrd_OFFSET                          8
#define D18F2x204_dct0_mp0_Trrd_WIDTH                           4
#define D18F2x204_dct0_mp0_Trrd_MASK                            0xf00
#define D18F2x204_dct0_mp0_Reserved_15_12_OFFSET                12
#define D18F2x204_dct0_mp0_Reserved_15_12_WIDTH                 4
#define D18F2x204_dct0_mp0_Reserved_15_12_MASK                  0xf000
#define D18F2x204_dct0_mp0_FourActWindow_OFFSET                 16
#define D18F2x204_dct0_mp0_FourActWindow_WIDTH                  6
#define D18F2x204_dct0_mp0_FourActWindow_MASK                   0x3f0000
#define D18F2x204_dct0_mp0_Reserved_23_22_OFFSET                22
#define D18F2x204_dct0_mp0_Reserved_23_22_WIDTH                 2
#define D18F2x204_dct0_mp0_Reserved_23_22_MASK                  0xc00000
#define D18F2x204_dct0_mp0_Trtp_OFFSET                          24
#define D18F2x204_dct0_mp0_Trtp_WIDTH                           4
#define D18F2x204_dct0_mp0_Trtp_MASK                            0xf000000
#define D18F2x204_dct0_mp0_Reserved_31_28_OFFSET                28
#define D18F2x204_dct0_mp0_Reserved_31_28_WIDTH                 4
#define D18F2x204_dct0_mp0_Reserved_31_28_MASK                  0xf0000000

/// D18F2x204_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                      Trc:6 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                                     Trrd:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                            FourActWindow:6 ; ///<
    UINT32                                           Reserved_23_22:2 ; ///<
    UINT32                                                     Trtp:4 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x204_dct0_mp0_STRUCT;

// **** D18F2x204_dct1_mp0 Register Definition ****
// Address
#define D18F2x204_dct1_mp0_ADDRESS                              0x204

// Type
#define D18F2x204_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
// Field Data
#define D18F2x204_dct1_mp0_Trc_OFFSET                           0
#define D18F2x204_dct1_mp0_Trc_WIDTH                            6
#define D18F2x204_dct1_mp0_Trc_MASK                             0x3f
#define D18F2x204_dct1_mp0_Reserved_7_6_OFFSET                  6
#define D18F2x204_dct1_mp0_Reserved_7_6_WIDTH                   2
#define D18F2x204_dct1_mp0_Reserved_7_6_MASK                    0xc0
#define D18F2x204_dct1_mp0_Trrd_OFFSET                          8
#define D18F2x204_dct1_mp0_Trrd_WIDTH                           4
#define D18F2x204_dct1_mp0_Trrd_MASK                            0xf00
#define D18F2x204_dct1_mp0_Reserved_15_12_OFFSET                12
#define D18F2x204_dct1_mp0_Reserved_15_12_WIDTH                 4
#define D18F2x204_dct1_mp0_Reserved_15_12_MASK                  0xf000
#define D18F2x204_dct1_mp0_FourActWindow_OFFSET                 16
#define D18F2x204_dct1_mp0_FourActWindow_WIDTH                  6
#define D18F2x204_dct1_mp0_FourActWindow_MASK                   0x3f0000
#define D18F2x204_dct1_mp0_Reserved_23_22_OFFSET                22
#define D18F2x204_dct1_mp0_Reserved_23_22_WIDTH                 2
#define D18F2x204_dct1_mp0_Reserved_23_22_MASK                  0xc00000
#define D18F2x204_dct1_mp0_Trtp_OFFSET                          24
#define D18F2x204_dct1_mp0_Trtp_WIDTH                           4
#define D18F2x204_dct1_mp0_Trtp_MASK                            0xf000000
#define D18F2x204_dct1_mp0_Reserved_31_28_OFFSET                28
#define D18F2x204_dct1_mp0_Reserved_31_28_WIDTH                 4
#define D18F2x204_dct1_mp0_Reserved_31_28_MASK                  0xf0000000

/// D18F2x204_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                      Trc:6 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                                     Trrd:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                            FourActWindow:6 ; ///<
    UINT32                                           Reserved_23_22:2 ; ///<
    UINT32                                                     Trtp:4 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x204_dct1_mp0_STRUCT;

// **** D18F2x204_dct0_mp1 Register Definition ****
// Address
#define D18F2x204_dct0_mp1_ADDRESS                              0x204

// Type
#define D18F2x204_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
// Field Data
#define D18F2x204_dct0_mp1_Trc_OFFSET                           0
#define D18F2x204_dct0_mp1_Trc_WIDTH                            6
#define D18F2x204_dct0_mp1_Trc_MASK                             0x3f
#define D18F2x204_dct0_mp1_Reserved_7_6_OFFSET                  6
#define D18F2x204_dct0_mp1_Reserved_7_6_WIDTH                   2
#define D18F2x204_dct0_mp1_Reserved_7_6_MASK                    0xc0
#define D18F2x204_dct0_mp1_Trrd_OFFSET                          8
#define D18F2x204_dct0_mp1_Trrd_WIDTH                           4
#define D18F2x204_dct0_mp1_Trrd_MASK                            0xf00
#define D18F2x204_dct0_mp1_Reserved_15_12_OFFSET                12
#define D18F2x204_dct0_mp1_Reserved_15_12_WIDTH                 4
#define D18F2x204_dct0_mp1_Reserved_15_12_MASK                  0xf000
#define D18F2x204_dct0_mp1_FourActWindow_OFFSET                 16
#define D18F2x204_dct0_mp1_FourActWindow_WIDTH                  6
#define D18F2x204_dct0_mp1_FourActWindow_MASK                   0x3f0000
#define D18F2x204_dct0_mp1_Reserved_23_22_OFFSET                22
#define D18F2x204_dct0_mp1_Reserved_23_22_WIDTH                 2
#define D18F2x204_dct0_mp1_Reserved_23_22_MASK                  0xc00000
#define D18F2x204_dct0_mp1_Trtp_OFFSET                          24
#define D18F2x204_dct0_mp1_Trtp_WIDTH                           4
#define D18F2x204_dct0_mp1_Trtp_MASK                            0xf000000
#define D18F2x204_dct0_mp1_Reserved_31_28_OFFSET                28
#define D18F2x204_dct0_mp1_Reserved_31_28_WIDTH                 4
#define D18F2x204_dct0_mp1_Reserved_31_28_MASK                  0xf0000000

/// D18F2x204_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                      Trc:6 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                                     Trrd:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                            FourActWindow:6 ; ///<
    UINT32                                           Reserved_23_22:2 ; ///<
    UINT32                                                     Trtp:4 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x204_dct0_mp1_STRUCT;

// **** D18F2x204_dct1_mp1 Register Definition ****
// Address
#define D18F2x204_dct1_mp1_ADDRESS                              0x204

// Type
#define D18F2x204_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
// Field Data
#define D18F2x204_dct1_mp1_Trc_OFFSET                           0
#define D18F2x204_dct1_mp1_Trc_WIDTH                            6
#define D18F2x204_dct1_mp1_Trc_MASK                             0x3f
#define D18F2x204_dct1_mp1_Reserved_7_6_OFFSET                  6
#define D18F2x204_dct1_mp1_Reserved_7_6_WIDTH                   2
#define D18F2x204_dct1_mp1_Reserved_7_6_MASK                    0xc0
#define D18F2x204_dct1_mp1_Trrd_OFFSET                          8
#define D18F2x204_dct1_mp1_Trrd_WIDTH                           4
#define D18F2x204_dct1_mp1_Trrd_MASK                            0xf00
#define D18F2x204_dct1_mp1_Reserved_15_12_OFFSET                12
#define D18F2x204_dct1_mp1_Reserved_15_12_WIDTH                 4
#define D18F2x204_dct1_mp1_Reserved_15_12_MASK                  0xf000
#define D18F2x204_dct1_mp1_FourActWindow_OFFSET                 16
#define D18F2x204_dct1_mp1_FourActWindow_WIDTH                  6
#define D18F2x204_dct1_mp1_FourActWindow_MASK                   0x3f0000
#define D18F2x204_dct1_mp1_Reserved_23_22_OFFSET                22
#define D18F2x204_dct1_mp1_Reserved_23_22_WIDTH                 2
#define D18F2x204_dct1_mp1_Reserved_23_22_MASK                  0xc00000
#define D18F2x204_dct1_mp1_Trtp_OFFSET                          24
#define D18F2x204_dct1_mp1_Trtp_WIDTH                           4
#define D18F2x204_dct1_mp1_Trtp_MASK                            0xf000000
#define D18F2x204_dct1_mp1_Reserved_31_28_OFFSET                28
#define D18F2x204_dct1_mp1_Reserved_31_28_WIDTH                 4
#define D18F2x204_dct1_mp1_Reserved_31_28_MASK                  0xf0000000

/// D18F2x204_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                      Trc:6 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                                     Trrd:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                            FourActWindow:6 ; ///<
    UINT32                                           Reserved_23_22:2 ; ///<
    UINT32                                                     Trtp:4 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x204_dct1_mp1_STRUCT;

// **** D18F2x208_dct0 Register Definition ****
// Address
#define D18F2x208_dct0_ADDRESS                                  0x208

// Type
#define D18F2x208_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x208_dct0_Trfc0_OFFSET                             0
#define D18F2x208_dct0_Trfc0_WIDTH                              3
#define D18F2x208_dct0_Trfc0_MASK                               0x7
#define D18F2x208_dct0_Reserved_7_3_OFFSET                      3
#define D18F2x208_dct0_Reserved_7_3_WIDTH                       5
#define D18F2x208_dct0_Reserved_7_3_MASK                        0xf8
#define D18F2x208_dct0_Trfc1_OFFSET                             8
#define D18F2x208_dct0_Trfc1_WIDTH                              3
#define D18F2x208_dct0_Trfc1_MASK                               0x700
#define D18F2x208_dct0_Reserved_15_11_OFFSET                    11
#define D18F2x208_dct0_Reserved_15_11_WIDTH                     5
#define D18F2x208_dct0_Reserved_15_11_MASK                      0xf800
#define D18F2x208_dct0_Trfc2_OFFSET                             16
#define D18F2x208_dct0_Trfc2_WIDTH                              3
#define D18F2x208_dct0_Trfc2_MASK                               0x70000
#define D18F2x208_dct0_Reserved_23_19_OFFSET                    19
#define D18F2x208_dct0_Reserved_23_19_WIDTH                     5
#define D18F2x208_dct0_Reserved_23_19_MASK                      0xf80000
#define D18F2x208_dct0_Trfc3_OFFSET                             24
#define D18F2x208_dct0_Trfc3_WIDTH                              3
#define D18F2x208_dct0_Trfc3_MASK                               0x7000000
#define D18F2x208_dct0_Reserved_31_27_OFFSET                    27
#define D18F2x208_dct0_Reserved_31_27_WIDTH                     5
#define D18F2x208_dct0_Reserved_31_27_MASK                      0xf8000000

/// D18F2x208_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                    Trfc0:3 ; ///<
    UINT32                                             Reserved_7_3:5 ; ///<
    UINT32                                                    Trfc1:3 ; ///<
    UINT32                                           Reserved_15_11:5 ; ///<
    UINT32                                                    Trfc2:3 ; ///<
    UINT32                                           Reserved_23_19:5 ; ///<
    UINT32                                                    Trfc3:3 ; ///<
    UINT32                                           Reserved_31_27:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x208_dct0_STRUCT;

// **** D18F2x208_dct1 Register Definition ****
// Address
#define D18F2x208_dct1_ADDRESS                                  0x208

// Type
#define D18F2x208_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x208_dct1_Trfc0_OFFSET                             0
#define D18F2x208_dct1_Trfc0_WIDTH                              3
#define D18F2x208_dct1_Trfc0_MASK                               0x7
#define D18F2x208_dct1_Reserved_7_3_OFFSET                      3
#define D18F2x208_dct1_Reserved_7_3_WIDTH                       5
#define D18F2x208_dct1_Reserved_7_3_MASK                        0xf8
#define D18F2x208_dct1_Trfc1_OFFSET                             8
#define D18F2x208_dct1_Trfc1_WIDTH                              3
#define D18F2x208_dct1_Trfc1_MASK                               0x700
#define D18F2x208_dct1_Reserved_15_11_OFFSET                    11
#define D18F2x208_dct1_Reserved_15_11_WIDTH                     5
#define D18F2x208_dct1_Reserved_15_11_MASK                      0xf800
#define D18F2x208_dct1_Trfc2_OFFSET                             16
#define D18F2x208_dct1_Trfc2_WIDTH                              3
#define D18F2x208_dct1_Trfc2_MASK                               0x70000
#define D18F2x208_dct1_Reserved_23_19_OFFSET                    19
#define D18F2x208_dct1_Reserved_23_19_WIDTH                     5
#define D18F2x208_dct1_Reserved_23_19_MASK                      0xf80000
#define D18F2x208_dct1_Trfc3_OFFSET                             24
#define D18F2x208_dct1_Trfc3_WIDTH                              3
#define D18F2x208_dct1_Trfc3_MASK                               0x7000000
#define D18F2x208_dct1_Reserved_31_27_OFFSET                    27
#define D18F2x208_dct1_Reserved_31_27_WIDTH                     5
#define D18F2x208_dct1_Reserved_31_27_MASK                      0xf8000000

/// D18F2x208_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                    Trfc0:3 ; ///<
    UINT32                                             Reserved_7_3:5 ; ///<
    UINT32                                                    Trfc1:3 ; ///<
    UINT32                                           Reserved_15_11:5 ; ///<
    UINT32                                                    Trfc2:3 ; ///<
    UINT32                                           Reserved_23_19:5 ; ///<
    UINT32                                                    Trfc3:3 ; ///<
    UINT32                                           Reserved_31_27:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x208_dct1_STRUCT;

// **** D18F2x20C_dct0_mp1 Register Definition ****
// Address
#define D18F2x20C_dct0_mp1_ADDRESS                              0x20c

// Type
#define D18F2x20C_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
// Field Data
#define D18F2x20C_dct0_mp1_Tcwl_OFFSET                          0
#define D18F2x20C_dct0_mp1_Tcwl_WIDTH                           5
#define D18F2x20C_dct0_mp1_Tcwl_MASK                            0x1f
#define D18F2x20C_dct0_mp1_Reserved_7_5_OFFSET                  5
#define D18F2x20C_dct0_mp1_Reserved_7_5_WIDTH                   3
#define D18F2x20C_dct0_mp1_Reserved_7_5_MASK                    0xe0
#define D18F2x20C_dct0_mp1_Twtr_OFFSET                          8
#define D18F2x20C_dct0_mp1_Twtr_WIDTH                           4
#define D18F2x20C_dct0_mp1_Twtr_MASK                            0xf00
#define D18F2x20C_dct0_mp1_Reserved_15_12_OFFSET                12
#define D18F2x20C_dct0_mp1_Reserved_15_12_WIDTH                 4
#define D18F2x20C_dct0_mp1_Reserved_15_12_MASK                  0xf000
#define D18F2x20C_dct0_mp1_WrDqDqsEarly_OFFSET                  16
#define D18F2x20C_dct0_mp1_WrDqDqsEarly_WIDTH                   2
#define D18F2x20C_dct0_mp1_WrDqDqsEarly_MASK                    0x30000
#define D18F2x20C_dct0_mp1_Reserved_31_18_OFFSET                18
#define D18F2x20C_dct0_mp1_Reserved_31_18_WIDTH                 14
#define D18F2x20C_dct0_mp1_Reserved_31_18_MASK                  0xfffc0000

/// D18F2x20C_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                     Tcwl:5 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                                     Twtr:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                             WrDqDqsEarly:2 ; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x20C_dct0_mp1_STRUCT;

// **** D18F2x20C_dct1_mp1 Register Definition ****
// Address
#define D18F2x20C_dct1_mp1_ADDRESS                              0x20c

// Type
#define D18F2x20C_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
// Field Data
#define D18F2x20C_dct1_mp1_Tcwl_OFFSET                          0
#define D18F2x20C_dct1_mp1_Tcwl_WIDTH                           5
#define D18F2x20C_dct1_mp1_Tcwl_MASK                            0x1f
#define D18F2x20C_dct1_mp1_Reserved_7_5_OFFSET                  5
#define D18F2x20C_dct1_mp1_Reserved_7_5_WIDTH                   3
#define D18F2x20C_dct1_mp1_Reserved_7_5_MASK                    0xe0
#define D18F2x20C_dct1_mp1_Twtr_OFFSET                          8
#define D18F2x20C_dct1_mp1_Twtr_WIDTH                           4
#define D18F2x20C_dct1_mp1_Twtr_MASK                            0xf00
#define D18F2x20C_dct1_mp1_Reserved_15_12_OFFSET                12
#define D18F2x20C_dct1_mp1_Reserved_15_12_WIDTH                 4
#define D18F2x20C_dct1_mp1_Reserved_15_12_MASK                  0xf000
#define D18F2x20C_dct1_mp1_WrDqDqsEarly_OFFSET                  16
#define D18F2x20C_dct1_mp1_WrDqDqsEarly_WIDTH                   2
#define D18F2x20C_dct1_mp1_WrDqDqsEarly_MASK                    0x30000
#define D18F2x20C_dct1_mp1_Reserved_31_18_OFFSET                18
#define D18F2x20C_dct1_mp1_Reserved_31_18_WIDTH                 14
#define D18F2x20C_dct1_mp1_Reserved_31_18_MASK                  0xfffc0000

/// D18F2x20C_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                     Tcwl:5 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                                     Twtr:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                             WrDqDqsEarly:2 ; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x20C_dct1_mp1_STRUCT;

// **** D18F2x20C_dct1_mp0 Register Definition ****
// Address
#define D18F2x20C_dct1_mp0_ADDRESS                              0x20c

// Type
#define D18F2x20C_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
// Field Data
#define D18F2x20C_dct1_mp0_Tcwl_OFFSET                          0
#define D18F2x20C_dct1_mp0_Tcwl_WIDTH                           5
#define D18F2x20C_dct1_mp0_Tcwl_MASK                            0x1f
#define D18F2x20C_dct1_mp0_Reserved_7_5_OFFSET                  5
#define D18F2x20C_dct1_mp0_Reserved_7_5_WIDTH                   3
#define D18F2x20C_dct1_mp0_Reserved_7_5_MASK                    0xe0
#define D18F2x20C_dct1_mp0_Twtr_OFFSET                          8
#define D18F2x20C_dct1_mp0_Twtr_WIDTH                           4
#define D18F2x20C_dct1_mp0_Twtr_MASK                            0xf00
#define D18F2x20C_dct1_mp0_Reserved_15_12_OFFSET                12
#define D18F2x20C_dct1_mp0_Reserved_15_12_WIDTH                 4
#define D18F2x20C_dct1_mp0_Reserved_15_12_MASK                  0xf000
#define D18F2x20C_dct1_mp0_WrDqDqsEarly_OFFSET                  16
#define D18F2x20C_dct1_mp0_WrDqDqsEarly_WIDTH                   2
#define D18F2x20C_dct1_mp0_WrDqDqsEarly_MASK                    0x30000
#define D18F2x20C_dct1_mp0_Reserved_31_18_OFFSET                18
#define D18F2x20C_dct1_mp0_Reserved_31_18_WIDTH                 14
#define D18F2x20C_dct1_mp0_Reserved_31_18_MASK                  0xfffc0000

/// D18F2x20C_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                     Tcwl:5 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                                     Twtr:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                             WrDqDqsEarly:2 ; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x20C_dct1_mp0_STRUCT;

// **** D18F2x20C_dct0_mp0 Register Definition ****
// Address
#define D18F2x20C_dct0_mp0_ADDRESS                              0x20c

// Type
#define D18F2x20C_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
// Field Data
#define D18F2x20C_dct0_mp0_Tcwl_OFFSET                          0
#define D18F2x20C_dct0_mp0_Tcwl_WIDTH                           5
#define D18F2x20C_dct0_mp0_Tcwl_MASK                            0x1f
#define D18F2x20C_dct0_mp0_Reserved_7_5_OFFSET                  5
#define D18F2x20C_dct0_mp0_Reserved_7_5_WIDTH                   3
#define D18F2x20C_dct0_mp0_Reserved_7_5_MASK                    0xe0
#define D18F2x20C_dct0_mp0_Twtr_OFFSET                          8
#define D18F2x20C_dct0_mp0_Twtr_WIDTH                           4
#define D18F2x20C_dct0_mp0_Twtr_MASK                            0xf00
#define D18F2x20C_dct0_mp0_Reserved_15_12_OFFSET                12
#define D18F2x20C_dct0_mp0_Reserved_15_12_WIDTH                 4
#define D18F2x20C_dct0_mp0_Reserved_15_12_MASK                  0xf000
#define D18F2x20C_dct0_mp0_WrDqDqsEarly_OFFSET                  16
#define D18F2x20C_dct0_mp0_WrDqDqsEarly_WIDTH                   2
#define D18F2x20C_dct0_mp0_WrDqDqsEarly_MASK                    0x30000
#define D18F2x20C_dct0_mp0_Reserved_31_18_OFFSET                18
#define D18F2x20C_dct0_mp0_Reserved_31_18_WIDTH                 14
#define D18F2x20C_dct0_mp0_Reserved_31_18_MASK                  0xfffc0000

/// D18F2x20C_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                     Tcwl:5 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                                     Twtr:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                             WrDqDqsEarly:2 ; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x20C_dct0_mp0_STRUCT;

// **** D18F2x210_dct1_nbp0 Register Definition ****
// Address
#define D18F2x210_dct1_nbp0_ADDRESS                             0x210

// Type
#define D18F2x210_dct1_nbp0_TYPE                                TYPE_D18F2_dct1
// Field Data
#define D18F2x210_dct1_nbp0_RdPtrInit_OFFSET                    0
#define D18F2x210_dct1_nbp0_RdPtrInit_WIDTH                     4
#define D18F2x210_dct1_nbp0_RdPtrInit_MASK                      0xf
#define D18F2x210_dct1_nbp0_Reserved_15_4_OFFSET                4
#define D18F2x210_dct1_nbp0_Reserved_15_4_WIDTH                 12
#define D18F2x210_dct1_nbp0_Reserved_15_4_MASK                  0xfff0
#define D18F2x210_dct1_nbp0_DataTxFifoWrDly_OFFSET              16
#define D18F2x210_dct1_nbp0_DataTxFifoWrDly_WIDTH               3
#define D18F2x210_dct1_nbp0_DataTxFifoWrDly_MASK                0x70000
#define D18F2x210_dct1_nbp0_Reserved_21_19_OFFSET               19
#define D18F2x210_dct1_nbp0_Reserved_21_19_WIDTH                3
#define D18F2x210_dct1_nbp0_Reserved_21_19_MASK                 0x380000
#define D18F2x210_dct1_nbp0_MaxRdLatency_OFFSET                 22
#define D18F2x210_dct1_nbp0_MaxRdLatency_WIDTH                  10
#define D18F2x210_dct1_nbp0_MaxRdLatency_MASK                   0xffc00000

/// D18F2x210_dct1_nbp0
typedef union {
  struct {                                                              ///<
    UINT32                                                RdPtrInit:4 ; ///<
    UINT32                                            Reserved_15_4:12; ///<
    UINT32                                          DataTxFifoWrDly:3 ; ///<
    UINT32                                           Reserved_21_19:3 ; ///<
    UINT32                                             MaxRdLatency:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x210_dct1_nbp0_STRUCT;

// **** D18F2x210_dct0_nbp2 Register Definition ****
// Address
#define D18F2x210_dct0_nbp2_ADDRESS                             0x210

// Type
#define D18F2x210_dct0_nbp2_TYPE                                TYPE_D18F2_dct0
// Field Data
#define D18F2x210_dct0_nbp2_RdPtrInit_OFFSET                    0
#define D18F2x210_dct0_nbp2_RdPtrInit_WIDTH                     4
#define D18F2x210_dct0_nbp2_RdPtrInit_MASK                      0xf
#define D18F2x210_dct0_nbp2_Reserved_15_4_OFFSET                4
#define D18F2x210_dct0_nbp2_Reserved_15_4_WIDTH                 12
#define D18F2x210_dct0_nbp2_Reserved_15_4_MASK                  0xfff0
#define D18F2x210_dct0_nbp2_DataTxFifoWrDly_OFFSET              16
#define D18F2x210_dct0_nbp2_DataTxFifoWrDly_WIDTH               3
#define D18F2x210_dct0_nbp2_DataTxFifoWrDly_MASK                0x70000
#define D18F2x210_dct0_nbp2_Reserved_21_19_OFFSET               19
#define D18F2x210_dct0_nbp2_Reserved_21_19_WIDTH                3
#define D18F2x210_dct0_nbp2_Reserved_21_19_MASK                 0x380000
#define D18F2x210_dct0_nbp2_MaxRdLatency_OFFSET                 22
#define D18F2x210_dct0_nbp2_MaxRdLatency_WIDTH                  10
#define D18F2x210_dct0_nbp2_MaxRdLatency_MASK                   0xffc00000

/// D18F2x210_dct0_nbp2
typedef union {
  struct {                                                              ///<
    UINT32                                                RdPtrInit:4 ; ///<
    UINT32                                            Reserved_15_4:12; ///<
    UINT32                                          DataTxFifoWrDly:3 ; ///<
    UINT32                                           Reserved_21_19:3 ; ///<
    UINT32                                             MaxRdLatency:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x210_dct0_nbp2_STRUCT;

// **** D18F2x210_dct1_nbp1 Register Definition ****
// Address
#define D18F2x210_dct1_nbp1_ADDRESS                             0x210

// Type
#define D18F2x210_dct1_nbp1_TYPE                                TYPE_D18F2_dct1
// Field Data
#define D18F2x210_dct1_nbp1_RdPtrInit_OFFSET                    0
#define D18F2x210_dct1_nbp1_RdPtrInit_WIDTH                     4
#define D18F2x210_dct1_nbp1_RdPtrInit_MASK                      0xf
#define D18F2x210_dct1_nbp1_Reserved_15_4_OFFSET                4
#define D18F2x210_dct1_nbp1_Reserved_15_4_WIDTH                 12
#define D18F2x210_dct1_nbp1_Reserved_15_4_MASK                  0xfff0
#define D18F2x210_dct1_nbp1_DataTxFifoWrDly_OFFSET              16
#define D18F2x210_dct1_nbp1_DataTxFifoWrDly_WIDTH               3
#define D18F2x210_dct1_nbp1_DataTxFifoWrDly_MASK                0x70000
#define D18F2x210_dct1_nbp1_Reserved_21_19_OFFSET               19
#define D18F2x210_dct1_nbp1_Reserved_21_19_WIDTH                3
#define D18F2x210_dct1_nbp1_Reserved_21_19_MASK                 0x380000
#define D18F2x210_dct1_nbp1_MaxRdLatency_OFFSET                 22
#define D18F2x210_dct1_nbp1_MaxRdLatency_WIDTH                  10
#define D18F2x210_dct1_nbp1_MaxRdLatency_MASK                   0xffc00000

/// D18F2x210_dct1_nbp1
typedef union {
  struct {                                                              ///<
    UINT32                                                RdPtrInit:4 ; ///<
    UINT32                                            Reserved_15_4:12; ///<
    UINT32                                          DataTxFifoWrDly:3 ; ///<
    UINT32                                           Reserved_21_19:3 ; ///<
    UINT32                                             MaxRdLatency:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x210_dct1_nbp1_STRUCT;

// **** D18F2x210_dct1_nbp3 Register Definition ****
// Address
#define D18F2x210_dct1_nbp3_ADDRESS                             0x210

// Type
#define D18F2x210_dct1_nbp3_TYPE                                TYPE_D18F2_dct1
// Field Data
#define D18F2x210_dct1_nbp3_RdPtrInit_OFFSET                    0
#define D18F2x210_dct1_nbp3_RdPtrInit_WIDTH                     4
#define D18F2x210_dct1_nbp3_RdPtrInit_MASK                      0xf
#define D18F2x210_dct1_nbp3_Reserved_15_4_OFFSET                4
#define D18F2x210_dct1_nbp3_Reserved_15_4_WIDTH                 12
#define D18F2x210_dct1_nbp3_Reserved_15_4_MASK                  0xfff0
#define D18F2x210_dct1_nbp3_DataTxFifoWrDly_OFFSET              16
#define D18F2x210_dct1_nbp3_DataTxFifoWrDly_WIDTH               3
#define D18F2x210_dct1_nbp3_DataTxFifoWrDly_MASK                0x70000
#define D18F2x210_dct1_nbp3_Reserved_21_19_OFFSET               19
#define D18F2x210_dct1_nbp3_Reserved_21_19_WIDTH                3
#define D18F2x210_dct1_nbp3_Reserved_21_19_MASK                 0x380000
#define D18F2x210_dct1_nbp3_MaxRdLatency_OFFSET                 22
#define D18F2x210_dct1_nbp3_MaxRdLatency_WIDTH                  10
#define D18F2x210_dct1_nbp3_MaxRdLatency_MASK                   0xffc00000

/// D18F2x210_dct1_nbp3
typedef union {
  struct {                                                              ///<
    UINT32                                                RdPtrInit:4 ; ///<
    UINT32                                            Reserved_15_4:12; ///<
    UINT32                                          DataTxFifoWrDly:3 ; ///<
    UINT32                                           Reserved_21_19:3 ; ///<
    UINT32                                             MaxRdLatency:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x210_dct1_nbp3_STRUCT;

// **** D18F2x210_dct0_nbp0 Register Definition ****
// Address
#define D18F2x210_dct0_nbp0_ADDRESS                             0x210

// Type
#define D18F2x210_dct0_nbp0_TYPE                                TYPE_D18F2_dct0
// Field Data
#define D18F2x210_dct0_nbp0_RdPtrInit_OFFSET                    0
#define D18F2x210_dct0_nbp0_RdPtrInit_WIDTH                     4
#define D18F2x210_dct0_nbp0_RdPtrInit_MASK                      0xf
#define D18F2x210_dct0_nbp0_Reserved_15_4_OFFSET                4
#define D18F2x210_dct0_nbp0_Reserved_15_4_WIDTH                 12
#define D18F2x210_dct0_nbp0_Reserved_15_4_MASK                  0xfff0
#define D18F2x210_dct0_nbp0_DataTxFifoWrDly_OFFSET              16
#define D18F2x210_dct0_nbp0_DataTxFifoWrDly_WIDTH               3
#define D18F2x210_dct0_nbp0_DataTxFifoWrDly_MASK                0x70000
#define D18F2x210_dct0_nbp0_Reserved_21_19_OFFSET               19
#define D18F2x210_dct0_nbp0_Reserved_21_19_WIDTH                3
#define D18F2x210_dct0_nbp0_Reserved_21_19_MASK                 0x380000
#define D18F2x210_dct0_nbp0_MaxRdLatency_OFFSET                 22
#define D18F2x210_dct0_nbp0_MaxRdLatency_WIDTH                  10
#define D18F2x210_dct0_nbp0_MaxRdLatency_MASK                   0xffc00000

/// D18F2x210_dct0_nbp0
typedef union {
  struct {                                                              ///<
    UINT32                                                RdPtrInit:4 ; ///<
    UINT32                                            Reserved_15_4:12; ///<
    UINT32                                          DataTxFifoWrDly:3 ; ///<
    UINT32                                           Reserved_21_19:3 ; ///<
    UINT32                                             MaxRdLatency:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x210_dct0_nbp0_STRUCT;

// **** D18F2x210_dct0_nbp3 Register Definition ****
// Address
#define D18F2x210_dct0_nbp3_ADDRESS                             0x210

// Type
#define D18F2x210_dct0_nbp3_TYPE                                TYPE_D18F2_dct0
// Field Data
#define D18F2x210_dct0_nbp3_RdPtrInit_OFFSET                    0
#define D18F2x210_dct0_nbp3_RdPtrInit_WIDTH                     4
#define D18F2x210_dct0_nbp3_RdPtrInit_MASK                      0xf
#define D18F2x210_dct0_nbp3_Reserved_15_4_OFFSET                4
#define D18F2x210_dct0_nbp3_Reserved_15_4_WIDTH                 12
#define D18F2x210_dct0_nbp3_Reserved_15_4_MASK                  0xfff0
#define D18F2x210_dct0_nbp3_DataTxFifoWrDly_OFFSET              16
#define D18F2x210_dct0_nbp3_DataTxFifoWrDly_WIDTH               3
#define D18F2x210_dct0_nbp3_DataTxFifoWrDly_MASK                0x70000
#define D18F2x210_dct0_nbp3_Reserved_21_19_OFFSET               19
#define D18F2x210_dct0_nbp3_Reserved_21_19_WIDTH                3
#define D18F2x210_dct0_nbp3_Reserved_21_19_MASK                 0x380000
#define D18F2x210_dct0_nbp3_MaxRdLatency_OFFSET                 22
#define D18F2x210_dct0_nbp3_MaxRdLatency_WIDTH                  10
#define D18F2x210_dct0_nbp3_MaxRdLatency_MASK                   0xffc00000

/// D18F2x210_dct0_nbp3
typedef union {
  struct {                                                              ///<
    UINT32                                                RdPtrInit:4 ; ///<
    UINT32                                            Reserved_15_4:12; ///<
    UINT32                                          DataTxFifoWrDly:3 ; ///<
    UINT32                                           Reserved_21_19:3 ; ///<
    UINT32                                             MaxRdLatency:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x210_dct0_nbp3_STRUCT;

// **** D18F2x210_dct1_nbp2 Register Definition ****
// Address
#define D18F2x210_dct1_nbp2_ADDRESS                             0x210

// Type
#define D18F2x210_dct1_nbp2_TYPE                                TYPE_D18F2_dct1
// Field Data
#define D18F2x210_dct1_nbp2_RdPtrInit_OFFSET                    0
#define D18F2x210_dct1_nbp2_RdPtrInit_WIDTH                     4
#define D18F2x210_dct1_nbp2_RdPtrInit_MASK                      0xf
#define D18F2x210_dct1_nbp2_Reserved_15_4_OFFSET                4
#define D18F2x210_dct1_nbp2_Reserved_15_4_WIDTH                 12
#define D18F2x210_dct1_nbp2_Reserved_15_4_MASK                  0xfff0
#define D18F2x210_dct1_nbp2_DataTxFifoWrDly_OFFSET              16
#define D18F2x210_dct1_nbp2_DataTxFifoWrDly_WIDTH               3
#define D18F2x210_dct1_nbp2_DataTxFifoWrDly_MASK                0x70000
#define D18F2x210_dct1_nbp2_Reserved_21_19_OFFSET               19
#define D18F2x210_dct1_nbp2_Reserved_21_19_WIDTH                3
#define D18F2x210_dct1_nbp2_Reserved_21_19_MASK                 0x380000
#define D18F2x210_dct1_nbp2_MaxRdLatency_OFFSET                 22
#define D18F2x210_dct1_nbp2_MaxRdLatency_WIDTH                  10
#define D18F2x210_dct1_nbp2_MaxRdLatency_MASK                   0xffc00000

/// D18F2x210_dct1_nbp2
typedef union {
  struct {                                                              ///<
    UINT32                                                RdPtrInit:4 ; ///<
    UINT32                                            Reserved_15_4:12; ///<
    UINT32                                          DataTxFifoWrDly:3 ; ///<
    UINT32                                           Reserved_21_19:3 ; ///<
    UINT32                                             MaxRdLatency:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x210_dct1_nbp2_STRUCT;

// **** D18F2x210_dct0_nbp1 Register Definition ****
// Address
#define D18F2x210_dct0_nbp1_ADDRESS                             0x210

// Type
#define D18F2x210_dct0_nbp1_TYPE                                TYPE_D18F2_dct0
// Field Data
#define D18F2x210_dct0_nbp1_RdPtrInit_OFFSET                    0
#define D18F2x210_dct0_nbp1_RdPtrInit_WIDTH                     4
#define D18F2x210_dct0_nbp1_RdPtrInit_MASK                      0xf
#define D18F2x210_dct0_nbp1_Reserved_15_4_OFFSET                4
#define D18F2x210_dct0_nbp1_Reserved_15_4_WIDTH                 12
#define D18F2x210_dct0_nbp1_Reserved_15_4_MASK                  0xfff0
#define D18F2x210_dct0_nbp1_DataTxFifoWrDly_OFFSET              16
#define D18F2x210_dct0_nbp1_DataTxFifoWrDly_WIDTH               3
#define D18F2x210_dct0_nbp1_DataTxFifoWrDly_MASK                0x70000
#define D18F2x210_dct0_nbp1_Reserved_21_19_OFFSET               19
#define D18F2x210_dct0_nbp1_Reserved_21_19_WIDTH                3
#define D18F2x210_dct0_nbp1_Reserved_21_19_MASK                 0x380000
#define D18F2x210_dct0_nbp1_MaxRdLatency_OFFSET                 22
#define D18F2x210_dct0_nbp1_MaxRdLatency_WIDTH                  10
#define D18F2x210_dct0_nbp1_MaxRdLatency_MASK                   0xffc00000

/// D18F2x210_dct0_nbp1
typedef union {
  struct {                                                              ///<
    UINT32                                                RdPtrInit:4 ; ///<
    UINT32                                            Reserved_15_4:12; ///<
    UINT32                                          DataTxFifoWrDly:3 ; ///<
    UINT32                                           Reserved_21_19:3 ; ///<
    UINT32                                             MaxRdLatency:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x210_dct0_nbp1_STRUCT;

// **** D18F2x214_dct1_mp1 Register Definition ****
// Address
#define D18F2x214_dct1_mp1_ADDRESS                              0x214

// Type
#define D18F2x214_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
// Field Data
#define D18F2x214_dct1_mp1_TwrwrDd_OFFSET                       0
#define D18F2x214_dct1_mp1_TwrwrDd_WIDTH                        4
#define D18F2x214_dct1_mp1_TwrwrDd_MASK                         0xf
#define D18F2x214_dct1_mp1_Reserved_7_4_OFFSET                  4
#define D18F2x214_dct1_mp1_Reserved_7_4_WIDTH                   4
#define D18F2x214_dct1_mp1_Reserved_7_4_MASK                    0xf0
#define D18F2x214_dct1_mp1_TwrwrSdDc_OFFSET                     8
#define D18F2x214_dct1_mp1_TwrwrSdDc_WIDTH                      4
#define D18F2x214_dct1_mp1_TwrwrSdDc_MASK                       0xf00
#define D18F2x214_dct1_mp1_Reserved_15_12_OFFSET                12
#define D18F2x214_dct1_mp1_Reserved_15_12_WIDTH                 4
#define D18F2x214_dct1_mp1_Reserved_15_12_MASK                  0xf000
#define D18F2x214_dct1_mp1_TwrwrSdSc_OFFSET                     16
#define D18F2x214_dct1_mp1_TwrwrSdSc_WIDTH                      4
#define D18F2x214_dct1_mp1_TwrwrSdSc_MASK                       0xf0000
#define D18F2x214_dct1_mp1_Reserved_31_20_OFFSET                20
#define D18F2x214_dct1_mp1_Reserved_31_20_WIDTH                 12
#define D18F2x214_dct1_mp1_Reserved_31_20_MASK                  0xfff00000

/// D18F2x214_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                  TwrwrDd:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                TwrwrSdDc:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                                TwrwrSdSc:4 ; ///<
    UINT32                                           Reserved_31_20:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x214_dct1_mp1_STRUCT;

// **** D18F2x214_dct0_mp0 Register Definition ****
// Address
#define D18F2x214_dct0_mp0_ADDRESS                              0x214

// Type
#define D18F2x214_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
// Field Data
#define D18F2x214_dct0_mp0_TwrwrDd_OFFSET                       0
#define D18F2x214_dct0_mp0_TwrwrDd_WIDTH                        4
#define D18F2x214_dct0_mp0_TwrwrDd_MASK                         0xf
#define D18F2x214_dct0_mp0_Reserved_7_4_OFFSET                  4
#define D18F2x214_dct0_mp0_Reserved_7_4_WIDTH                   4
#define D18F2x214_dct0_mp0_Reserved_7_4_MASK                    0xf0
#define D18F2x214_dct0_mp0_TwrwrSdDc_OFFSET                     8
#define D18F2x214_dct0_mp0_TwrwrSdDc_WIDTH                      4
#define D18F2x214_dct0_mp0_TwrwrSdDc_MASK                       0xf00
#define D18F2x214_dct0_mp0_Reserved_15_12_OFFSET                12
#define D18F2x214_dct0_mp0_Reserved_15_12_WIDTH                 4
#define D18F2x214_dct0_mp0_Reserved_15_12_MASK                  0xf000
#define D18F2x214_dct0_mp0_TwrwrSdSc_OFFSET                     16
#define D18F2x214_dct0_mp0_TwrwrSdSc_WIDTH                      4
#define D18F2x214_dct0_mp0_TwrwrSdSc_MASK                       0xf0000
#define D18F2x214_dct0_mp0_Reserved_31_20_OFFSET                20
#define D18F2x214_dct0_mp0_Reserved_31_20_WIDTH                 12
#define D18F2x214_dct0_mp0_Reserved_31_20_MASK                  0xfff00000

/// D18F2x214_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                  TwrwrDd:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                TwrwrSdDc:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                                TwrwrSdSc:4 ; ///<
    UINT32                                           Reserved_31_20:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x214_dct0_mp0_STRUCT;

// **** D18F2x214_dct1_mp0 Register Definition ****
// Address
#define D18F2x214_dct1_mp0_ADDRESS                              0x214

// Type
#define D18F2x214_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
// Field Data
#define D18F2x214_dct1_mp0_TwrwrDd_OFFSET                       0
#define D18F2x214_dct1_mp0_TwrwrDd_WIDTH                        4
#define D18F2x214_dct1_mp0_TwrwrDd_MASK                         0xf
#define D18F2x214_dct1_mp0_Reserved_7_4_OFFSET                  4
#define D18F2x214_dct1_mp0_Reserved_7_4_WIDTH                   4
#define D18F2x214_dct1_mp0_Reserved_7_4_MASK                    0xf0
#define D18F2x214_dct1_mp0_TwrwrSdDc_OFFSET                     8
#define D18F2x214_dct1_mp0_TwrwrSdDc_WIDTH                      4
#define D18F2x214_dct1_mp0_TwrwrSdDc_MASK                       0xf00
#define D18F2x214_dct1_mp0_Reserved_15_12_OFFSET                12
#define D18F2x214_dct1_mp0_Reserved_15_12_WIDTH                 4
#define D18F2x214_dct1_mp0_Reserved_15_12_MASK                  0xf000
#define D18F2x214_dct1_mp0_TwrwrSdSc_OFFSET                     16
#define D18F2x214_dct1_mp0_TwrwrSdSc_WIDTH                      4
#define D18F2x214_dct1_mp0_TwrwrSdSc_MASK                       0xf0000
#define D18F2x214_dct1_mp0_Reserved_31_20_OFFSET                20
#define D18F2x214_dct1_mp0_Reserved_31_20_WIDTH                 12
#define D18F2x214_dct1_mp0_Reserved_31_20_MASK                  0xfff00000

/// D18F2x214_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                  TwrwrDd:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                TwrwrSdDc:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                                TwrwrSdSc:4 ; ///<
    UINT32                                           Reserved_31_20:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x214_dct1_mp0_STRUCT;

// **** D18F2x214_dct0_mp1 Register Definition ****
// Address
#define D18F2x214_dct0_mp1_ADDRESS                              0x214

// Type
#define D18F2x214_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
// Field Data
#define D18F2x214_dct0_mp1_TwrwrDd_OFFSET                       0
#define D18F2x214_dct0_mp1_TwrwrDd_WIDTH                        4
#define D18F2x214_dct0_mp1_TwrwrDd_MASK                         0xf
#define D18F2x214_dct0_mp1_Reserved_7_4_OFFSET                  4
#define D18F2x214_dct0_mp1_Reserved_7_4_WIDTH                   4
#define D18F2x214_dct0_mp1_Reserved_7_4_MASK                    0xf0
#define D18F2x214_dct0_mp1_TwrwrSdDc_OFFSET                     8
#define D18F2x214_dct0_mp1_TwrwrSdDc_WIDTH                      4
#define D18F2x214_dct0_mp1_TwrwrSdDc_MASK                       0xf00
#define D18F2x214_dct0_mp1_Reserved_15_12_OFFSET                12
#define D18F2x214_dct0_mp1_Reserved_15_12_WIDTH                 4
#define D18F2x214_dct0_mp1_Reserved_15_12_MASK                  0xf000
#define D18F2x214_dct0_mp1_TwrwrSdSc_OFFSET                     16
#define D18F2x214_dct0_mp1_TwrwrSdSc_WIDTH                      4
#define D18F2x214_dct0_mp1_TwrwrSdSc_MASK                       0xf0000
#define D18F2x214_dct0_mp1_Reserved_31_20_OFFSET                20
#define D18F2x214_dct0_mp1_Reserved_31_20_WIDTH                 12
#define D18F2x214_dct0_mp1_Reserved_31_20_MASK                  0xfff00000

/// D18F2x214_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                  TwrwrDd:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                TwrwrSdDc:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                                TwrwrSdSc:4 ; ///<
    UINT32                                           Reserved_31_20:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x214_dct0_mp1_STRUCT;

// **** D18F2x218_dct0_mp1 Register Definition ****
// Address
#define D18F2x218_dct0_mp1_ADDRESS                              0x218

// Type
#define D18F2x218_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
// Field Data
#define D18F2x218_dct0_mp1_TrdrdDd_OFFSET                       0
#define D18F2x218_dct0_mp1_TrdrdDd_WIDTH                        4
#define D18F2x218_dct0_mp1_TrdrdDd_MASK                         0xf
#define D18F2x218_dct0_mp1_Reserved_7_4_OFFSET                  4
#define D18F2x218_dct0_mp1_Reserved_7_4_WIDTH                   4
#define D18F2x218_dct0_mp1_Reserved_7_4_MASK                    0xf0
#define D18F2x218_dct0_mp1_Twrrd_OFFSET                         8
#define D18F2x218_dct0_mp1_Twrrd_WIDTH                          4
#define D18F2x218_dct0_mp1_Twrrd_MASK                           0xf00
#define D18F2x218_dct0_mp1_Reserved_15_12_OFFSET                12
#define D18F2x218_dct0_mp1_Reserved_15_12_WIDTH                 4
#define D18F2x218_dct0_mp1_Reserved_15_12_MASK                  0xf000
#define D18F2x218_dct0_mp1_TrdrdSdDc_OFFSET                     16
#define D18F2x218_dct0_mp1_TrdrdSdDc_WIDTH                      4
#define D18F2x218_dct0_mp1_TrdrdSdDc_MASK                       0xf0000
#define D18F2x218_dct0_mp1_Reserved_23_20_OFFSET                20
#define D18F2x218_dct0_mp1_Reserved_23_20_WIDTH                 4
#define D18F2x218_dct0_mp1_Reserved_23_20_MASK                  0xf00000
#define D18F2x218_dct0_mp1_TrdrdSdSc_OFFSET                     24
#define D18F2x218_dct0_mp1_TrdrdSdSc_WIDTH                      4
#define D18F2x218_dct0_mp1_TrdrdSdSc_MASK                       0xf000000
#define D18F2x218_dct0_mp1_Reserved_31_28_OFFSET                28
#define D18F2x218_dct0_mp1_Reserved_31_28_WIDTH                 4
#define D18F2x218_dct0_mp1_Reserved_31_28_MASK                  0xf0000000

/// D18F2x218_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                  TrdrdDd:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                    Twrrd:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                                TrdrdSdDc:4 ; ///<
    UINT32                                           Reserved_23_20:4 ; ///<
    UINT32                                                TrdrdSdSc:4 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x218_dct0_mp1_STRUCT;

// **** D18F2x218_dct1_mp1 Register Definition ****
// Address
#define D18F2x218_dct1_mp1_ADDRESS                              0x218

// Type
#define D18F2x218_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
// Field Data
#define D18F2x218_dct1_mp1_TrdrdDd_OFFSET                       0
#define D18F2x218_dct1_mp1_TrdrdDd_WIDTH                        4
#define D18F2x218_dct1_mp1_TrdrdDd_MASK                         0xf
#define D18F2x218_dct1_mp1_Reserved_7_4_OFFSET                  4
#define D18F2x218_dct1_mp1_Reserved_7_4_WIDTH                   4
#define D18F2x218_dct1_mp1_Reserved_7_4_MASK                    0xf0
#define D18F2x218_dct1_mp1_Twrrd_OFFSET                         8
#define D18F2x218_dct1_mp1_Twrrd_WIDTH                          4
#define D18F2x218_dct1_mp1_Twrrd_MASK                           0xf00
#define D18F2x218_dct1_mp1_Reserved_15_12_OFFSET                12
#define D18F2x218_dct1_mp1_Reserved_15_12_WIDTH                 4
#define D18F2x218_dct1_mp1_Reserved_15_12_MASK                  0xf000
#define D18F2x218_dct1_mp1_TrdrdSdDc_OFFSET                     16
#define D18F2x218_dct1_mp1_TrdrdSdDc_WIDTH                      4
#define D18F2x218_dct1_mp1_TrdrdSdDc_MASK                       0xf0000
#define D18F2x218_dct1_mp1_Reserved_23_20_OFFSET                20
#define D18F2x218_dct1_mp1_Reserved_23_20_WIDTH                 4
#define D18F2x218_dct1_mp1_Reserved_23_20_MASK                  0xf00000
#define D18F2x218_dct1_mp1_TrdrdSdSc_OFFSET                     24
#define D18F2x218_dct1_mp1_TrdrdSdSc_WIDTH                      4
#define D18F2x218_dct1_mp1_TrdrdSdSc_MASK                       0xf000000
#define D18F2x218_dct1_mp1_Reserved_31_28_OFFSET                28
#define D18F2x218_dct1_mp1_Reserved_31_28_WIDTH                 4
#define D18F2x218_dct1_mp1_Reserved_31_28_MASK                  0xf0000000

/// D18F2x218_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                  TrdrdDd:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                    Twrrd:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                                TrdrdSdDc:4 ; ///<
    UINT32                                           Reserved_23_20:4 ; ///<
    UINT32                                                TrdrdSdSc:4 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x218_dct1_mp1_STRUCT;

// **** D18F2x218_dct0_mp0 Register Definition ****
// Address
#define D18F2x218_dct0_mp0_ADDRESS                              0x218

// Type
#define D18F2x218_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
// Field Data
#define D18F2x218_dct0_mp0_TrdrdDd_OFFSET                       0
#define D18F2x218_dct0_mp0_TrdrdDd_WIDTH                        4
#define D18F2x218_dct0_mp0_TrdrdDd_MASK                         0xf
#define D18F2x218_dct0_mp0_Reserved_7_4_OFFSET                  4
#define D18F2x218_dct0_mp0_Reserved_7_4_WIDTH                   4
#define D18F2x218_dct0_mp0_Reserved_7_4_MASK                    0xf0
#define D18F2x218_dct0_mp0_Twrrd_OFFSET                         8
#define D18F2x218_dct0_mp0_Twrrd_WIDTH                          4
#define D18F2x218_dct0_mp0_Twrrd_MASK                           0xf00
#define D18F2x218_dct0_mp0_Reserved_15_12_OFFSET                12
#define D18F2x218_dct0_mp0_Reserved_15_12_WIDTH                 4
#define D18F2x218_dct0_mp0_Reserved_15_12_MASK                  0xf000
#define D18F2x218_dct0_mp0_TrdrdSdDc_OFFSET                     16
#define D18F2x218_dct0_mp0_TrdrdSdDc_WIDTH                      4
#define D18F2x218_dct0_mp0_TrdrdSdDc_MASK                       0xf0000
#define D18F2x218_dct0_mp0_Reserved_23_20_OFFSET                20
#define D18F2x218_dct0_mp0_Reserved_23_20_WIDTH                 4
#define D18F2x218_dct0_mp0_Reserved_23_20_MASK                  0xf00000
#define D18F2x218_dct0_mp0_TrdrdSdSc_OFFSET                     24
#define D18F2x218_dct0_mp0_TrdrdSdSc_WIDTH                      4
#define D18F2x218_dct0_mp0_TrdrdSdSc_MASK                       0xf000000
#define D18F2x218_dct0_mp0_Reserved_31_28_OFFSET                28
#define D18F2x218_dct0_mp0_Reserved_31_28_WIDTH                 4
#define D18F2x218_dct0_mp0_Reserved_31_28_MASK                  0xf0000000

/// D18F2x218_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                  TrdrdDd:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                    Twrrd:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                                TrdrdSdDc:4 ; ///<
    UINT32                                           Reserved_23_20:4 ; ///<
    UINT32                                                TrdrdSdSc:4 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x218_dct0_mp0_STRUCT;

// **** D18F2x218_dct1_mp0 Register Definition ****
// Address
#define D18F2x218_dct1_mp0_ADDRESS                              0x218

// Type
#define D18F2x218_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
// Field Data
#define D18F2x218_dct1_mp0_TrdrdDd_OFFSET                       0
#define D18F2x218_dct1_mp0_TrdrdDd_WIDTH                        4
#define D18F2x218_dct1_mp0_TrdrdDd_MASK                         0xf
#define D18F2x218_dct1_mp0_Reserved_7_4_OFFSET                  4
#define D18F2x218_dct1_mp0_Reserved_7_4_WIDTH                   4
#define D18F2x218_dct1_mp0_Reserved_7_4_MASK                    0xf0
#define D18F2x218_dct1_mp0_Twrrd_OFFSET                         8
#define D18F2x218_dct1_mp0_Twrrd_WIDTH                          4
#define D18F2x218_dct1_mp0_Twrrd_MASK                           0xf00
#define D18F2x218_dct1_mp0_Reserved_15_12_OFFSET                12
#define D18F2x218_dct1_mp0_Reserved_15_12_WIDTH                 4
#define D18F2x218_dct1_mp0_Reserved_15_12_MASK                  0xf000
#define D18F2x218_dct1_mp0_TrdrdSdDc_OFFSET                     16
#define D18F2x218_dct1_mp0_TrdrdSdDc_WIDTH                      4
#define D18F2x218_dct1_mp0_TrdrdSdDc_MASK                       0xf0000
#define D18F2x218_dct1_mp0_Reserved_23_20_OFFSET                20
#define D18F2x218_dct1_mp0_Reserved_23_20_WIDTH                 4
#define D18F2x218_dct1_mp0_Reserved_23_20_MASK                  0xf00000
#define D18F2x218_dct1_mp0_TrdrdSdSc_OFFSET                     24
#define D18F2x218_dct1_mp0_TrdrdSdSc_WIDTH                      4
#define D18F2x218_dct1_mp0_TrdrdSdSc_MASK                       0xf000000
#define D18F2x218_dct1_mp0_Reserved_31_28_OFFSET                28
#define D18F2x218_dct1_mp0_Reserved_31_28_WIDTH                 4
#define D18F2x218_dct1_mp0_Reserved_31_28_MASK                  0xf0000000

/// D18F2x218_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                  TrdrdDd:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                    Twrrd:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                                TrdrdSdDc:4 ; ///<
    UINT32                                           Reserved_23_20:4 ; ///<
    UINT32                                                TrdrdSdSc:4 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x218_dct1_mp0_STRUCT;

// **** D18F2x21C_dct1_mp1 Register Definition ****
// Address
#define D18F2x21C_dct1_mp1_ADDRESS                              0x21c

// Type
#define D18F2x21C_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
// Field Data
#define D18F2x21C_dct1_mp1_Reserved_7_0_OFFSET                  0
#define D18F2x21C_dct1_mp1_Reserved_7_0_WIDTH                   8
#define D18F2x21C_dct1_mp1_Reserved_7_0_MASK                    0xff
#define D18F2x21C_dct1_mp1_TrwtTO_OFFSET                        8
#define D18F2x21C_dct1_mp1_TrwtTO_WIDTH                         5
#define D18F2x21C_dct1_mp1_TrwtTO_MASK                          0x1f00
#define D18F2x21C_dct1_mp1_Reserved_15_13_OFFSET                13
#define D18F2x21C_dct1_mp1_Reserved_15_13_WIDTH                 3
#define D18F2x21C_dct1_mp1_Reserved_15_13_MASK                  0xe000
#define D18F2x21C_dct1_mp1_TrwtWB_OFFSET                        16
#define D18F2x21C_dct1_mp1_TrwtWB_WIDTH                         5
#define D18F2x21C_dct1_mp1_TrwtWB_MASK                          0x1f0000
#define D18F2x21C_dct1_mp1_Reserved_31_21_OFFSET                21
#define D18F2x21C_dct1_mp1_Reserved_31_21_WIDTH                 11
#define D18F2x21C_dct1_mp1_Reserved_31_21_MASK                  0xffe00000

/// D18F2x21C_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_7_0:8 ; ///<
    UINT32                                                   TrwtTO:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                                   TrwtWB:5 ; ///<
    UINT32                                           Reserved_31_21:11; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x21C_dct1_mp1_STRUCT;

// **** D18F2x21C_dct1_mp0 Register Definition ****
// Address
#define D18F2x21C_dct1_mp0_ADDRESS                              0x21c

// Type
#define D18F2x21C_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
// Field Data
#define D18F2x21C_dct1_mp0_Reserved_7_0_OFFSET                  0
#define D18F2x21C_dct1_mp0_Reserved_7_0_WIDTH                   8
#define D18F2x21C_dct1_mp0_Reserved_7_0_MASK                    0xff
#define D18F2x21C_dct1_mp0_TrwtTO_OFFSET                        8
#define D18F2x21C_dct1_mp0_TrwtTO_WIDTH                         5
#define D18F2x21C_dct1_mp0_TrwtTO_MASK                          0x1f00
#define D18F2x21C_dct1_mp0_Reserved_15_13_OFFSET                13
#define D18F2x21C_dct1_mp0_Reserved_15_13_WIDTH                 3
#define D18F2x21C_dct1_mp0_Reserved_15_13_MASK                  0xe000
#define D18F2x21C_dct1_mp0_TrwtWB_OFFSET                        16
#define D18F2x21C_dct1_mp0_TrwtWB_WIDTH                         5
#define D18F2x21C_dct1_mp0_TrwtWB_MASK                          0x1f0000
#define D18F2x21C_dct1_mp0_Reserved_31_21_OFFSET                21
#define D18F2x21C_dct1_mp0_Reserved_31_21_WIDTH                 11
#define D18F2x21C_dct1_mp0_Reserved_31_21_MASK                  0xffe00000

/// D18F2x21C_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_7_0:8 ; ///<
    UINT32                                                   TrwtTO:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                                   TrwtWB:5 ; ///<
    UINT32                                           Reserved_31_21:11; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x21C_dct1_mp0_STRUCT;

// **** D18F2x21C_dct0_mp0 Register Definition ****
// Address
#define D18F2x21C_dct0_mp0_ADDRESS                              0x21c

// Type
#define D18F2x21C_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
// Field Data
#define D18F2x21C_dct0_mp0_Reserved_7_0_OFFSET                  0
#define D18F2x21C_dct0_mp0_Reserved_7_0_WIDTH                   8
#define D18F2x21C_dct0_mp0_Reserved_7_0_MASK                    0xff
#define D18F2x21C_dct0_mp0_TrwtTO_OFFSET                        8
#define D18F2x21C_dct0_mp0_TrwtTO_WIDTH                         5
#define D18F2x21C_dct0_mp0_TrwtTO_MASK                          0x1f00
#define D18F2x21C_dct0_mp0_Reserved_15_13_OFFSET                13
#define D18F2x21C_dct0_mp0_Reserved_15_13_WIDTH                 3
#define D18F2x21C_dct0_mp0_Reserved_15_13_MASK                  0xe000
#define D18F2x21C_dct0_mp0_TrwtWB_OFFSET                        16
#define D18F2x21C_dct0_mp0_TrwtWB_WIDTH                         5
#define D18F2x21C_dct0_mp0_TrwtWB_MASK                          0x1f0000
#define D18F2x21C_dct0_mp0_Reserved_31_21_OFFSET                21
#define D18F2x21C_dct0_mp0_Reserved_31_21_WIDTH                 11
#define D18F2x21C_dct0_mp0_Reserved_31_21_MASK                  0xffe00000

/// D18F2x21C_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_7_0:8 ; ///<
    UINT32                                                   TrwtTO:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                                   TrwtWB:5 ; ///<
    UINT32                                           Reserved_31_21:11; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x21C_dct0_mp0_STRUCT;

// **** D18F2x21C_dct0_mp1 Register Definition ****
// Address
#define D18F2x21C_dct0_mp1_ADDRESS                              0x21c

// Type
#define D18F2x21C_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
// Field Data
#define D18F2x21C_dct0_mp1_Reserved_7_0_OFFSET                  0
#define D18F2x21C_dct0_mp1_Reserved_7_0_WIDTH                   8
#define D18F2x21C_dct0_mp1_Reserved_7_0_MASK                    0xff
#define D18F2x21C_dct0_mp1_TrwtTO_OFFSET                        8
#define D18F2x21C_dct0_mp1_TrwtTO_WIDTH                         5
#define D18F2x21C_dct0_mp1_TrwtTO_MASK                          0x1f00
#define D18F2x21C_dct0_mp1_Reserved_15_13_OFFSET                13
#define D18F2x21C_dct0_mp1_Reserved_15_13_WIDTH                 3
#define D18F2x21C_dct0_mp1_Reserved_15_13_MASK                  0xe000
#define D18F2x21C_dct0_mp1_TrwtWB_OFFSET                        16
#define D18F2x21C_dct0_mp1_TrwtWB_WIDTH                         5
#define D18F2x21C_dct0_mp1_TrwtWB_MASK                          0x1f0000
#define D18F2x21C_dct0_mp1_Reserved_31_21_OFFSET                21
#define D18F2x21C_dct0_mp1_Reserved_31_21_WIDTH                 11
#define D18F2x21C_dct0_mp1_Reserved_31_21_MASK                  0xffe00000

/// D18F2x21C_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_7_0:8 ; ///<
    UINT32                                                   TrwtTO:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                                   TrwtWB:5 ; ///<
    UINT32                                           Reserved_31_21:11; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x21C_dct0_mp1_STRUCT;

// **** D18F2x220_dct1 Register Definition ****
// Address
#define D18F2x220_dct1_ADDRESS                                  0x220

// Type
#define D18F2x220_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x220_dct1_Tmrd_OFFSET                              0
#define D18F2x220_dct1_Tmrd_WIDTH                               4
#define D18F2x220_dct1_Tmrd_MASK                                0xf
#define D18F2x220_dct1_Reserved_7_4_OFFSET                      4
#define D18F2x220_dct1_Reserved_7_4_WIDTH                       4
#define D18F2x220_dct1_Reserved_7_4_MASK                        0xf0
#define D18F2x220_dct1_Tmod_OFFSET                              8
#define D18F2x220_dct1_Tmod_WIDTH                               5
#define D18F2x220_dct1_Tmod_MASK                                0x1f00
#define D18F2x220_dct1_Reserved_31_13_OFFSET                    13
#define D18F2x220_dct1_Reserved_31_13_WIDTH                     19
#define D18F2x220_dct1_Reserved_31_13_MASK                      0xffffe000

/// D18F2x220_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                     Tmrd:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                     Tmod:5 ; ///<
    UINT32                                           Reserved_31_13:19; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x220_dct1_STRUCT;

// **** D18F2x220_dct0 Register Definition ****
// Address
#define D18F2x220_dct0_ADDRESS                                  0x220

// Type
#define D18F2x220_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x220_dct0_Tmrd_OFFSET                              0
#define D18F2x220_dct0_Tmrd_WIDTH                               4
#define D18F2x220_dct0_Tmrd_MASK                                0xf
#define D18F2x220_dct0_Reserved_7_4_OFFSET                      4
#define D18F2x220_dct0_Reserved_7_4_WIDTH                       4
#define D18F2x220_dct0_Reserved_7_4_MASK                        0xf0
#define D18F2x220_dct0_Tmod_OFFSET                              8
#define D18F2x220_dct0_Tmod_WIDTH                               5
#define D18F2x220_dct0_Tmod_MASK                                0x1f00
#define D18F2x220_dct0_Reserved_31_13_OFFSET                    13
#define D18F2x220_dct0_Reserved_31_13_WIDTH                     19
#define D18F2x220_dct0_Reserved_31_13_MASK                      0xffffe000

/// D18F2x220_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                     Tmrd:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                     Tmod:5 ; ///<
    UINT32                                           Reserved_31_13:19; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x220_dct0_STRUCT;

// **** D18F2x224_dct0 Register Definition ****
// Address
#define D18F2x224_dct0_ADDRESS                                  0x224

// Type
#define D18F2x224_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x224_dct0_Tzqoper_OFFSET                           0
#define D18F2x224_dct0_Tzqoper_WIDTH                            4
#define D18F2x224_dct0_Tzqoper_MASK                             0xf
#define D18F2x224_dct0_Reserved_7_4_OFFSET                      4
#define D18F2x224_dct0_Reserved_7_4_WIDTH                       4
#define D18F2x224_dct0_Reserved_7_4_MASK                        0xf0
#define D18F2x224_dct0_Tzqcs_OFFSET                             8
#define D18F2x224_dct0_Tzqcs_WIDTH                              3
#define D18F2x224_dct0_Tzqcs_MASK                               0x700
#define D18F2x224_dct0_Reserved_31_11_OFFSET                    11
#define D18F2x224_dct0_Reserved_31_11_WIDTH                     21
#define D18F2x224_dct0_Reserved_31_11_MASK                      0xfffff800

/// D18F2x224_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                  Tzqoper:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                    Tzqcs:3 ; ///<
    UINT32                                           Reserved_31_11:21; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x224_dct0_STRUCT;

// **** D18F2x224_dct1 Register Definition ****
// Address
#define D18F2x224_dct1_ADDRESS                                  0x224

// Type
#define D18F2x224_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x224_dct1_Tzqoper_OFFSET                           0
#define D18F2x224_dct1_Tzqoper_WIDTH                            4
#define D18F2x224_dct1_Tzqoper_MASK                             0xf
#define D18F2x224_dct1_Reserved_7_4_OFFSET                      4
#define D18F2x224_dct1_Reserved_7_4_WIDTH                       4
#define D18F2x224_dct1_Reserved_7_4_MASK                        0xf0
#define D18F2x224_dct1_Tzqcs_OFFSET                             8
#define D18F2x224_dct1_Tzqcs_WIDTH                              3
#define D18F2x224_dct1_Tzqcs_MASK                               0x700
#define D18F2x224_dct1_Reserved_31_11_OFFSET                    11
#define D18F2x224_dct1_Reserved_31_11_WIDTH                     21
#define D18F2x224_dct1_Reserved_31_11_MASK                      0xfffff800

/// D18F2x224_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                  Tzqoper:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                    Tzqcs:3 ; ///<
    UINT32                                           Reserved_31_11:21; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x224_dct1_STRUCT;

// **** D18F2x228_dct1 Register Definition ****
// Address
#define D18F2x228_dct1_ADDRESS                                  0x228

// Type
#define D18F2x228_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x228_dct1_Tstag0_OFFSET                            0
#define D18F2x228_dct1_Tstag0_WIDTH                             8
#define D18F2x228_dct1_Tstag0_MASK                              0xff
#define D18F2x228_dct1_Tstag1_OFFSET                            8
#define D18F2x228_dct1_Tstag1_WIDTH                             8
#define D18F2x228_dct1_Tstag1_MASK                              0xff00
#define D18F2x228_dct1_Tstag2_OFFSET                            16
#define D18F2x228_dct1_Tstag2_WIDTH                             8
#define D18F2x228_dct1_Tstag2_MASK                              0xff0000
#define D18F2x228_dct1_Tstag3_OFFSET                            24
#define D18F2x228_dct1_Tstag3_WIDTH                             8
#define D18F2x228_dct1_Tstag3_MASK                              0xff000000

/// D18F2x228_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                   Tstag0:8 ; ///<
    UINT32                                                   Tstag1:8 ; ///<
    UINT32                                                   Tstag2:8 ; ///<
    UINT32                                                   Tstag3:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x228_dct1_STRUCT;

// **** D18F2x228_dct0 Register Definition ****
// Address
#define D18F2x228_dct0_ADDRESS                                  0x228

// Type
#define D18F2x228_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x228_dct0_Tstag0_OFFSET                            0
#define D18F2x228_dct0_Tstag0_WIDTH                             8
#define D18F2x228_dct0_Tstag0_MASK                              0xff
#define D18F2x228_dct0_Tstag1_OFFSET                            8
#define D18F2x228_dct0_Tstag1_WIDTH                             8
#define D18F2x228_dct0_Tstag1_MASK                              0xff00
#define D18F2x228_dct0_Tstag2_OFFSET                            16
#define D18F2x228_dct0_Tstag2_WIDTH                             8
#define D18F2x228_dct0_Tstag2_MASK                              0xff0000
#define D18F2x228_dct0_Tstag3_OFFSET                            24
#define D18F2x228_dct0_Tstag3_WIDTH                             8
#define D18F2x228_dct0_Tstag3_MASK                              0xff000000

/// D18F2x228_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                   Tstag0:8 ; ///<
    UINT32                                                   Tstag1:8 ; ///<
    UINT32                                                   Tstag2:8 ; ///<
    UINT32                                                   Tstag3:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x228_dct0_STRUCT;

// **** D18F2x22C_dct1_mp1 Register Definition ****
// Address
#define D18F2x22C_dct1_mp1_ADDRESS                              0x22c

// Type
#define D18F2x22C_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
// Field Data
#define D18F2x22C_dct1_mp1_Twr_OFFSET                           0
#define D18F2x22C_dct1_mp1_Twr_WIDTH                            5
#define D18F2x22C_dct1_mp1_Twr_MASK                             0x1f
#define D18F2x22C_dct1_mp1_Reserved_31_5_OFFSET                 5
#define D18F2x22C_dct1_mp1_Reserved_31_5_WIDTH                  27
#define D18F2x22C_dct1_mp1_Reserved_31_5_MASK                   0xffffffe0

/// D18F2x22C_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                      Twr:5 ; ///<
    UINT32                                            Reserved_31_5:27; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x22C_dct1_mp1_STRUCT;

// **** D18F2x22C_dct1_mp0 Register Definition ****
// Address
#define D18F2x22C_dct1_mp0_ADDRESS                              0x22c

// Type
#define D18F2x22C_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
// Field Data
#define D18F2x22C_dct1_mp0_Twr_OFFSET                           0
#define D18F2x22C_dct1_mp0_Twr_WIDTH                            5
#define D18F2x22C_dct1_mp0_Twr_MASK                             0x1f
#define D18F2x22C_dct1_mp0_Reserved_31_5_OFFSET                 5
#define D18F2x22C_dct1_mp0_Reserved_31_5_WIDTH                  27
#define D18F2x22C_dct1_mp0_Reserved_31_5_MASK                   0xffffffe0

/// D18F2x22C_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                      Twr:5 ; ///<
    UINT32                                            Reserved_31_5:27; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x22C_dct1_mp0_STRUCT;

// **** D18F2x22C_dct0_mp0 Register Definition ****
// Address
#define D18F2x22C_dct0_mp0_ADDRESS                              0x22c

// Type
#define D18F2x22C_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
// Field Data
#define D18F2x22C_dct0_mp0_Twr_OFFSET                           0
#define D18F2x22C_dct0_mp0_Twr_WIDTH                            5
#define D18F2x22C_dct0_mp0_Twr_MASK                             0x1f
#define D18F2x22C_dct0_mp0_Reserved_31_5_OFFSET                 5
#define D18F2x22C_dct0_mp0_Reserved_31_5_WIDTH                  27
#define D18F2x22C_dct0_mp0_Reserved_31_5_MASK                   0xffffffe0

/// D18F2x22C_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                      Twr:5 ; ///<
    UINT32                                            Reserved_31_5:27; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x22C_dct0_mp0_STRUCT;

// **** D18F2x22C_dct0_mp1 Register Definition ****
// Address
#define D18F2x22C_dct0_mp1_ADDRESS                              0x22c

// Type
#define D18F2x22C_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
// Field Data
#define D18F2x22C_dct0_mp1_Twr_OFFSET                           0
#define D18F2x22C_dct0_mp1_Twr_WIDTH                            5
#define D18F2x22C_dct0_mp1_Twr_MASK                             0x1f
#define D18F2x22C_dct0_mp1_Reserved_31_5_OFFSET                 5
#define D18F2x22C_dct0_mp1_Reserved_31_5_WIDTH                  27
#define D18F2x22C_dct0_mp1_Reserved_31_5_MASK                   0xffffffe0

/// D18F2x22C_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                      Twr:5 ; ///<
    UINT32                                            Reserved_31_5:27; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x22C_dct0_mp1_STRUCT;

// **** D18F2x230_dct0 Register Definition ****
// Address
#define D18F2x230_dct0_ADDRESS                                  0x230

// Type
#define D18F2x230_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x230_dct0_RdOdtPatCs40_OFFSET                      0
#define D18F2x230_dct0_RdOdtPatCs40_WIDTH                       4
#define D18F2x230_dct0_RdOdtPatCs40_MASK                        0xf
#define D18F2x230_dct0_Reserved_7_4_OFFSET                      4
#define D18F2x230_dct0_Reserved_7_4_WIDTH                       4
#define D18F2x230_dct0_Reserved_7_4_MASK                        0xf0
#define D18F2x230_dct0_RdOdtPatCs51_OFFSET                      8
#define D18F2x230_dct0_RdOdtPatCs51_WIDTH                       4
#define D18F2x230_dct0_RdOdtPatCs51_MASK                        0xf00
#define D18F2x230_dct0_Reserved_15_12_OFFSET                    12
#define D18F2x230_dct0_Reserved_15_12_WIDTH                     4
#define D18F2x230_dct0_Reserved_15_12_MASK                      0xf000
#define D18F2x230_dct0_RdOdtPatCs62_OFFSET                      16
#define D18F2x230_dct0_RdOdtPatCs62_WIDTH                       4
#define D18F2x230_dct0_RdOdtPatCs62_MASK                        0xf0000
#define D18F2x230_dct0_Reserved_23_20_OFFSET                    20
#define D18F2x230_dct0_Reserved_23_20_WIDTH                     4
#define D18F2x230_dct0_Reserved_23_20_MASK                      0xf00000
#define D18F2x230_dct0_RdOdtPatCs73_OFFSET                      24
#define D18F2x230_dct0_RdOdtPatCs73_WIDTH                       4
#define D18F2x230_dct0_RdOdtPatCs73_MASK                        0xf000000
#define D18F2x230_dct0_Reserved_31_28_OFFSET                    28
#define D18F2x230_dct0_Reserved_31_28_WIDTH                     4
#define D18F2x230_dct0_Reserved_31_28_MASK                      0xf0000000

/// D18F2x230_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             RdOdtPatCs40:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                             RdOdtPatCs51:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                             RdOdtPatCs62:4 ; ///<
    UINT32                                           Reserved_23_20:4 ; ///<
    UINT32                                             RdOdtPatCs73:4 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x230_dct0_STRUCT;

// **** D18F2x230_dct1 Register Definition ****
// Address
#define D18F2x230_dct1_ADDRESS                                  0x230

// Type
#define D18F2x230_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x230_dct1_RdOdtPatCs40_OFFSET                      0
#define D18F2x230_dct1_RdOdtPatCs40_WIDTH                       4
#define D18F2x230_dct1_RdOdtPatCs40_MASK                        0xf
#define D18F2x230_dct1_Reserved_7_4_OFFSET                      4
#define D18F2x230_dct1_Reserved_7_4_WIDTH                       4
#define D18F2x230_dct1_Reserved_7_4_MASK                        0xf0
#define D18F2x230_dct1_RdOdtPatCs51_OFFSET                      8
#define D18F2x230_dct1_RdOdtPatCs51_WIDTH                       4
#define D18F2x230_dct1_RdOdtPatCs51_MASK                        0xf00
#define D18F2x230_dct1_Reserved_15_12_OFFSET                    12
#define D18F2x230_dct1_Reserved_15_12_WIDTH                     4
#define D18F2x230_dct1_Reserved_15_12_MASK                      0xf000
#define D18F2x230_dct1_RdOdtPatCs62_OFFSET                      16
#define D18F2x230_dct1_RdOdtPatCs62_WIDTH                       4
#define D18F2x230_dct1_RdOdtPatCs62_MASK                        0xf0000
#define D18F2x230_dct1_Reserved_23_20_OFFSET                    20
#define D18F2x230_dct1_Reserved_23_20_WIDTH                     4
#define D18F2x230_dct1_Reserved_23_20_MASK                      0xf00000
#define D18F2x230_dct1_RdOdtPatCs73_OFFSET                      24
#define D18F2x230_dct1_RdOdtPatCs73_WIDTH                       4
#define D18F2x230_dct1_RdOdtPatCs73_MASK                        0xf000000
#define D18F2x230_dct1_Reserved_31_28_OFFSET                    28
#define D18F2x230_dct1_Reserved_31_28_WIDTH                     4
#define D18F2x230_dct1_Reserved_31_28_MASK                      0xf0000000

/// D18F2x230_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             RdOdtPatCs40:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                             RdOdtPatCs51:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                             RdOdtPatCs62:4 ; ///<
    UINT32                                           Reserved_23_20:4 ; ///<
    UINT32                                             RdOdtPatCs73:4 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x230_dct1_STRUCT;

// **** D18F2x234_dct1 Register Definition ****
// Address
#define D18F2x234_dct1_ADDRESS                                  0x234

// Type
#define D18F2x234_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x234_dct1_RdOdtPatCs40_OFFSET                      0
#define D18F2x234_dct1_RdOdtPatCs40_WIDTH                       4
#define D18F2x234_dct1_RdOdtPatCs40_MASK                        0xf
#define D18F2x234_dct1_Reserved_7_4_OFFSET                      4
#define D18F2x234_dct1_Reserved_7_4_WIDTH                       4
#define D18F2x234_dct1_Reserved_7_4_MASK                        0xf0
#define D18F2x234_dct1_RdOdtPatCs51_OFFSET                      8
#define D18F2x234_dct1_RdOdtPatCs51_WIDTH                       4
#define D18F2x234_dct1_RdOdtPatCs51_MASK                        0xf00
#define D18F2x234_dct1_Reserved_15_12_OFFSET                    12
#define D18F2x234_dct1_Reserved_15_12_WIDTH                     4
#define D18F2x234_dct1_Reserved_15_12_MASK                      0xf000
#define D18F2x234_dct1_RdOdtPatCs62_OFFSET                      16
#define D18F2x234_dct1_RdOdtPatCs62_WIDTH                       4
#define D18F2x234_dct1_RdOdtPatCs62_MASK                        0xf0000
#define D18F2x234_dct1_Reserved_23_20_OFFSET                    20
#define D18F2x234_dct1_Reserved_23_20_WIDTH                     4
#define D18F2x234_dct1_Reserved_23_20_MASK                      0xf00000
#define D18F2x234_dct1_RdOdtPatCs73_OFFSET                      24
#define D18F2x234_dct1_RdOdtPatCs73_WIDTH                       4
#define D18F2x234_dct1_RdOdtPatCs73_MASK                        0xf000000
#define D18F2x234_dct1_Reserved_31_28_OFFSET                    28
#define D18F2x234_dct1_Reserved_31_28_WIDTH                     4
#define D18F2x234_dct1_Reserved_31_28_MASK                      0xf0000000

/// D18F2x234_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             RdOdtPatCs40:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                             RdOdtPatCs51:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                             RdOdtPatCs62:4 ; ///<
    UINT32                                           Reserved_23_20:4 ; ///<
    UINT32                                             RdOdtPatCs73:4 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x234_dct1_STRUCT;

// **** D18F2x234_dct0 Register Definition ****
// Address
#define D18F2x234_dct0_ADDRESS                                  0x234

// Type
#define D18F2x234_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x234_dct0_RdOdtPatCs40_OFFSET                      0
#define D18F2x234_dct0_RdOdtPatCs40_WIDTH                       4
#define D18F2x234_dct0_RdOdtPatCs40_MASK                        0xf
#define D18F2x234_dct0_Reserved_7_4_OFFSET                      4
#define D18F2x234_dct0_Reserved_7_4_WIDTH                       4
#define D18F2x234_dct0_Reserved_7_4_MASK                        0xf0
#define D18F2x234_dct0_RdOdtPatCs51_OFFSET                      8
#define D18F2x234_dct0_RdOdtPatCs51_WIDTH                       4
#define D18F2x234_dct0_RdOdtPatCs51_MASK                        0xf00
#define D18F2x234_dct0_Reserved_15_12_OFFSET                    12
#define D18F2x234_dct0_Reserved_15_12_WIDTH                     4
#define D18F2x234_dct0_Reserved_15_12_MASK                      0xf000
#define D18F2x234_dct0_RdOdtPatCs62_OFFSET                      16
#define D18F2x234_dct0_RdOdtPatCs62_WIDTH                       4
#define D18F2x234_dct0_RdOdtPatCs62_MASK                        0xf0000
#define D18F2x234_dct0_Reserved_23_20_OFFSET                    20
#define D18F2x234_dct0_Reserved_23_20_WIDTH                     4
#define D18F2x234_dct0_Reserved_23_20_MASK                      0xf00000
#define D18F2x234_dct0_RdOdtPatCs73_OFFSET                      24
#define D18F2x234_dct0_RdOdtPatCs73_WIDTH                       4
#define D18F2x234_dct0_RdOdtPatCs73_MASK                        0xf000000
#define D18F2x234_dct0_Reserved_31_28_OFFSET                    28
#define D18F2x234_dct0_Reserved_31_28_WIDTH                     4
#define D18F2x234_dct0_Reserved_31_28_MASK                      0xf0000000

/// D18F2x234_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             RdOdtPatCs40:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                             RdOdtPatCs51:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                             RdOdtPatCs62:4 ; ///<
    UINT32                                           Reserved_23_20:4 ; ///<
    UINT32                                             RdOdtPatCs73:4 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x234_dct0_STRUCT;

// **** D18F2x238_dct1 Register Definition ****
// Address
#define D18F2x238_dct1_ADDRESS                                  0x238

// Type
#define D18F2x238_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x238_dct1_WrOdtPatCs40_OFFSET                      0
#define D18F2x238_dct1_WrOdtPatCs40_WIDTH                       4
#define D18F2x238_dct1_WrOdtPatCs40_MASK                        0xf
#define D18F2x238_dct1_Reserved_7_4_OFFSET                      4
#define D18F2x238_dct1_Reserved_7_4_WIDTH                       4
#define D18F2x238_dct1_Reserved_7_4_MASK                        0xf0
#define D18F2x238_dct1_WrOdtPatCs51_OFFSET                      8
#define D18F2x238_dct1_WrOdtPatCs51_WIDTH                       4
#define D18F2x238_dct1_WrOdtPatCs51_MASK                        0xf00
#define D18F2x238_dct1_Reserved_15_12_OFFSET                    12
#define D18F2x238_dct1_Reserved_15_12_WIDTH                     4
#define D18F2x238_dct1_Reserved_15_12_MASK                      0xf000
#define D18F2x238_dct1_WrOdtPatCs62_OFFSET                      16
#define D18F2x238_dct1_WrOdtPatCs62_WIDTH                       4
#define D18F2x238_dct1_WrOdtPatCs62_MASK                        0xf0000
#define D18F2x238_dct1_Reserved_23_20_OFFSET                    20
#define D18F2x238_dct1_Reserved_23_20_WIDTH                     4
#define D18F2x238_dct1_Reserved_23_20_MASK                      0xf00000
#define D18F2x238_dct1_WrOdtPatCs73_OFFSET                      24
#define D18F2x238_dct1_WrOdtPatCs73_WIDTH                       4
#define D18F2x238_dct1_WrOdtPatCs73_MASK                        0xf000000
#define D18F2x238_dct1_Reserved_31_28_OFFSET                    28
#define D18F2x238_dct1_Reserved_31_28_WIDTH                     4
#define D18F2x238_dct1_Reserved_31_28_MASK                      0xf0000000

/// D18F2x238_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrOdtPatCs40:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                             WrOdtPatCs51:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                             WrOdtPatCs62:4 ; ///<
    UINT32                                           Reserved_23_20:4 ; ///<
    UINT32                                             WrOdtPatCs73:4 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x238_dct1_STRUCT;

// **** D18F2x238_dct0 Register Definition ****
// Address
#define D18F2x238_dct0_ADDRESS                                  0x238

// Type
#define D18F2x238_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x238_dct0_WrOdtPatCs40_OFFSET                      0
#define D18F2x238_dct0_WrOdtPatCs40_WIDTH                       4
#define D18F2x238_dct0_WrOdtPatCs40_MASK                        0xf
#define D18F2x238_dct0_Reserved_7_4_OFFSET                      4
#define D18F2x238_dct0_Reserved_7_4_WIDTH                       4
#define D18F2x238_dct0_Reserved_7_4_MASK                        0xf0
#define D18F2x238_dct0_WrOdtPatCs51_OFFSET                      8
#define D18F2x238_dct0_WrOdtPatCs51_WIDTH                       4
#define D18F2x238_dct0_WrOdtPatCs51_MASK                        0xf00
#define D18F2x238_dct0_Reserved_15_12_OFFSET                    12
#define D18F2x238_dct0_Reserved_15_12_WIDTH                     4
#define D18F2x238_dct0_Reserved_15_12_MASK                      0xf000
#define D18F2x238_dct0_WrOdtPatCs62_OFFSET                      16
#define D18F2x238_dct0_WrOdtPatCs62_WIDTH                       4
#define D18F2x238_dct0_WrOdtPatCs62_MASK                        0xf0000
#define D18F2x238_dct0_Reserved_23_20_OFFSET                    20
#define D18F2x238_dct0_Reserved_23_20_WIDTH                     4
#define D18F2x238_dct0_Reserved_23_20_MASK                      0xf00000
#define D18F2x238_dct0_WrOdtPatCs73_OFFSET                      24
#define D18F2x238_dct0_WrOdtPatCs73_WIDTH                       4
#define D18F2x238_dct0_WrOdtPatCs73_MASK                        0xf000000
#define D18F2x238_dct0_Reserved_31_28_OFFSET                    28
#define D18F2x238_dct0_Reserved_31_28_WIDTH                     4
#define D18F2x238_dct0_Reserved_31_28_MASK                      0xf0000000

/// D18F2x238_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrOdtPatCs40:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                             WrOdtPatCs51:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                             WrOdtPatCs62:4 ; ///<
    UINT32                                           Reserved_23_20:4 ; ///<
    UINT32                                             WrOdtPatCs73:4 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x238_dct0_STRUCT;

// **** D18F2x23C_dct0 Register Definition ****
// Address
#define D18F2x23C_dct0_ADDRESS                                  0x23c

// Type
#define D18F2x23C_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x23C_dct0_WrOdtPatCs40_OFFSET                      0
#define D18F2x23C_dct0_WrOdtPatCs40_WIDTH                       4
#define D18F2x23C_dct0_WrOdtPatCs40_MASK                        0xf
#define D18F2x23C_dct0_Reserved_7_4_OFFSET                      4
#define D18F2x23C_dct0_Reserved_7_4_WIDTH                       4
#define D18F2x23C_dct0_Reserved_7_4_MASK                        0xf0
#define D18F2x23C_dct0_WrOdtPatCs51_OFFSET                      8
#define D18F2x23C_dct0_WrOdtPatCs51_WIDTH                       4
#define D18F2x23C_dct0_WrOdtPatCs51_MASK                        0xf00
#define D18F2x23C_dct0_Reserved_15_12_OFFSET                    12
#define D18F2x23C_dct0_Reserved_15_12_WIDTH                     4
#define D18F2x23C_dct0_Reserved_15_12_MASK                      0xf000
#define D18F2x23C_dct0_WrOdtPatCs62_OFFSET                      16
#define D18F2x23C_dct0_WrOdtPatCs62_WIDTH                       4
#define D18F2x23C_dct0_WrOdtPatCs62_MASK                        0xf0000
#define D18F2x23C_dct0_Reserved_23_20_OFFSET                    20
#define D18F2x23C_dct0_Reserved_23_20_WIDTH                     4
#define D18F2x23C_dct0_Reserved_23_20_MASK                      0xf00000
#define D18F2x23C_dct0_WrOdtPatCs73_OFFSET                      24
#define D18F2x23C_dct0_WrOdtPatCs73_WIDTH                       4
#define D18F2x23C_dct0_WrOdtPatCs73_MASK                        0xf000000
#define D18F2x23C_dct0_Reserved_31_28_OFFSET                    28
#define D18F2x23C_dct0_Reserved_31_28_WIDTH                     4
#define D18F2x23C_dct0_Reserved_31_28_MASK                      0xf0000000

/// D18F2x23C_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrOdtPatCs40:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                             WrOdtPatCs51:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                             WrOdtPatCs62:4 ; ///<
    UINT32                                           Reserved_23_20:4 ; ///<
    UINT32                                             WrOdtPatCs73:4 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x23C_dct0_STRUCT;

// **** D18F2x23C_dct1 Register Definition ****
// Address
#define D18F2x23C_dct1_ADDRESS                                  0x23c

// Type
#define D18F2x23C_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x23C_dct1_WrOdtPatCs40_OFFSET                      0
#define D18F2x23C_dct1_WrOdtPatCs40_WIDTH                       4
#define D18F2x23C_dct1_WrOdtPatCs40_MASK                        0xf
#define D18F2x23C_dct1_Reserved_7_4_OFFSET                      4
#define D18F2x23C_dct1_Reserved_7_4_WIDTH                       4
#define D18F2x23C_dct1_Reserved_7_4_MASK                        0xf0
#define D18F2x23C_dct1_WrOdtPatCs51_OFFSET                      8
#define D18F2x23C_dct1_WrOdtPatCs51_WIDTH                       4
#define D18F2x23C_dct1_WrOdtPatCs51_MASK                        0xf00
#define D18F2x23C_dct1_Reserved_15_12_OFFSET                    12
#define D18F2x23C_dct1_Reserved_15_12_WIDTH                     4
#define D18F2x23C_dct1_Reserved_15_12_MASK                      0xf000
#define D18F2x23C_dct1_WrOdtPatCs62_OFFSET                      16
#define D18F2x23C_dct1_WrOdtPatCs62_WIDTH                       4
#define D18F2x23C_dct1_WrOdtPatCs62_MASK                        0xf0000
#define D18F2x23C_dct1_Reserved_23_20_OFFSET                    20
#define D18F2x23C_dct1_Reserved_23_20_WIDTH                     4
#define D18F2x23C_dct1_Reserved_23_20_MASK                      0xf00000
#define D18F2x23C_dct1_WrOdtPatCs73_OFFSET                      24
#define D18F2x23C_dct1_WrOdtPatCs73_WIDTH                       4
#define D18F2x23C_dct1_WrOdtPatCs73_MASK                        0xf000000
#define D18F2x23C_dct1_Reserved_31_28_OFFSET                    28
#define D18F2x23C_dct1_Reserved_31_28_WIDTH                     4
#define D18F2x23C_dct1_Reserved_31_28_MASK                      0xf0000000

/// D18F2x23C_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrOdtPatCs40:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                             WrOdtPatCs51:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                             WrOdtPatCs62:4 ; ///<
    UINT32                                           Reserved_23_20:4 ; ///<
    UINT32                                             WrOdtPatCs73:4 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x23C_dct1_STRUCT;

// **** D18F2x240_dct0_mp1 Register Definition ****
// Address
#define D18F2x240_dct0_mp1_ADDRESS                              0x240

// Type
#define D18F2x240_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
// Field Data
#define D18F2x240_dct0_mp1_RdOdtTrnOnDly_OFFSET                 0
#define D18F2x240_dct0_mp1_RdOdtTrnOnDly_WIDTH                  4
#define D18F2x240_dct0_mp1_RdOdtTrnOnDly_MASK                   0xf
#define D18F2x240_dct0_mp1_RdOdtOnDuration_OFFSET               4
#define D18F2x240_dct0_mp1_RdOdtOnDuration_WIDTH                3
#define D18F2x240_dct0_mp1_RdOdtOnDuration_MASK                 0x70
#define D18F2x240_dct0_mp1_Reserved_7_7_OFFSET                  7
#define D18F2x240_dct0_mp1_Reserved_7_7_WIDTH                   1
#define D18F2x240_dct0_mp1_Reserved_7_7_MASK                    0x80
#define D18F2x240_dct0_mp1_WrOdtTrnOnDly_OFFSET                 8
#define D18F2x240_dct0_mp1_WrOdtTrnOnDly_WIDTH                  3
#define D18F2x240_dct0_mp1_WrOdtTrnOnDly_MASK                   0x700
#define D18F2x240_dct0_mp1_Reserved_11_11_OFFSET                11
#define D18F2x240_dct0_mp1_Reserved_11_11_WIDTH                 1
#define D18F2x240_dct0_mp1_Reserved_11_11_MASK                  0x800
#define D18F2x240_dct0_mp1_WrOdtOnDuration_OFFSET               12
#define D18F2x240_dct0_mp1_WrOdtOnDuration_WIDTH                3
#define D18F2x240_dct0_mp1_WrOdtOnDuration_MASK                 0x7000
#define D18F2x240_dct0_mp1_Reserved_31_15_OFFSET                15
#define D18F2x240_dct0_mp1_Reserved_31_15_WIDTH                 17
#define D18F2x240_dct0_mp1_Reserved_31_15_MASK                  0xffff8000

/// D18F2x240_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                            RdOdtTrnOnDly:4 ; ///<
    UINT32                                          RdOdtOnDuration:3 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                            WrOdtTrnOnDly:3 ; ///<
    UINT32                                           Reserved_11_11:1 ; ///<
    UINT32                                          WrOdtOnDuration:3 ; ///<
    UINT32                                           Reserved_31_15:17; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x240_dct0_mp1_STRUCT;

// **** D18F2x240_dct1_mp0 Register Definition ****
// Address
#define D18F2x240_dct1_mp0_ADDRESS                              0x240

// Type
#define D18F2x240_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
// Field Data
#define D18F2x240_dct1_mp0_RdOdtTrnOnDly_OFFSET                 0
#define D18F2x240_dct1_mp0_RdOdtTrnOnDly_WIDTH                  4
#define D18F2x240_dct1_mp0_RdOdtTrnOnDly_MASK                   0xf
#define D18F2x240_dct1_mp0_RdOdtOnDuration_OFFSET               4
#define D18F2x240_dct1_mp0_RdOdtOnDuration_WIDTH                3
#define D18F2x240_dct1_mp0_RdOdtOnDuration_MASK                 0x70
#define D18F2x240_dct1_mp0_Reserved_7_7_OFFSET                  7
#define D18F2x240_dct1_mp0_Reserved_7_7_WIDTH                   1
#define D18F2x240_dct1_mp0_Reserved_7_7_MASK                    0x80
#define D18F2x240_dct1_mp0_WrOdtTrnOnDly_OFFSET                 8
#define D18F2x240_dct1_mp0_WrOdtTrnOnDly_WIDTH                  3
#define D18F2x240_dct1_mp0_WrOdtTrnOnDly_MASK                   0x700
#define D18F2x240_dct1_mp0_Reserved_11_11_OFFSET                11
#define D18F2x240_dct1_mp0_Reserved_11_11_WIDTH                 1
#define D18F2x240_dct1_mp0_Reserved_11_11_MASK                  0x800
#define D18F2x240_dct1_mp0_WrOdtOnDuration_OFFSET               12
#define D18F2x240_dct1_mp0_WrOdtOnDuration_WIDTH                3
#define D18F2x240_dct1_mp0_WrOdtOnDuration_MASK                 0x7000
#define D18F2x240_dct1_mp0_Reserved_31_15_OFFSET                15
#define D18F2x240_dct1_mp0_Reserved_31_15_WIDTH                 17
#define D18F2x240_dct1_mp0_Reserved_31_15_MASK                  0xffff8000

/// D18F2x240_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                            RdOdtTrnOnDly:4 ; ///<
    UINT32                                          RdOdtOnDuration:3 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                            WrOdtTrnOnDly:3 ; ///<
    UINT32                                           Reserved_11_11:1 ; ///<
    UINT32                                          WrOdtOnDuration:3 ; ///<
    UINT32                                           Reserved_31_15:17; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x240_dct1_mp0_STRUCT;

// **** D18F2x240_dct0_mp0 Register Definition ****
// Address
#define D18F2x240_dct0_mp0_ADDRESS                              0x240

// Type
#define D18F2x240_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
// Field Data
#define D18F2x240_dct0_mp0_RdOdtTrnOnDly_OFFSET                 0
#define D18F2x240_dct0_mp0_RdOdtTrnOnDly_WIDTH                  4
#define D18F2x240_dct0_mp0_RdOdtTrnOnDly_MASK                   0xf
#define D18F2x240_dct0_mp0_RdOdtOnDuration_OFFSET               4
#define D18F2x240_dct0_mp0_RdOdtOnDuration_WIDTH                3
#define D18F2x240_dct0_mp0_RdOdtOnDuration_MASK                 0x70
#define D18F2x240_dct0_mp0_Reserved_7_7_OFFSET                  7
#define D18F2x240_dct0_mp0_Reserved_7_7_WIDTH                   1
#define D18F2x240_dct0_mp0_Reserved_7_7_MASK                    0x80
#define D18F2x240_dct0_mp0_WrOdtTrnOnDly_OFFSET                 8
#define D18F2x240_dct0_mp0_WrOdtTrnOnDly_WIDTH                  3
#define D18F2x240_dct0_mp0_WrOdtTrnOnDly_MASK                   0x700
#define D18F2x240_dct0_mp0_Reserved_11_11_OFFSET                11
#define D18F2x240_dct0_mp0_Reserved_11_11_WIDTH                 1
#define D18F2x240_dct0_mp0_Reserved_11_11_MASK                  0x800
#define D18F2x240_dct0_mp0_WrOdtOnDuration_OFFSET               12
#define D18F2x240_dct0_mp0_WrOdtOnDuration_WIDTH                3
#define D18F2x240_dct0_mp0_WrOdtOnDuration_MASK                 0x7000
#define D18F2x240_dct0_mp0_Reserved_31_15_OFFSET                15
#define D18F2x240_dct0_mp0_Reserved_31_15_WIDTH                 17
#define D18F2x240_dct0_mp0_Reserved_31_15_MASK                  0xffff8000

/// D18F2x240_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                            RdOdtTrnOnDly:4 ; ///<
    UINT32                                          RdOdtOnDuration:3 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                            WrOdtTrnOnDly:3 ; ///<
    UINT32                                           Reserved_11_11:1 ; ///<
    UINT32                                          WrOdtOnDuration:3 ; ///<
    UINT32                                           Reserved_31_15:17; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x240_dct0_mp0_STRUCT;

// **** D18F2x240_dct1_mp1 Register Definition ****
// Address
#define D18F2x240_dct1_mp1_ADDRESS                              0x240

// Type
#define D18F2x240_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
// Field Data
#define D18F2x240_dct1_mp1_RdOdtTrnOnDly_OFFSET                 0
#define D18F2x240_dct1_mp1_RdOdtTrnOnDly_WIDTH                  4
#define D18F2x240_dct1_mp1_RdOdtTrnOnDly_MASK                   0xf
#define D18F2x240_dct1_mp1_RdOdtOnDuration_OFFSET               4
#define D18F2x240_dct1_mp1_RdOdtOnDuration_WIDTH                3
#define D18F2x240_dct1_mp1_RdOdtOnDuration_MASK                 0x70
#define D18F2x240_dct1_mp1_Reserved_7_7_OFFSET                  7
#define D18F2x240_dct1_mp1_Reserved_7_7_WIDTH                   1
#define D18F2x240_dct1_mp1_Reserved_7_7_MASK                    0x80
#define D18F2x240_dct1_mp1_WrOdtTrnOnDly_OFFSET                 8
#define D18F2x240_dct1_mp1_WrOdtTrnOnDly_WIDTH                  3
#define D18F2x240_dct1_mp1_WrOdtTrnOnDly_MASK                   0x700
#define D18F2x240_dct1_mp1_Reserved_11_11_OFFSET                11
#define D18F2x240_dct1_mp1_Reserved_11_11_WIDTH                 1
#define D18F2x240_dct1_mp1_Reserved_11_11_MASK                  0x800
#define D18F2x240_dct1_mp1_WrOdtOnDuration_OFFSET               12
#define D18F2x240_dct1_mp1_WrOdtOnDuration_WIDTH                3
#define D18F2x240_dct1_mp1_WrOdtOnDuration_MASK                 0x7000
#define D18F2x240_dct1_mp1_Reserved_31_15_OFFSET                15
#define D18F2x240_dct1_mp1_Reserved_31_15_WIDTH                 17
#define D18F2x240_dct1_mp1_Reserved_31_15_MASK                  0xffff8000

/// D18F2x240_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                            RdOdtTrnOnDly:4 ; ///<
    UINT32                                          RdOdtOnDuration:3 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                            WrOdtTrnOnDly:3 ; ///<
    UINT32                                           Reserved_11_11:1 ; ///<
    UINT32                                          WrOdtOnDuration:3 ; ///<
    UINT32                                           Reserved_31_15:17; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x240_dct1_mp1_STRUCT;

// **** D18F2x244_dct1 Register Definition ****
// Address
#define D18F2x244_dct1_ADDRESS                                  0x244

// Type
#define D18F2x244_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x244_dct1_PrtlChPDDynDly_OFFSET                    0
#define D18F2x244_dct1_PrtlChPDDynDly_WIDTH                     4
#define D18F2x244_dct1_PrtlChPDDynDly_MASK                      0xf
#define D18F2x244_dct1_Reserved_31_4_OFFSET                     4
#define D18F2x244_dct1_Reserved_31_4_WIDTH                      28
#define D18F2x244_dct1_Reserved_31_4_MASK                       0xfffffff0

/// D18F2x244_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                           PrtlChPDDynDly:4 ; ///<
    UINT32                                            Reserved_31_4:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x244_dct1_STRUCT;

// **** D18F2x244_dct0 Register Definition ****
// Address
#define D18F2x244_dct0_ADDRESS                                  0x244

// Type
#define D18F2x244_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x244_dct0_PrtlChPDDynDly_OFFSET                    0
#define D18F2x244_dct0_PrtlChPDDynDly_WIDTH                     4
#define D18F2x244_dct0_PrtlChPDDynDly_MASK                      0xf
#define D18F2x244_dct0_Reserved_31_4_OFFSET                     4
#define D18F2x244_dct0_Reserved_31_4_WIDTH                      28
#define D18F2x244_dct0_Reserved_31_4_MASK                       0xfffffff0

/// D18F2x244_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                           PrtlChPDDynDly:4 ; ///<
    UINT32                                            Reserved_31_4:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x244_dct0_STRUCT;

// **** D18F2x248_dct1_mp1 Register Definition ****
// Address
#define D18F2x248_dct1_mp1_ADDRESS                              0x248

// Type
#define D18F2x248_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
// Field Data
#define D18F2x248_dct1_mp1_Txp_OFFSET                           0
#define D18F2x248_dct1_mp1_Txp_WIDTH                            4
#define D18F2x248_dct1_mp1_Txp_MASK                             0xf
#define D18F2x248_dct1_mp1_Reserved_7_4_OFFSET                  4
#define D18F2x248_dct1_mp1_Reserved_7_4_WIDTH                   4
#define D18F2x248_dct1_mp1_Reserved_7_4_MASK                    0xf0
#define D18F2x248_dct1_mp1_Txpdll_OFFSET                        8
#define D18F2x248_dct1_mp1_Txpdll_WIDTH                         5
#define D18F2x248_dct1_mp1_Txpdll_MASK                          0x1f00
#define D18F2x248_dct1_mp1_Reserved_15_13_OFFSET                13
#define D18F2x248_dct1_mp1_Reserved_15_13_WIDTH                 3
#define D18F2x248_dct1_mp1_Reserved_15_13_MASK                  0xe000
#define D18F2x248_dct1_mp1_PchgPDEnDelay_OFFSET                 16
#define D18F2x248_dct1_mp1_PchgPDEnDelay_WIDTH                  6
#define D18F2x248_dct1_mp1_PchgPDEnDelay_MASK                   0x3f0000
#define D18F2x248_dct1_mp1_Reserved_23_22_OFFSET                22
#define D18F2x248_dct1_mp1_Reserved_23_22_WIDTH                 2
#define D18F2x248_dct1_mp1_Reserved_23_22_MASK                  0xc00000
#define D18F2x248_dct1_mp1_AggrPDDelay_OFFSET                   24
#define D18F2x248_dct1_mp1_AggrPDDelay_WIDTH                    6
#define D18F2x248_dct1_mp1_AggrPDDelay_MASK                     0x3f000000
#define D18F2x248_dct1_mp1_Reserved_30_30_OFFSET                30
#define D18F2x248_dct1_mp1_Reserved_30_30_WIDTH                 1
#define D18F2x248_dct1_mp1_Reserved_30_30_MASK                  0x40000000
#define D18F2x248_dct1_mp1_RxChMntClkEn_OFFSET                  31
#define D18F2x248_dct1_mp1_RxChMntClkEn_WIDTH                   1
#define D18F2x248_dct1_mp1_RxChMntClkEn_MASK                    0x80000000

/// D18F2x248_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                      Txp:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                   Txpdll:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            PchgPDEnDelay:6 ; ///<
    UINT32                                           Reserved_23_22:2 ; ///<
    UINT32                                              AggrPDDelay:6 ; ///<
    UINT32                                           Reserved_30_30:1 ; ///<
    UINT32                                             RxChMntClkEn:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x248_dct1_mp1_STRUCT;

// **** D18F2x248_dct0_mp1 Register Definition ****
// Address
#define D18F2x248_dct0_mp1_ADDRESS                              0x248

// Type
#define D18F2x248_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
// Field Data
#define D18F2x248_dct0_mp1_Txp_OFFSET                           0
#define D18F2x248_dct0_mp1_Txp_WIDTH                            4
#define D18F2x248_dct0_mp1_Txp_MASK                             0xf
#define D18F2x248_dct0_mp1_Reserved_7_4_OFFSET                  4
#define D18F2x248_dct0_mp1_Reserved_7_4_WIDTH                   4
#define D18F2x248_dct0_mp1_Reserved_7_4_MASK                    0xf0
#define D18F2x248_dct0_mp1_Txpdll_OFFSET                        8
#define D18F2x248_dct0_mp1_Txpdll_WIDTH                         5
#define D18F2x248_dct0_mp1_Txpdll_MASK                          0x1f00
#define D18F2x248_dct0_mp1_Reserved_15_13_OFFSET                13
#define D18F2x248_dct0_mp1_Reserved_15_13_WIDTH                 3
#define D18F2x248_dct0_mp1_Reserved_15_13_MASK                  0xe000
#define D18F2x248_dct0_mp1_PchgPDEnDelay_OFFSET                 16
#define D18F2x248_dct0_mp1_PchgPDEnDelay_WIDTH                  6
#define D18F2x248_dct0_mp1_PchgPDEnDelay_MASK                   0x3f0000
#define D18F2x248_dct0_mp1_Reserved_23_22_OFFSET                22
#define D18F2x248_dct0_mp1_Reserved_23_22_WIDTH                 2
#define D18F2x248_dct0_mp1_Reserved_23_22_MASK                  0xc00000
#define D18F2x248_dct0_mp1_AggrPDDelay_OFFSET                   24
#define D18F2x248_dct0_mp1_AggrPDDelay_WIDTH                    6
#define D18F2x248_dct0_mp1_AggrPDDelay_MASK                     0x3f000000
#define D18F2x248_dct0_mp1_Reserved_30_30_OFFSET                30
#define D18F2x248_dct0_mp1_Reserved_30_30_WIDTH                 1
#define D18F2x248_dct0_mp1_Reserved_30_30_MASK                  0x40000000
#define D18F2x248_dct0_mp1_RxChMntClkEn_OFFSET                  31
#define D18F2x248_dct0_mp1_RxChMntClkEn_WIDTH                   1
#define D18F2x248_dct0_mp1_RxChMntClkEn_MASK                    0x80000000

/// D18F2x248_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                      Txp:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                   Txpdll:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            PchgPDEnDelay:6 ; ///<
    UINT32                                           Reserved_23_22:2 ; ///<
    UINT32                                              AggrPDDelay:6 ; ///<
    UINT32                                           Reserved_30_30:1 ; ///<
    UINT32                                             RxChMntClkEn:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x248_dct0_mp1_STRUCT;

// **** D18F2x248_dct1_mp0 Register Definition ****
// Address
#define D18F2x248_dct1_mp0_ADDRESS                              0x248

// Type
#define D18F2x248_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
// Field Data
#define D18F2x248_dct1_mp0_Txp_OFFSET                           0
#define D18F2x248_dct1_mp0_Txp_WIDTH                            4
#define D18F2x248_dct1_mp0_Txp_MASK                             0xf
#define D18F2x248_dct1_mp0_Reserved_7_4_OFFSET                  4
#define D18F2x248_dct1_mp0_Reserved_7_4_WIDTH                   4
#define D18F2x248_dct1_mp0_Reserved_7_4_MASK                    0xf0
#define D18F2x248_dct1_mp0_Txpdll_OFFSET                        8
#define D18F2x248_dct1_mp0_Txpdll_WIDTH                         5
#define D18F2x248_dct1_mp0_Txpdll_MASK                          0x1f00
#define D18F2x248_dct1_mp0_Reserved_15_13_OFFSET                13
#define D18F2x248_dct1_mp0_Reserved_15_13_WIDTH                 3
#define D18F2x248_dct1_mp0_Reserved_15_13_MASK                  0xe000
#define D18F2x248_dct1_mp0_PchgPDEnDelay_OFFSET                 16
#define D18F2x248_dct1_mp0_PchgPDEnDelay_WIDTH                  6
#define D18F2x248_dct1_mp0_PchgPDEnDelay_MASK                   0x3f0000
#define D18F2x248_dct1_mp0_Reserved_23_22_OFFSET                22
#define D18F2x248_dct1_mp0_Reserved_23_22_WIDTH                 2
#define D18F2x248_dct1_mp0_Reserved_23_22_MASK                  0xc00000
#define D18F2x248_dct1_mp0_AggrPDDelay_OFFSET                   24
#define D18F2x248_dct1_mp0_AggrPDDelay_WIDTH                    6
#define D18F2x248_dct1_mp0_AggrPDDelay_MASK                     0x3f000000
#define D18F2x248_dct1_mp0_Reserved_30_30_OFFSET                30
#define D18F2x248_dct1_mp0_Reserved_30_30_WIDTH                 1
#define D18F2x248_dct1_mp0_Reserved_30_30_MASK                  0x40000000
#define D18F2x248_dct1_mp0_RxChMntClkEn_OFFSET                  31
#define D18F2x248_dct1_mp0_RxChMntClkEn_WIDTH                   1
#define D18F2x248_dct1_mp0_RxChMntClkEn_MASK                    0x80000000

/// D18F2x248_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                      Txp:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                   Txpdll:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            PchgPDEnDelay:6 ; ///<
    UINT32                                           Reserved_23_22:2 ; ///<
    UINT32                                              AggrPDDelay:6 ; ///<
    UINT32                                           Reserved_30_30:1 ; ///<
    UINT32                                             RxChMntClkEn:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x248_dct1_mp0_STRUCT;

// **** D18F2x248_dct0_mp0 Register Definition ****
// Address
#define D18F2x248_dct0_mp0_ADDRESS                              0x248

// Type
#define D18F2x248_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
// Field Data
#define D18F2x248_dct0_mp0_Txp_OFFSET                           0
#define D18F2x248_dct0_mp0_Txp_WIDTH                            4
#define D18F2x248_dct0_mp0_Txp_MASK                             0xf
#define D18F2x248_dct0_mp0_Reserved_7_4_OFFSET                  4
#define D18F2x248_dct0_mp0_Reserved_7_4_WIDTH                   4
#define D18F2x248_dct0_mp0_Reserved_7_4_MASK                    0xf0
#define D18F2x248_dct0_mp0_Txpdll_OFFSET                        8
#define D18F2x248_dct0_mp0_Txpdll_WIDTH                         5
#define D18F2x248_dct0_mp0_Txpdll_MASK                          0x1f00
#define D18F2x248_dct0_mp0_Reserved_15_13_OFFSET                13
#define D18F2x248_dct0_mp0_Reserved_15_13_WIDTH                 3
#define D18F2x248_dct0_mp0_Reserved_15_13_MASK                  0xe000
#define D18F2x248_dct0_mp0_PchgPDEnDelay_OFFSET                 16
#define D18F2x248_dct0_mp0_PchgPDEnDelay_WIDTH                  6
#define D18F2x248_dct0_mp0_PchgPDEnDelay_MASK                   0x3f0000
#define D18F2x248_dct0_mp0_Reserved_23_22_OFFSET                22
#define D18F2x248_dct0_mp0_Reserved_23_22_WIDTH                 2
#define D18F2x248_dct0_mp0_Reserved_23_22_MASK                  0xc00000
#define D18F2x248_dct0_mp0_AggrPDDelay_OFFSET                   24
#define D18F2x248_dct0_mp0_AggrPDDelay_WIDTH                    6
#define D18F2x248_dct0_mp0_AggrPDDelay_MASK                     0x3f000000
#define D18F2x248_dct0_mp0_Reserved_30_30_OFFSET                30
#define D18F2x248_dct0_mp0_Reserved_30_30_WIDTH                 1
#define D18F2x248_dct0_mp0_Reserved_30_30_MASK                  0x40000000
#define D18F2x248_dct0_mp0_RxChMntClkEn_OFFSET                  31
#define D18F2x248_dct0_mp0_RxChMntClkEn_WIDTH                   1
#define D18F2x248_dct0_mp0_RxChMntClkEn_MASK                    0x80000000

/// D18F2x248_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                      Txp:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                   Txpdll:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            PchgPDEnDelay:6 ; ///<
    UINT32                                           Reserved_23_22:2 ; ///<
    UINT32                                              AggrPDDelay:6 ; ///<
    UINT32                                           Reserved_30_30:1 ; ///<
    UINT32                                             RxChMntClkEn:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x248_dct0_mp0_STRUCT;

// **** D18F2x24C_dct0 Register Definition ****
// Address
#define D18F2x24C_dct0_ADDRESS                                  0x24c

// Type
#define D18F2x24C_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x24C_dct0_Tpd_OFFSET                               0
#define D18F2x24C_dct0_Tpd_WIDTH                                4
#define D18F2x24C_dct0_Tpd_MASK                                 0xf
#define D18F2x24C_dct0_Reserved_7_4_OFFSET                      4
#define D18F2x24C_dct0_Reserved_7_4_WIDTH                       4
#define D18F2x24C_dct0_Reserved_7_4_MASK                        0xf0
#define D18F2x24C_dct0_Tckesr_OFFSET                            8
#define D18F2x24C_dct0_Tckesr_WIDTH                             6
#define D18F2x24C_dct0_Tckesr_MASK                              0x3f00
#define D18F2x24C_dct0_Reserved_15_14_OFFSET                    14
#define D18F2x24C_dct0_Reserved_15_14_WIDTH                     2
#define D18F2x24C_dct0_Reserved_15_14_MASK                      0xc000
#define D18F2x24C_dct0_Tcksre_OFFSET                            16
#define D18F2x24C_dct0_Tcksre_WIDTH                             6
#define D18F2x24C_dct0_Tcksre_MASK                              0x3f0000
#define D18F2x24C_dct0_Reserved_23_22_OFFSET                    22
#define D18F2x24C_dct0_Reserved_23_22_WIDTH                     2
#define D18F2x24C_dct0_Reserved_23_22_MASK                      0xc00000
#define D18F2x24C_dct0_Tcksrx_OFFSET                            24
#define D18F2x24C_dct0_Tcksrx_WIDTH                             6
#define D18F2x24C_dct0_Tcksrx_MASK                              0x3f000000
#define D18F2x24C_dct0_Reserved_31_30_OFFSET                    30
#define D18F2x24C_dct0_Reserved_31_30_WIDTH                     2
#define D18F2x24C_dct0_Reserved_31_30_MASK                      0xc0000000

/// D18F2x24C_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                      Tpd:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                   Tckesr:6 ; ///<
    UINT32                                           Reserved_15_14:2 ; ///<
    UINT32                                                   Tcksre:6 ; ///<
    UINT32                                           Reserved_23_22:2 ; ///<
    UINT32                                                   Tcksrx:6 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x24C_dct0_STRUCT;

// **** D18F2x24C_dct1 Register Definition ****
// Address
#define D18F2x24C_dct1_ADDRESS                                  0x24c

// Type
#define D18F2x24C_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x24C_dct1_Tpd_OFFSET                               0
#define D18F2x24C_dct1_Tpd_WIDTH                                4
#define D18F2x24C_dct1_Tpd_MASK                                 0xf
#define D18F2x24C_dct1_Reserved_7_4_OFFSET                      4
#define D18F2x24C_dct1_Reserved_7_4_WIDTH                       4
#define D18F2x24C_dct1_Reserved_7_4_MASK                        0xf0
#define D18F2x24C_dct1_Tckesr_OFFSET                            8
#define D18F2x24C_dct1_Tckesr_WIDTH                             6
#define D18F2x24C_dct1_Tckesr_MASK                              0x3f00
#define D18F2x24C_dct1_Reserved_15_14_OFFSET                    14
#define D18F2x24C_dct1_Reserved_15_14_WIDTH                     2
#define D18F2x24C_dct1_Reserved_15_14_MASK                      0xc000
#define D18F2x24C_dct1_Tcksre_OFFSET                            16
#define D18F2x24C_dct1_Tcksre_WIDTH                             6
#define D18F2x24C_dct1_Tcksre_MASK                              0x3f0000
#define D18F2x24C_dct1_Reserved_23_22_OFFSET                    22
#define D18F2x24C_dct1_Reserved_23_22_WIDTH                     2
#define D18F2x24C_dct1_Reserved_23_22_MASK                      0xc00000
#define D18F2x24C_dct1_Tcksrx_OFFSET                            24
#define D18F2x24C_dct1_Tcksrx_WIDTH                             6
#define D18F2x24C_dct1_Tcksrx_MASK                              0x3f000000
#define D18F2x24C_dct1_Reserved_31_30_OFFSET                    30
#define D18F2x24C_dct1_Reserved_31_30_WIDTH                     2
#define D18F2x24C_dct1_Reserved_31_30_MASK                      0xc0000000

/// D18F2x24C_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                      Tpd:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                   Tckesr:6 ; ///<
    UINT32                                           Reserved_15_14:2 ; ///<
    UINT32                                                   Tcksre:6 ; ///<
    UINT32                                           Reserved_23_22:2 ; ///<
    UINT32                                                   Tcksrx:6 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x24C_dct1_STRUCT;

// **** D18F2x250_dct0 Register Definition ****
// Address
#define D18F2x250_dct0_ADDRESS                                  0x250

// Type
#define D18F2x250_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x250_dct0_Reserved_1_0_OFFSET                      0
#define D18F2x250_dct0_Reserved_1_0_WIDTH                       2
#define D18F2x250_dct0_Reserved_1_0_MASK                        0x3
#define D18F2x250_dct0_CmdTestEnable_OFFSET                     2
#define D18F2x250_dct0_CmdTestEnable_WIDTH                      1
#define D18F2x250_dct0_CmdTestEnable_MASK                       0x4
#define D18F2x250_dct0_ResetAllErr_OFFSET                       3
#define D18F2x250_dct0_ResetAllErr_WIDTH                        1
#define D18F2x250_dct0_ResetAllErr_MASK                         0x8
#define D18F2x250_dct0_StopOnErr_OFFSET                         4
#define D18F2x250_dct0_StopOnErr_WIDTH                          1
#define D18F2x250_dct0_StopOnErr_MASK                           0x10
#define D18F2x250_dct0_CmdType_OFFSET                           5
#define D18F2x250_dct0_CmdType_WIDTH                            3
#define D18F2x250_dct0_CmdType_MASK                             0xe0
#define D18F2x250_dct0_CmdTgt_OFFSET                            8
#define D18F2x250_dct0_CmdTgt_WIDTH                             2
#define D18F2x250_dct0_CmdTgt_MASK                              0x300
#define D18F2x250_dct0_TestStatus_OFFSET                        10
#define D18F2x250_dct0_TestStatus_WIDTH                         1
#define D18F2x250_dct0_TestStatus_MASK                          0x400
#define D18F2x250_dct0_SendCmd_OFFSET                           11
#define D18F2x250_dct0_SendCmd_WIDTH                            1
#define D18F2x250_dct0_SendCmd_MASK                             0x800
#define D18F2x250_dct0_CmdSendInProg_OFFSET                     12
#define D18F2x250_dct0_CmdSendInProg_WIDTH                      1
#define D18F2x250_dct0_CmdSendInProg_MASK                       0x1000
#define D18F2x250_dct0_Reserved_31_13_OFFSET                    13
#define D18F2x250_dct0_Reserved_31_13_WIDTH                     19
#define D18F2x250_dct0_Reserved_31_13_MASK                      0xffffe000

/// D18F2x250_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_1_0:2 ; ///<
    UINT32                                            CmdTestEnable:1 ; ///<
    UINT32                                              ResetAllErr:1 ; ///<
    UINT32                                                StopOnErr:1 ; ///<
    UINT32                                                  CmdType:3 ; ///<
    UINT32                                                   CmdTgt:2 ; ///<
    UINT32                                               TestStatus:1 ; ///<
    UINT32                                                  SendCmd:1 ; ///<
    UINT32                                            CmdSendInProg:1 ; ///<
    UINT32                                           Reserved_31_13:19; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x250_dct0_STRUCT;

// **** D18F2x250_dct1 Register Definition ****
// Address
#define D18F2x250_dct1_ADDRESS                                  0x250

// Type
#define D18F2x250_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x250_dct1_Reserved_1_0_OFFSET                      0
#define D18F2x250_dct1_Reserved_1_0_WIDTH                       2
#define D18F2x250_dct1_Reserved_1_0_MASK                        0x3
#define D18F2x250_dct1_CmdTestEnable_OFFSET                     2
#define D18F2x250_dct1_CmdTestEnable_WIDTH                      1
#define D18F2x250_dct1_CmdTestEnable_MASK                       0x4
#define D18F2x250_dct1_ResetAllErr_OFFSET                       3
#define D18F2x250_dct1_ResetAllErr_WIDTH                        1
#define D18F2x250_dct1_ResetAllErr_MASK                         0x8
#define D18F2x250_dct1_StopOnErr_OFFSET                         4
#define D18F2x250_dct1_StopOnErr_WIDTH                          1
#define D18F2x250_dct1_StopOnErr_MASK                           0x10
#define D18F2x250_dct1_CmdType_OFFSET                           5
#define D18F2x250_dct1_CmdType_WIDTH                            3
#define D18F2x250_dct1_CmdType_MASK                             0xe0
#define D18F2x250_dct1_CmdTgt_OFFSET                            8
#define D18F2x250_dct1_CmdTgt_WIDTH                             2
#define D18F2x250_dct1_CmdTgt_MASK                              0x300
#define D18F2x250_dct1_TestStatus_OFFSET                        10
#define D18F2x250_dct1_TestStatus_WIDTH                         1
#define D18F2x250_dct1_TestStatus_MASK                          0x400
#define D18F2x250_dct1_SendCmd_OFFSET                           11
#define D18F2x250_dct1_SendCmd_WIDTH                            1
#define D18F2x250_dct1_SendCmd_MASK                             0x800
#define D18F2x250_dct1_CmdSendInProg_OFFSET                     12
#define D18F2x250_dct1_CmdSendInProg_WIDTH                      1
#define D18F2x250_dct1_CmdSendInProg_MASK                       0x1000
#define D18F2x250_dct1_Reserved_31_13_OFFSET                    13
#define D18F2x250_dct1_Reserved_31_13_WIDTH                     19
#define D18F2x250_dct1_Reserved_31_13_MASK                      0xffffe000

/// D18F2x250_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_1_0:2 ; ///<
    UINT32                                            CmdTestEnable:1 ; ///<
    UINT32                                              ResetAllErr:1 ; ///<
    UINT32                                                StopOnErr:1 ; ///<
    UINT32                                                  CmdType:3 ; ///<
    UINT32                                                   CmdTgt:2 ; ///<
    UINT32                                               TestStatus:1 ; ///<
    UINT32                                                  SendCmd:1 ; ///<
    UINT32                                            CmdSendInProg:1 ; ///<
    UINT32                                           Reserved_31_13:19; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x250_dct1_STRUCT;

// **** D18F2x254_dct0 Register Definition ****
// Address
#define D18F2x254_dct0_ADDRESS                                  0x254

// Type
#define D18F2x254_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x254_dct0_TgtAddress_9_0__OFFSET                   0
#define D18F2x254_dct0_TgtAddress_9_0__WIDTH                    10
#define D18F2x254_dct0_TgtAddress_9_0__MASK                     0x3ff
#define D18F2x254_dct0_Reserved_20_10_OFFSET                    10
#define D18F2x254_dct0_Reserved_20_10_WIDTH                     11
#define D18F2x254_dct0_Reserved_20_10_MASK                      0x1ffc00
#define D18F2x254_dct0_TgtBank_OFFSET                           21
#define D18F2x254_dct0_TgtBank_WIDTH                            3
#define D18F2x254_dct0_TgtBank_MASK                             0xe00000
#define D18F2x254_dct0_TgtChipSelect_OFFSET                     24
#define D18F2x254_dct0_TgtChipSelect_WIDTH                      3
#define D18F2x254_dct0_TgtChipSelect_MASK                       0x7000000
#define D18F2x254_dct0_Reserved_31_27_OFFSET                    27
#define D18F2x254_dct0_Reserved_31_27_WIDTH                     5
#define D18F2x254_dct0_Reserved_31_27_MASK                      0xf8000000

/// D18F2x254_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                          TgtAddress_9_0_:10; ///<
    UINT32                                           Reserved_20_10:11; ///<
    UINT32                                                  TgtBank:3 ; ///<
    UINT32                                            TgtChipSelect:3 ; ///<
    UINT32                                           Reserved_31_27:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x254_dct0_STRUCT;

// **** D18F2x254_dct1 Register Definition ****
// Address
#define D18F2x254_dct1_ADDRESS                                  0x254

// Type
#define D18F2x254_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x254_dct1_TgtAddress_9_0__OFFSET                   0
#define D18F2x254_dct1_TgtAddress_9_0__WIDTH                    10
#define D18F2x254_dct1_TgtAddress_9_0__MASK                     0x3ff
#define D18F2x254_dct1_Reserved_20_10_OFFSET                    10
#define D18F2x254_dct1_Reserved_20_10_WIDTH                     11
#define D18F2x254_dct1_Reserved_20_10_MASK                      0x1ffc00
#define D18F2x254_dct1_TgtBank_OFFSET                           21
#define D18F2x254_dct1_TgtBank_WIDTH                            3
#define D18F2x254_dct1_TgtBank_MASK                             0xe00000
#define D18F2x254_dct1_TgtChipSelect_OFFSET                     24
#define D18F2x254_dct1_TgtChipSelect_WIDTH                      3
#define D18F2x254_dct1_TgtChipSelect_MASK                       0x7000000
#define D18F2x254_dct1_Reserved_31_27_OFFSET                    27
#define D18F2x254_dct1_Reserved_31_27_WIDTH                     5
#define D18F2x254_dct1_Reserved_31_27_MASK                      0xf8000000

/// D18F2x254_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                          TgtAddress_9_0_:10; ///<
    UINT32                                           Reserved_20_10:11; ///<
    UINT32                                                  TgtBank:3 ; ///<
    UINT32                                            TgtChipSelect:3 ; ///<
    UINT32                                           Reserved_31_27:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x254_dct1_STRUCT;

// **** D18F2x258_dct0 Register Definition ****
// Address
#define D18F2x258_dct0_ADDRESS                                  0x258

// Type
#define D18F2x258_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x258_dct0_TgtAddress_9_0__OFFSET                   0
#define D18F2x258_dct0_TgtAddress_9_0__WIDTH                    10
#define D18F2x258_dct0_TgtAddress_9_0__MASK                     0x3ff
#define D18F2x258_dct0_Reserved_20_10_OFFSET                    10
#define D18F2x258_dct0_Reserved_20_10_WIDTH                     11
#define D18F2x258_dct0_Reserved_20_10_MASK                      0x1ffc00
#define D18F2x258_dct0_TgtBank_OFFSET                           21
#define D18F2x258_dct0_TgtBank_WIDTH                            3
#define D18F2x258_dct0_TgtBank_MASK                             0xe00000
#define D18F2x258_dct0_TgtChipSelect_OFFSET                     24
#define D18F2x258_dct0_TgtChipSelect_WIDTH                      3
#define D18F2x258_dct0_TgtChipSelect_MASK                       0x7000000
#define D18F2x258_dct0_Reserved_31_27_OFFSET                    27
#define D18F2x258_dct0_Reserved_31_27_WIDTH                     5
#define D18F2x258_dct0_Reserved_31_27_MASK                      0xf8000000

/// D18F2x258_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                          TgtAddress_9_0_:10; ///<
    UINT32                                           Reserved_20_10:11; ///<
    UINT32                                                  TgtBank:3 ; ///<
    UINT32                                            TgtChipSelect:3 ; ///<
    UINT32                                           Reserved_31_27:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x258_dct0_STRUCT;

// **** D18F2x258_dct1 Register Definition ****
// Address
#define D18F2x258_dct1_ADDRESS                                  0x258

// Type
#define D18F2x258_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x258_dct1_TgtAddress_9_0__OFFSET                   0
#define D18F2x258_dct1_TgtAddress_9_0__WIDTH                    10
#define D18F2x258_dct1_TgtAddress_9_0__MASK                     0x3ff
#define D18F2x258_dct1_Reserved_20_10_OFFSET                    10
#define D18F2x258_dct1_Reserved_20_10_WIDTH                     11
#define D18F2x258_dct1_Reserved_20_10_MASK                      0x1ffc00
#define D18F2x258_dct1_TgtBank_OFFSET                           21
#define D18F2x258_dct1_TgtBank_WIDTH                            3
#define D18F2x258_dct1_TgtBank_MASK                             0xe00000
#define D18F2x258_dct1_TgtChipSelect_OFFSET                     24
#define D18F2x258_dct1_TgtChipSelect_WIDTH                      3
#define D18F2x258_dct1_TgtChipSelect_MASK                       0x7000000
#define D18F2x258_dct1_Reserved_31_27_OFFSET                    27
#define D18F2x258_dct1_Reserved_31_27_WIDTH                     5
#define D18F2x258_dct1_Reserved_31_27_MASK                      0xf8000000

/// D18F2x258_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                          TgtAddress_9_0_:10; ///<
    UINT32                                           Reserved_20_10:11; ///<
    UINT32                                                  TgtBank:3 ; ///<
    UINT32                                            TgtChipSelect:3 ; ///<
    UINT32                                           Reserved_31_27:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x258_dct1_STRUCT;


// **** D18F2x260_dct1 Register Definition ****
// Address
#define D18F2x260_dct1_ADDRESS                                  0x260

// Type
#define D18F2x260_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x260_dct1_CmdCount_OFFSET                          0
#define D18F2x260_dct1_CmdCount_WIDTH                           21
#define D18F2x260_dct1_CmdCount_MASK                            0x1fffff
#define D18F2x260_dct1_Reserved_31_21_OFFSET                    21
#define D18F2x260_dct1_Reserved_31_21_WIDTH                     11
#define D18F2x260_dct1_Reserved_31_21_MASK                      0xffe00000

/// D18F2x260_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                 CmdCount:21; ///<
    UINT32                                           Reserved_31_21:11; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x260_dct1_STRUCT;

// **** D18F2x260_dct0 Register Definition ****
// Address
#define D18F2x260_dct0_ADDRESS                                  0x260

// Type
#define D18F2x260_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x260_dct0_CmdCount_OFFSET                          0
#define D18F2x260_dct0_CmdCount_WIDTH                           21
#define D18F2x260_dct0_CmdCount_MASK                            0x1fffff
#define D18F2x260_dct0_Reserved_31_21_OFFSET                    21
#define D18F2x260_dct0_Reserved_31_21_WIDTH                     11
#define D18F2x260_dct0_Reserved_31_21_MASK                      0xffe00000

/// D18F2x260_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                 CmdCount:21; ///<
    UINT32                                           Reserved_31_21:11; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x260_dct0_STRUCT;

// **** D18F2x264_dct1 Register Definition ****
// Address
#define D18F2x264_dct1_ADDRESS                                  0x264

// Type
#define D18F2x264_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x264_dct1_ErrCnt_OFFSET                            0
#define D18F2x264_dct1_ErrCnt_WIDTH                             25
#define D18F2x264_dct1_ErrCnt_MASK                              0x1ffffff
#define D18F2x264_dct1_ErrDqNum_OFFSET                          25
#define D18F2x264_dct1_ErrDqNum_WIDTH                           7
#define D18F2x264_dct1_ErrDqNum_MASK                            0xfe000000

/// D18F2x264_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                   ErrCnt:25; ///<
    UINT32                                                 ErrDqNum:7 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x264_dct1_STRUCT;

// **** D18F2x264_dct0 Register Definition ****
// Address
#define D18F2x264_dct0_ADDRESS                                  0x264

// Type
#define D18F2x264_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x264_dct0_ErrCnt_OFFSET                            0
#define D18F2x264_dct0_ErrCnt_WIDTH                             25
#define D18F2x264_dct0_ErrCnt_MASK                              0x1ffffff
#define D18F2x264_dct0_ErrDqNum_OFFSET                          25
#define D18F2x264_dct0_ErrDqNum_WIDTH                           7
#define D18F2x264_dct0_ErrDqNum_MASK                            0xfe000000

/// D18F2x264_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                   ErrCnt:25; ///<
    UINT32                                                 ErrDqNum:7 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x264_dct0_STRUCT;

// **** D18F2x268_dct1 Register Definition ****
// Address
#define D18F2x268_dct1_ADDRESS                                  0x268

// Type
#define D18F2x268_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x268_dct1_NibbleErrSts_OFFSET                      0
#define D18F2x268_dct1_NibbleErrSts_WIDTH                       18
#define D18F2x268_dct1_NibbleErrSts_MASK                        0x3ffff
#define D18F2x268_dct1_Reserved_31_18_OFFSET                    18
#define D18F2x268_dct1_Reserved_31_18_WIDTH                     14
#define D18F2x268_dct1_Reserved_31_18_MASK                      0xfffc0000

/// D18F2x268_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             NibbleErrSts:18; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x268_dct1_STRUCT;

// **** D18F2x268_dct0 Register Definition ****
// Address
#define D18F2x268_dct0_ADDRESS                                  0x268

// Type
#define D18F2x268_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x268_dct0_NibbleErrSts_OFFSET                      0
#define D18F2x268_dct0_NibbleErrSts_WIDTH                       18
#define D18F2x268_dct0_NibbleErrSts_MASK                        0x3ffff
#define D18F2x268_dct0_Reserved_31_18_OFFSET                    18
#define D18F2x268_dct0_Reserved_31_18_WIDTH                     14
#define D18F2x268_dct0_Reserved_31_18_MASK                      0xfffc0000

/// D18F2x268_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             NibbleErrSts:18; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x268_dct0_STRUCT;

// **** D18F2x26C_dct1 Register Definition ****
// Address
#define D18F2x26C_dct1_ADDRESS                                  0x26c

// Type
#define D18F2x26C_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x26C_dct1_NibbleErr180Sts_OFFSET                   0
#define D18F2x26C_dct1_NibbleErr180Sts_WIDTH                    18
#define D18F2x26C_dct1_NibbleErr180Sts_MASK                     0x3ffff
#define D18F2x26C_dct1_Reserved_31_18_OFFSET                    18
#define D18F2x26C_dct1_Reserved_31_18_WIDTH                     14
#define D18F2x26C_dct1_Reserved_31_18_MASK                      0xfffc0000

/// D18F2x26C_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                          NibbleErr180Sts:18; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x26C_dct1_STRUCT;

// **** D18F2x26C_dct0 Register Definition ****
// Address
#define D18F2x26C_dct0_ADDRESS                                  0x26c

// Type
#define D18F2x26C_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x26C_dct0_NibbleErr180Sts_OFFSET                   0
#define D18F2x26C_dct0_NibbleErr180Sts_WIDTH                    18
#define D18F2x26C_dct0_NibbleErr180Sts_MASK                     0x3ffff
#define D18F2x26C_dct0_Reserved_31_18_OFFSET                    18
#define D18F2x26C_dct0_Reserved_31_18_WIDTH                     14
#define D18F2x26C_dct0_Reserved_31_18_MASK                      0xfffc0000

/// D18F2x26C_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                          NibbleErr180Sts:18; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x26C_dct0_STRUCT;

// **** D18F2x270_dct0 Register Definition ****
// Address
#define D18F2x270_dct0_ADDRESS                                  0x270

// Type
#define D18F2x270_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x270_dct0_DataPrbsSeed_OFFSET                      0
#define D18F2x270_dct0_DataPrbsSeed_WIDTH                       19
#define D18F2x270_dct0_DataPrbsSeed_MASK                        0x7ffff
#define D18F2x270_dct0_Reserved_23_19_OFFSET                    19
#define D18F2x270_dct0_Reserved_23_19_WIDTH                     5
#define D18F2x270_dct0_Reserved_23_19_MASK                      0xf80000
#define D18F2x270_dct0_Reserved_30_24_OFFSET                    24
#define D18F2x270_dct0_Reserved_30_24_WIDTH                     7
#define D18F2x270_dct0_Reserved_30_24_MASK                      0x7f000000
#define D18F2x270_dct0_Reserved_31_31_OFFSET                    31
#define D18F2x270_dct0_Reserved_31_31_WIDTH                     1
#define D18F2x270_dct0_Reserved_31_31_MASK                      0x80000000

/// D18F2x270_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             DataPrbsSeed:19; ///<
    UINT32                                           Reserved_23_19:5 ; ///<
    UINT32                                           Reserved_30_24:7 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x270_dct0_STRUCT;

// **** D18F2x270_dct1 Register Definition ****
// Address
#define D18F2x270_dct1_ADDRESS                                  0x270

// Type
#define D18F2x270_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x270_dct1_DataPrbsSeed_OFFSET                      0
#define D18F2x270_dct1_DataPrbsSeed_WIDTH                       19
#define D18F2x270_dct1_DataPrbsSeed_MASK                        0x7ffff
#define D18F2x270_dct1_Reserved_23_19_OFFSET                    19
#define D18F2x270_dct1_Reserved_23_19_WIDTH                     5
#define D18F2x270_dct1_Reserved_23_19_MASK                      0xf80000
#define D18F2x270_dct1_Reserved_30_24_OFFSET                    24
#define D18F2x270_dct1_Reserved_30_24_WIDTH                     7
#define D18F2x270_dct1_Reserved_30_24_MASK                      0x7f000000
#define D18F2x270_dct1_Reserved_31_31_OFFSET                    31
#define D18F2x270_dct1_Reserved_31_31_WIDTH                     1
#define D18F2x270_dct1_Reserved_31_31_MASK                      0x80000000

/// D18F2x270_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             DataPrbsSeed:19; ///<
    UINT32                                           Reserved_23_19:5 ; ///<
    UINT32                                           Reserved_30_24:7 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x270_dct1_STRUCT;

// **** D18F2x274_dct0 Register Definition ****
// Address
#define D18F2x274_dct0_ADDRESS                                  0x274

// Type
#define D18F2x274_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x274_dct0_DQMask_31_0__OFFSET                      0
#define D18F2x274_dct0_DQMask_31_0__WIDTH                       32
#define D18F2x274_dct0_DQMask_31_0__MASK                        0xffffffff

/// D18F2x274_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             DQMask_31_0_:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x274_dct0_STRUCT;

// **** D18F2x274_dct1 Register Definition ****
// Address
#define D18F2x274_dct1_ADDRESS                                  0x274

// Type
#define D18F2x274_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x274_dct1_DQMask_31_0__OFFSET                      0
#define D18F2x274_dct1_DQMask_31_0__WIDTH                       32
#define D18F2x274_dct1_DQMask_31_0__MASK                        0xffffffff

/// D18F2x274_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             DQMask_31_0_:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x274_dct1_STRUCT;

// **** D18F2x278_dct0 Register Definition ****
// Address
#define D18F2x278_dct0_ADDRESS                                  0x278

// Type
#define D18F2x278_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x278_dct0_DQMask_63_32__OFFSET                     0
#define D18F2x278_dct0_DQMask_63_32__WIDTH                      32
#define D18F2x278_dct0_DQMask_63_32__MASK                       0xffffffff

/// D18F2x278_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                            DQMask_63_32_:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x278_dct0_STRUCT;

// **** D18F2x278_dct1 Register Definition ****
// Address
#define D18F2x278_dct1_ADDRESS                                  0x278

// Type
#define D18F2x278_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x278_dct1_DQMask_63_32__OFFSET                     0
#define D18F2x278_dct1_DQMask_63_32__WIDTH                      32
#define D18F2x278_dct1_DQMask_63_32__MASK                       0xffffffff

/// D18F2x278_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                            DQMask_63_32_:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x278_dct1_STRUCT;

// **** D18F2x28C_dct0 Register Definition ****
// Address
#define D18F2x28C_dct0_ADDRESS                                  0x28c

// Type
#define D18F2x28C_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x28C_dct0_CmdAddress_17_0__OFFSET                  0
#define D18F2x28C_dct0_CmdAddress_17_0__WIDTH                   18
#define D18F2x28C_dct0_CmdAddress_17_0__MASK                    0x3ffff
#define D18F2x28C_dct0_Reserved_18_18_OFFSET                    18
#define D18F2x28C_dct0_Reserved_18_18_WIDTH                     1
#define D18F2x28C_dct0_Reserved_18_18_MASK                      0x40000
#define D18F2x28C_dct0_CmdBank_2_0__OFFSET                      19
#define D18F2x28C_dct0_CmdBank_2_0__WIDTH                       3
#define D18F2x28C_dct0_CmdBank_2_0__MASK                        0x380000
#define D18F2x28C_dct0_CmdChipSelect_OFFSET                     22
#define D18F2x28C_dct0_CmdChipSelect_WIDTH                      8
#define D18F2x28C_dct0_CmdChipSelect_MASK                       0x3fc00000
#define D18F2x28C_dct0_SendPchgCmd_OFFSET                       30
#define D18F2x28C_dct0_SendPchgCmd_WIDTH                        1
#define D18F2x28C_dct0_SendPchgCmd_MASK                         0x40000000
#define D18F2x28C_dct0_SendActCmd_OFFSET                        31
#define D18F2x28C_dct0_SendActCmd_WIDTH                         1
#define D18F2x28C_dct0_SendActCmd_MASK                          0x80000000

/// D18F2x28C_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                         CmdAddress_17_0_:18; ///<
    UINT32                                           Reserved_18_18:1 ; ///<
    UINT32                                             CmdBank_2_0_:3 ; ///<
    UINT32                                            CmdChipSelect:8 ; ///<
    UINT32                                              SendPchgCmd:1 ; ///<
    UINT32                                               SendActCmd:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x28C_dct0_STRUCT;

// **** D18F2x28C_dct1 Register Definition ****
// Address
#define D18F2x28C_dct1_ADDRESS                                  0x28c

// Type
#define D18F2x28C_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x28C_dct1_CmdAddress_17_0__OFFSET                  0
#define D18F2x28C_dct1_CmdAddress_17_0__WIDTH                   18
#define D18F2x28C_dct1_CmdAddress_17_0__MASK                    0x3ffff
#define D18F2x28C_dct1_Reserved_18_18_OFFSET                    18
#define D18F2x28C_dct1_Reserved_18_18_WIDTH                     1
#define D18F2x28C_dct1_Reserved_18_18_MASK                      0x40000
#define D18F2x28C_dct1_CmdBank_2_0__OFFSET                      19
#define D18F2x28C_dct1_CmdBank_2_0__WIDTH                       3
#define D18F2x28C_dct1_CmdBank_2_0__MASK                        0x380000
#define D18F2x28C_dct1_CmdChipSelect_OFFSET                     22
#define D18F2x28C_dct1_CmdChipSelect_WIDTH                      8
#define D18F2x28C_dct1_CmdChipSelect_MASK                       0x3fc00000
#define D18F2x28C_dct1_SendPchgCmd_OFFSET                       30
#define D18F2x28C_dct1_SendPchgCmd_WIDTH                        1
#define D18F2x28C_dct1_SendPchgCmd_MASK                         0x40000000
#define D18F2x28C_dct1_SendActCmd_OFFSET                        31
#define D18F2x28C_dct1_SendActCmd_WIDTH                         1
#define D18F2x28C_dct1_SendActCmd_MASK                          0x80000000

/// D18F2x28C_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                         CmdAddress_17_0_:18; ///<
    UINT32                                           Reserved_18_18:1 ; ///<
    UINT32                                             CmdBank_2_0_:3 ; ///<
    UINT32                                            CmdChipSelect:8 ; ///<
    UINT32                                              SendPchgCmd:1 ; ///<
    UINT32                                               SendActCmd:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x28C_dct1_STRUCT;

// **** D18F2x290_dct1 Register Definition ****
// Address
#define D18F2x290_dct1_ADDRESS                                  0x290

// Type
#define D18F2x290_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x290_dct1_ErrCmdNum_OFFSET                         0
#define D18F2x290_dct1_ErrCmdNum_WIDTH                          21
#define D18F2x290_dct1_ErrCmdNum_MASK                           0x1fffff
#define D18F2x290_dct1_Reserved_23_21_OFFSET                    21
#define D18F2x290_dct1_Reserved_23_21_WIDTH                     3
#define D18F2x290_dct1_Reserved_23_21_MASK                      0xe00000
#define D18F2x290_dct1_ErrBeatNum_OFFSET                        24
#define D18F2x290_dct1_ErrBeatNum_WIDTH                         3
#define D18F2x290_dct1_ErrBeatNum_MASK                          0x7000000
#define D18F2x290_dct1_Reserved_31_27_OFFSET                    27
#define D18F2x290_dct1_Reserved_31_27_WIDTH                     5
#define D18F2x290_dct1_Reserved_31_27_MASK                      0xf8000000

/// D18F2x290_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                                ErrCmdNum:21; ///<
    UINT32                                           Reserved_23_21:3 ; ///<
    UINT32                                               ErrBeatNum:3 ; ///<
    UINT32                                           Reserved_31_27:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x290_dct1_STRUCT;

// **** D18F2x290_dct0 Register Definition ****
// Address
#define D18F2x290_dct0_ADDRESS                                  0x290

// Type
#define D18F2x290_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x290_dct0_ErrCmdNum_OFFSET                         0
#define D18F2x290_dct0_ErrCmdNum_WIDTH                          21
#define D18F2x290_dct0_ErrCmdNum_MASK                           0x1fffff
#define D18F2x290_dct0_Reserved_23_21_OFFSET                    21
#define D18F2x290_dct0_Reserved_23_21_WIDTH                     3
#define D18F2x290_dct0_Reserved_23_21_MASK                      0xe00000
#define D18F2x290_dct0_ErrBeatNum_OFFSET                        24
#define D18F2x290_dct0_ErrBeatNum_WIDTH                         3
#define D18F2x290_dct0_ErrBeatNum_MASK                          0x7000000
#define D18F2x290_dct0_Reserved_31_27_OFFSET                    27
#define D18F2x290_dct0_Reserved_31_27_WIDTH                     5
#define D18F2x290_dct0_Reserved_31_27_MASK                      0xf8000000

/// D18F2x290_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                                ErrCmdNum:21; ///<
    UINT32                                           Reserved_23_21:3 ; ///<
    UINT32                                               ErrBeatNum:3 ; ///<
    UINT32                                           Reserved_31_27:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x290_dct0_STRUCT;

// **** D18F2x294_dct1 Register Definition ****
// Address
#define D18F2x294_dct1_ADDRESS                                  0x294

// Type
#define D18F2x294_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x294_dct1_DQErr_31_0__OFFSET                       0
#define D18F2x294_dct1_DQErr_31_0__WIDTH                        32
#define D18F2x294_dct1_DQErr_31_0__MASK                         0xffffffff

/// D18F2x294_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                              DQErr_31_0_:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x294_dct1_STRUCT;

// **** D18F2x294_dct0 Register Definition ****
// Address
#define D18F2x294_dct0_ADDRESS                                  0x294

// Type
#define D18F2x294_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x294_dct0_DQErr_31_0__OFFSET                       0
#define D18F2x294_dct0_DQErr_31_0__WIDTH                        32
#define D18F2x294_dct0_DQErr_31_0__MASK                         0xffffffff

/// D18F2x294_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                              DQErr_31_0_:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x294_dct0_STRUCT;

// **** D18F2x298_dct0 Register Definition ****
// Address
#define D18F2x298_dct0_ADDRESS                                  0x298

// Type
#define D18F2x298_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x298_dct0_DQErr_63_32__OFFSET                      0
#define D18F2x298_dct0_DQErr_63_32__WIDTH                       32
#define D18F2x298_dct0_DQErr_63_32__MASK                        0xffffffff

/// D18F2x298_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             DQErr_63_32_:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x298_dct0_STRUCT;

// **** D18F2x298_dct1 Register Definition ****
// Address
#define D18F2x298_dct1_ADDRESS                                  0x298

// Type
#define D18F2x298_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x298_dct1_DQErr_63_32__OFFSET                      0
#define D18F2x298_dct1_DQErr_63_32__WIDTH                       32
#define D18F2x298_dct1_DQErr_63_32__MASK                        0xffffffff

/// D18F2x298_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             DQErr_63_32_:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x298_dct1_STRUCT;

// **** D18F2x2E0_dct1 Register Definition ****
// Address
#define D18F2x2E0_dct1_ADDRESS                                  0x2e0

// Type
#define D18F2x2E0_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x2E0_dct1_CurMemPstate_OFFSET                      0
#define D18F2x2E0_dct1_CurMemPstate_WIDTH                       1
#define D18F2x2E0_dct1_CurMemPstate_MASK                        0x1
#define D18F2x2E0_dct1_Reserved_19_1_OFFSET                     1
#define D18F2x2E0_dct1_Reserved_19_1_WIDTH                      19
#define D18F2x2E0_dct1_Reserved_19_1_MASK                       0xffffe
#define D18F2x2E0_dct1_MxMrsEn_OFFSET                           20
#define D18F2x2E0_dct1_MxMrsEn_WIDTH                            3
#define D18F2x2E0_dct1_MxMrsEn_MASK                             0x700000
#define D18F2x2E0_dct1_Reserved_23_23_OFFSET                    23
#define D18F2x2E0_dct1_Reserved_23_23_WIDTH                     1
#define D18F2x2E0_dct1_Reserved_23_23_MASK                      0x800000
#define D18F2x2E0_dct1_M1MemClkFreq_OFFSET                      24
#define D18F2x2E0_dct1_M1MemClkFreq_WIDTH                       5
#define D18F2x2E0_dct1_M1MemClkFreq_MASK                        0x1f000000
#define D18F2x2E0_dct1_Reserved_29_29_OFFSET                    29
#define D18F2x2E0_dct1_Reserved_29_29_WIDTH                     1
#define D18F2x2E0_dct1_Reserved_29_29_MASK                      0x20000000
#define D18F2x2E0_dct1_FastMstateDis_OFFSET                     30
#define D18F2x2E0_dct1_FastMstateDis_WIDTH                      1
#define D18F2x2E0_dct1_FastMstateDis_MASK                       0x40000000
#define D18F2x2E0_dct1_Reserved_31_31_OFFSET                    31
#define D18F2x2E0_dct1_Reserved_31_31_WIDTH                     1
#define D18F2x2E0_dct1_Reserved_31_31_MASK                      0x80000000

/// D18F2x2E0_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             CurMemPstate:1 ; ///<
    UINT32                                            Reserved_19_1:19; ///<
    UINT32                                                  MxMrsEn:3 ; ///<
    UINT32                                           Reserved_23_23:1 ; ///<
    UINT32                                             M1MemClkFreq:5 ; ///<
    UINT32                                           Reserved_29_29:1 ; ///<
    UINT32                                            FastMstateDis:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x2E0_dct1_STRUCT;

// **** D18F2x2E0_dct0 Register Definition ****
// Address
#define D18F2x2E0_dct0_ADDRESS                                  0x2e0

// Type
#define D18F2x2E0_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x2E0_dct0_CurMemPstate_OFFSET                      0
#define D18F2x2E0_dct0_CurMemPstate_WIDTH                       1
#define D18F2x2E0_dct0_CurMemPstate_MASK                        0x1
#define D18F2x2E0_dct0_Reserved_19_1_OFFSET                     1
#define D18F2x2E0_dct0_Reserved_19_1_WIDTH                      19
#define D18F2x2E0_dct0_Reserved_19_1_MASK                       0xffffe
#define D18F2x2E0_dct0_MxMrsEn_OFFSET                           20
#define D18F2x2E0_dct0_MxMrsEn_WIDTH                            3
#define D18F2x2E0_dct0_MxMrsEn_MASK                             0x700000
#define D18F2x2E0_dct0_Reserved_23_23_OFFSET                    23
#define D18F2x2E0_dct0_Reserved_23_23_WIDTH                     1
#define D18F2x2E0_dct0_Reserved_23_23_MASK                      0x800000
#define D18F2x2E0_dct0_M1MemClkFreq_OFFSET                      24
#define D18F2x2E0_dct0_M1MemClkFreq_WIDTH                       5
#define D18F2x2E0_dct0_M1MemClkFreq_MASK                        0x1f000000
#define D18F2x2E0_dct0_Reserved_29_29_OFFSET                    29
#define D18F2x2E0_dct0_Reserved_29_29_WIDTH                     1
#define D18F2x2E0_dct0_Reserved_29_29_MASK                      0x20000000
#define D18F2x2E0_dct0_FastMstateDis_OFFSET                     30
#define D18F2x2E0_dct0_FastMstateDis_WIDTH                      1
#define D18F2x2E0_dct0_FastMstateDis_MASK                       0x40000000
#define D18F2x2E0_dct0_Reserved_31_31_OFFSET                    31
#define D18F2x2E0_dct0_Reserved_31_31_WIDTH                     1
#define D18F2x2E0_dct0_Reserved_31_31_MASK                      0x80000000

/// D18F2x2E0_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             CurMemPstate:1 ; ///<
    UINT32                                            Reserved_19_1:19; ///<
    UINT32                                                  MxMrsEn:3 ; ///<
    UINT32                                           Reserved_23_23:1 ; ///<
    UINT32                                             M1MemClkFreq:5 ; ///<
    UINT32                                           Reserved_29_29:1 ; ///<
    UINT32                                            FastMstateDis:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x2E0_dct0_STRUCT;

// **** D18F2x2E8_dct0_mp1 Register Definition ****
// Address
#define D18F2x2E8_dct0_mp1_ADDRESS                              0x2e8

// Type
#define D18F2x2E8_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
// Field Data
#define D18F2x2E8_dct0_mp1_MxMr0_OFFSET                         0
#define D18F2x2E8_dct0_mp1_MxMr0_WIDTH                          16
#define D18F2x2E8_dct0_mp1_MxMr0_MASK                           0xffff
#define D18F2x2E8_dct0_mp1_MxMr1_OFFSET                         16
#define D18F2x2E8_dct0_mp1_MxMr1_WIDTH                          16
#define D18F2x2E8_dct0_mp1_MxMr1_MASK                           0xffff0000

/// D18F2x2E8_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                    MxMr0:16; ///<
    UINT32                                                    MxMr1:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x2E8_dct0_mp1_STRUCT;

// **** D18F2x2E8_dct1_mp1 Register Definition ****
// Address
#define D18F2x2E8_dct1_mp1_ADDRESS                              0x2e8

// Type
#define D18F2x2E8_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
// Field Data
#define D18F2x2E8_dct1_mp1_MxMr0_OFFSET                         0
#define D18F2x2E8_dct1_mp1_MxMr0_WIDTH                          16
#define D18F2x2E8_dct1_mp1_MxMr0_MASK                           0xffff
#define D18F2x2E8_dct1_mp1_MxMr1_OFFSET                         16
#define D18F2x2E8_dct1_mp1_MxMr1_WIDTH                          16
#define D18F2x2E8_dct1_mp1_MxMr1_MASK                           0xffff0000

/// D18F2x2E8_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                    MxMr0:16; ///<
    UINT32                                                    MxMr1:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x2E8_dct1_mp1_STRUCT;

// **** D18F2x2E8_dct1_mp0 Register Definition ****
// Address
#define D18F2x2E8_dct1_mp0_ADDRESS                              0x2e8

// Type
#define D18F2x2E8_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
// Field Data
#define D18F2x2E8_dct1_mp0_MxMr0_OFFSET                         0
#define D18F2x2E8_dct1_mp0_MxMr0_WIDTH                          16
#define D18F2x2E8_dct1_mp0_MxMr0_MASK                           0xffff
#define D18F2x2E8_dct1_mp0_MxMr1_OFFSET                         16
#define D18F2x2E8_dct1_mp0_MxMr1_WIDTH                          16
#define D18F2x2E8_dct1_mp0_MxMr1_MASK                           0xffff0000

/// D18F2x2E8_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                    MxMr0:16; ///<
    UINT32                                                    MxMr1:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x2E8_dct1_mp0_STRUCT;

// **** D18F2x2E8_dct0_mp0 Register Definition ****
// Address
#define D18F2x2E8_dct0_mp0_ADDRESS                              0x2e8

// Type
#define D18F2x2E8_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
// Field Data
#define D18F2x2E8_dct0_mp0_MxMr0_OFFSET                         0
#define D18F2x2E8_dct0_mp0_MxMr0_WIDTH                          16
#define D18F2x2E8_dct0_mp0_MxMr0_MASK                           0xffff
#define D18F2x2E8_dct0_mp0_MxMr1_OFFSET                         16
#define D18F2x2E8_dct0_mp0_MxMr1_WIDTH                          16
#define D18F2x2E8_dct0_mp0_MxMr1_MASK                           0xffff0000

/// D18F2x2E8_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                    MxMr0:16; ///<
    UINT32                                                    MxMr1:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x2E8_dct0_mp0_STRUCT;

// **** D18F2x2EC_dct0_mp0 Register Definition ****
// Address
#define D18F2x2EC_dct0_mp0_ADDRESS                              0x2ec

// Type
#define D18F2x2EC_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
// Field Data
#define D18F2x2EC_dct0_mp0_MxMr2_OFFSET                         0
#define D18F2x2EC_dct0_mp0_MxMr2_WIDTH                          16
#define D18F2x2EC_dct0_mp0_MxMr2_MASK                           0xffff
#define D18F2x2EC_dct0_mp0_Reserved_31_16_OFFSET                16
#define D18F2x2EC_dct0_mp0_Reserved_31_16_WIDTH                 16
#define D18F2x2EC_dct0_mp0_Reserved_31_16_MASK                  0xffff0000

/// D18F2x2EC_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                    MxMr2:16; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x2EC_dct0_mp0_STRUCT;

// **** D18F2x2EC_dct0_mp1 Register Definition ****
// Address
#define D18F2x2EC_dct0_mp1_ADDRESS                              0x2ec

// Type
#define D18F2x2EC_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
// Field Data
#define D18F2x2EC_dct0_mp1_MxMr2_OFFSET                         0
#define D18F2x2EC_dct0_mp1_MxMr2_WIDTH                          16
#define D18F2x2EC_dct0_mp1_MxMr2_MASK                           0xffff
#define D18F2x2EC_dct0_mp1_Reserved_31_16_OFFSET                16
#define D18F2x2EC_dct0_mp1_Reserved_31_16_WIDTH                 16
#define D18F2x2EC_dct0_mp1_Reserved_31_16_MASK                  0xffff0000

/// D18F2x2EC_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                    MxMr2:16; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x2EC_dct0_mp1_STRUCT;

// **** D18F2x2EC_dct1_mp1 Register Definition ****
// Address
#define D18F2x2EC_dct1_mp1_ADDRESS                              0x2ec

// Type
#define D18F2x2EC_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
// Field Data
#define D18F2x2EC_dct1_mp1_MxMr2_OFFSET                         0
#define D18F2x2EC_dct1_mp1_MxMr2_WIDTH                          16
#define D18F2x2EC_dct1_mp1_MxMr2_MASK                           0xffff
#define D18F2x2EC_dct1_mp1_Reserved_31_16_OFFSET                16
#define D18F2x2EC_dct1_mp1_Reserved_31_16_WIDTH                 16
#define D18F2x2EC_dct1_mp1_Reserved_31_16_MASK                  0xffff0000

/// D18F2x2EC_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                    MxMr2:16; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x2EC_dct1_mp1_STRUCT;

// **** D18F2x2EC_dct1_mp0 Register Definition ****
// Address
#define D18F2x2EC_dct1_mp0_ADDRESS                              0x2ec

// Type
#define D18F2x2EC_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
// Field Data
#define D18F2x2EC_dct1_mp0_MxMr2_OFFSET                         0
#define D18F2x2EC_dct1_mp0_MxMr2_WIDTH                          16
#define D18F2x2EC_dct1_mp0_MxMr2_MASK                           0xffff
#define D18F2x2EC_dct1_mp0_Reserved_31_16_OFFSET                16
#define D18F2x2EC_dct1_mp0_Reserved_31_16_WIDTH                 16
#define D18F2x2EC_dct1_mp0_Reserved_31_16_MASK                  0xffff0000

/// D18F2x2EC_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                    MxMr2:16; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x2EC_dct1_mp0_STRUCT;

// **** D18F2x2F0_dct1_mp1 Register Definition ****
// Address
#define D18F2x2F0_dct1_mp1_ADDRESS                              0x2f0

// Type
#define D18F2x2F0_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
// Field Data
#define D18F2x2F0_dct1_mp1_EffArbDis_OFFSET                     0
#define D18F2x2F0_dct1_mp1_EffArbDis_WIDTH                      1
#define D18F2x2F0_dct1_mp1_EffArbDis_MASK                       0x1
#define D18F2x2F0_dct1_mp1_Reserved_31_1_OFFSET                 1
#define D18F2x2F0_dct1_mp1_Reserved_31_1_WIDTH                  31
#define D18F2x2F0_dct1_mp1_Reserved_31_1_MASK                   0xfffffffe

/// D18F2x2F0_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                EffArbDis:1 ; ///<
    UINT32                                            Reserved_31_1:31; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x2F0_dct1_mp1_STRUCT;

// **** D18F2x2F0_dct0_mp1 Register Definition ****
// Address
#define D18F2x2F0_dct0_mp1_ADDRESS                              0x2f0

// Type
#define D18F2x2F0_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
// Field Data
#define D18F2x2F0_dct0_mp1_EffArbDis_OFFSET                     0
#define D18F2x2F0_dct0_mp1_EffArbDis_WIDTH                      1
#define D18F2x2F0_dct0_mp1_EffArbDis_MASK                       0x1
#define D18F2x2F0_dct0_mp1_Reserved_31_1_OFFSET                 1
#define D18F2x2F0_dct0_mp1_Reserved_31_1_WIDTH                  31
#define D18F2x2F0_dct0_mp1_Reserved_31_1_MASK                   0xfffffffe

/// D18F2x2F0_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                EffArbDis:1 ; ///<
    UINT32                                            Reserved_31_1:31; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x2F0_dct0_mp1_STRUCT;

// **** D18F2x2F0_dct1_mp0 Register Definition ****
// Address
#define D18F2x2F0_dct1_mp0_ADDRESS                              0x2f0

// Type
#define D18F2x2F0_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
// Field Data
#define D18F2x2F0_dct1_mp0_EffArbDis_OFFSET                     0
#define D18F2x2F0_dct1_mp0_EffArbDis_WIDTH                      1
#define D18F2x2F0_dct1_mp0_EffArbDis_MASK                       0x1
#define D18F2x2F0_dct1_mp0_Reserved_31_1_OFFSET                 1
#define D18F2x2F0_dct1_mp0_Reserved_31_1_WIDTH                  31
#define D18F2x2F0_dct1_mp0_Reserved_31_1_MASK                   0xfffffffe

/// D18F2x2F0_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                EffArbDis:1 ; ///<
    UINT32                                            Reserved_31_1:31; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x2F0_dct1_mp0_STRUCT;

// **** D18F2x2F0_dct0_mp0 Register Definition ****
// Address
#define D18F2x2F0_dct0_mp0_ADDRESS                              0x2f0

// Type
#define D18F2x2F0_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
// Field Data
#define D18F2x2F0_dct0_mp0_EffArbDis_OFFSET                     0
#define D18F2x2F0_dct0_mp0_EffArbDis_WIDTH                      1
#define D18F2x2F0_dct0_mp0_EffArbDis_MASK                       0x1
#define D18F2x2F0_dct0_mp0_Reserved_31_1_OFFSET                 1
#define D18F2x2F0_dct0_mp0_Reserved_31_1_WIDTH                  31
#define D18F2x2F0_dct0_mp0_Reserved_31_1_MASK                   0xfffffffe

/// D18F2x2F0_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                EffArbDis:1 ; ///<
    UINT32                                            Reserved_31_1:31; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x2F0_dct0_mp0_STRUCT;

// **** D18F2x400_dct1 Register Definition ****
// Address
#define D18F2x400_dct1_ADDRESS                                  0x400

// Type
#define D18F2x400_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x400_dct1_MctTokenLimit_OFFSET                     0
#define D18F2x400_dct1_MctTokenLimit_WIDTH                      4
#define D18F2x400_dct1_MctTokenLimit_MASK                       0xf
#define D18F2x400_dct1_Reserved_7_4_OFFSET                      4
#define D18F2x400_dct1_Reserved_7_4_WIDTH                       4
#define D18F2x400_dct1_Reserved_7_4_MASK                        0xf0
#define D18F2x400_dct1_GmcTokenLimit_OFFSET                     8
#define D18F2x400_dct1_GmcTokenLimit_WIDTH                      4
#define D18F2x400_dct1_GmcTokenLimit_MASK                       0xf00
#define D18F2x400_dct1_Reserved_15_12_OFFSET                    12
#define D18F2x400_dct1_Reserved_15_12_WIDTH                     4
#define D18F2x400_dct1_Reserved_15_12_MASK                      0xf000
#define D18F2x400_dct1_Reserved_31_16_OFFSET                    16
#define D18F2x400_dct1_Reserved_31_16_WIDTH                     16
#define D18F2x400_dct1_Reserved_31_16_MASK                      0xffff0000

/// D18F2x400_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                            MctTokenLimit:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                            GmcTokenLimit:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x400_dct1_STRUCT;

// **** D18F2x400_dct0 Register Definition ****
// Address
#define D18F2x400_dct0_ADDRESS                                  0x400

// Type
#define D18F2x400_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x400_dct0_MctTokenLimit_OFFSET                     0
#define D18F2x400_dct0_MctTokenLimit_WIDTH                      4
#define D18F2x400_dct0_MctTokenLimit_MASK                       0xf
#define D18F2x400_dct0_Reserved_7_4_OFFSET                      4
#define D18F2x400_dct0_Reserved_7_4_WIDTH                       4
#define D18F2x400_dct0_Reserved_7_4_MASK                        0xf0
#define D18F2x400_dct0_GmcTokenLimit_OFFSET                     8
#define D18F2x400_dct0_GmcTokenLimit_WIDTH                      4
#define D18F2x400_dct0_GmcTokenLimit_MASK                       0xf00
#define D18F2x400_dct0_Reserved_15_12_OFFSET                    12
#define D18F2x400_dct0_Reserved_15_12_WIDTH                     4
#define D18F2x400_dct0_Reserved_15_12_MASK                      0xf000
#define D18F2x400_dct0_Reserved_31_16_OFFSET                    16
#define D18F2x400_dct0_Reserved_31_16_WIDTH                     16
#define D18F2x400_dct0_Reserved_31_16_MASK                      0xffff0000

/// D18F2x400_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                            MctTokenLimit:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                            GmcTokenLimit:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x400_dct0_STRUCT;

// **** D18F2x404_dct0 Register Definition ****
// Address
#define D18F2x404_dct0_ADDRESS                                  0x404

// Type
#define D18F2x404_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x404_dct0_UrMctTokenLimit_OFFSET                   0
#define D18F2x404_dct0_UrMctTokenLimit_WIDTH                    4
#define D18F2x404_dct0_UrMctTokenLimit_MASK                     0xf
#define D18F2x404_dct0_UrMctMinTokens_OFFSET                    4
#define D18F2x404_dct0_UrMctMinTokens_WIDTH                     4
#define D18F2x404_dct0_UrMctMinTokens_MASK                      0xf0
#define D18F2x404_dct0_UrGmcTokenLimit_OFFSET                   8
#define D18F2x404_dct0_UrGmcTokenLimit_WIDTH                    4
#define D18F2x404_dct0_UrGmcTokenLimit_MASK                     0xf00
#define D18F2x404_dct0_UrGmcMinTokens_OFFSET                    12
#define D18F2x404_dct0_UrGmcMinTokens_WIDTH                     4
#define D18F2x404_dct0_UrGmcMinTokens_MASK                      0xf000
#define D18F2x404_dct0_UrgentTknDis_OFFSET                      16
#define D18F2x404_dct0_UrgentTknDis_WIDTH                       1
#define D18F2x404_dct0_UrgentTknDis_MASK                        0x10000
#define D18F2x404_dct0_Reserved_31_17_OFFSET                    17
#define D18F2x404_dct0_Reserved_31_17_WIDTH                     15
#define D18F2x404_dct0_Reserved_31_17_MASK                      0xfffe0000

/// D18F2x404_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                          UrMctTokenLimit:4 ; ///<
    UINT32                                           UrMctMinTokens:4 ; ///<
    UINT32                                          UrGmcTokenLimit:4 ; ///<
    UINT32                                           UrGmcMinTokens:4 ; ///<
    UINT32                                             UrgentTknDis:1 ; ///<
    UINT32                                           Reserved_31_17:15; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x404_dct0_STRUCT;

// **** D18F2x404_dct1 Register Definition ****
// Address
#define D18F2x404_dct1_ADDRESS                                  0x404

// Type
#define D18F2x404_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x404_dct1_UrMctTokenLimit_OFFSET                   0
#define D18F2x404_dct1_UrMctTokenLimit_WIDTH                    4
#define D18F2x404_dct1_UrMctTokenLimit_MASK                     0xf
#define D18F2x404_dct1_UrMctMinTokens_OFFSET                    4
#define D18F2x404_dct1_UrMctMinTokens_WIDTH                     4
#define D18F2x404_dct1_UrMctMinTokens_MASK                      0xf0
#define D18F2x404_dct1_UrGmcTokenLimit_OFFSET                   8
#define D18F2x404_dct1_UrGmcTokenLimit_WIDTH                    4
#define D18F2x404_dct1_UrGmcTokenLimit_MASK                     0xf00
#define D18F2x404_dct1_UrGmcMinTokens_OFFSET                    12
#define D18F2x404_dct1_UrGmcMinTokens_WIDTH                     4
#define D18F2x404_dct1_UrGmcMinTokens_MASK                      0xf000
#define D18F2x404_dct1_UrgentTknDis_OFFSET                      16
#define D18F2x404_dct1_UrgentTknDis_WIDTH                       1
#define D18F2x404_dct1_UrgentTknDis_MASK                        0x10000
#define D18F2x404_dct1_Reserved_31_17_OFFSET                    17
#define D18F2x404_dct1_Reserved_31_17_WIDTH                     15
#define D18F2x404_dct1_Reserved_31_17_MASK                      0xfffe0000

/// D18F2x404_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                          UrMctTokenLimit:4 ; ///<
    UINT32                                           UrMctMinTokens:4 ; ///<
    UINT32                                          UrGmcTokenLimit:4 ; ///<
    UINT32                                           UrGmcMinTokens:4 ; ///<
    UINT32                                             UrgentTknDis:1 ; ///<
    UINT32                                           Reserved_31_17:15; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x404_dct1_STRUCT;

// **** D18F2x408_dct1 Register Definition ****
// Address
#define D18F2x408_dct1_ADDRESS                                  0x408

// Type
#define D18F2x408_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x408_dct1_CpuElevPrioDis_OFFSET                    0
#define D18F2x408_dct1_CpuElevPrioDis_WIDTH                     1
#define D18F2x408_dct1_CpuElevPrioDis_MASK                      0x1
#define D18F2x408_dct1_TokenAllocSelect_OFFSET                  1
#define D18F2x408_dct1_TokenAllocSelect_WIDTH                   1
#define D18F2x408_dct1_TokenAllocSelect_MASK                    0x2
#define D18F2x408_dct1_Reserved_30_2_OFFSET                     2
#define D18F2x408_dct1_Reserved_30_2_WIDTH                      29
#define D18F2x408_dct1_Reserved_30_2_MASK                       0x7ffffffc
#define D18F2x408_dct1_DisHalfNclkPwrGate_OFFSET                31
#define D18F2x408_dct1_DisHalfNclkPwrGate_WIDTH                 1
#define D18F2x408_dct1_DisHalfNclkPwrGate_MASK                  0x80000000

/// D18F2x408_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                           CpuElevPrioDis:1 ; ///<
    UINT32                                         TokenAllocSelect:1 ; ///<
    UINT32                                            Reserved_30_2:29; ///<
    UINT32                                       DisHalfNclkPwrGate:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x408_dct1_STRUCT;

// **** D18F2x408_dct0 Register Definition ****
// Address
#define D18F2x408_dct0_ADDRESS                                  0x408

// Type
#define D18F2x408_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x408_dct0_CpuElevPrioDis_OFFSET                    0
#define D18F2x408_dct0_CpuElevPrioDis_WIDTH                     1
#define D18F2x408_dct0_CpuElevPrioDis_MASK                      0x1
#define D18F2x408_dct0_TokenAllocSelect_OFFSET                  1
#define D18F2x408_dct0_TokenAllocSelect_WIDTH                   1
#define D18F2x408_dct0_TokenAllocSelect_MASK                    0x2
#define D18F2x408_dct0_Reserved_30_2_OFFSET                     2
#define D18F2x408_dct0_Reserved_30_2_WIDTH                      29
#define D18F2x408_dct0_Reserved_30_2_MASK                       0x7ffffffc
#define D18F2x408_dct0_DisHalfNclkPwrGate_OFFSET                31
#define D18F2x408_dct0_DisHalfNclkPwrGate_WIDTH                 1
#define D18F2x408_dct0_DisHalfNclkPwrGate_MASK                  0x80000000

/// D18F2x408_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                           CpuElevPrioDis:1 ; ///<
    UINT32                                         TokenAllocSelect:1 ; ///<
    UINT32                                            Reserved_30_2:29; ///<
    UINT32                                       DisHalfNclkPwrGate:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x408_dct0_STRUCT;

// **** D18F2x420_dct0 Register Definition ****
// Address
#define D18F2x420_dct0_ADDRESS                                  0x420

// Type
#define D18F2x420_dct0_TYPE                                     TYPE_D18F2_dct0
// Field Data
#define D18F2x420_dct0_CmdRdPtrInit_OFFSET                      0
#define D18F2x420_dct0_CmdRdPtrInit_WIDTH                       4
#define D18F2x420_dct0_CmdRdPtrInit_MASK                        0xf
#define D18F2x420_dct0_Reserved_7_4_OFFSET                      4
#define D18F2x420_dct0_Reserved_7_4_WIDTH                       4
#define D18F2x420_dct0_Reserved_7_4_MASK                        0xf0
#define D18F2x420_dct0_SbRdPtrInit_OFFSET                       8
#define D18F2x420_dct0_SbRdPtrInit_WIDTH                        4
#define D18F2x420_dct0_SbRdPtrInit_MASK                         0xf00
#define D18F2x420_dct0_Reserved_31_12_OFFSET                    12
#define D18F2x420_dct0_Reserved_31_12_WIDTH                     20
#define D18F2x420_dct0_Reserved_31_12_MASK                      0xfffff000

/// D18F2x420_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             CmdRdPtrInit:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                              SbRdPtrInit:4 ; ///<
    UINT32                                           Reserved_31_12:20; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x420_dct0_STRUCT;

// **** D18F2x420_dct1 Register Definition ****
// Address
#define D18F2x420_dct1_ADDRESS                                  0x420

// Type
#define D18F2x420_dct1_TYPE                                     TYPE_D18F2_dct1
// Field Data
#define D18F2x420_dct1_CmdRdPtrInit_OFFSET                      0
#define D18F2x420_dct1_CmdRdPtrInit_WIDTH                       4
#define D18F2x420_dct1_CmdRdPtrInit_MASK                        0xf
#define D18F2x420_dct1_Reserved_7_4_OFFSET                      4
#define D18F2x420_dct1_Reserved_7_4_WIDTH                       4
#define D18F2x420_dct1_Reserved_7_4_MASK                        0xf0
#define D18F2x420_dct1_SbRdPtrInit_OFFSET                       8
#define D18F2x420_dct1_SbRdPtrInit_WIDTH                        4
#define D18F2x420_dct1_SbRdPtrInit_MASK                         0xf00
#define D18F2x420_dct1_Reserved_31_12_OFFSET                    12
#define D18F2x420_dct1_Reserved_31_12_WIDTH                     20
#define D18F2x420_dct1_Reserved_31_12_MASK                      0xfffff000

/// D18F2x420_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             CmdRdPtrInit:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                              SbRdPtrInit:4 ; ///<
    UINT32                                           Reserved_31_12:20; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x420_dct1_STRUCT;

// **** D18F3x00 Register Definition ****
// Address
#define D18F3x00_ADDRESS                                        0x0

// Type
#define D18F3x00_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x00_VendorID_OFFSET                                0
#define D18F3x00_VendorID_WIDTH                                 16
#define D18F3x00_VendorID_MASK                                  0xffff
#define D18F3x00_DeviceID_OFFSET                                16
#define D18F3x00_DeviceID_WIDTH                                 16
#define D18F3x00_DeviceID_MASK                                  0xffff0000

/// D18F3x00
typedef union {
  struct {                                                              ///<
    UINT32                                                 VendorID:16; ///<
    UINT32                                                 DeviceID:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x00_STRUCT;

// **** D18F3x04 Register Definition ****
// Address
#define D18F3x04_ADDRESS                                        0x4

// Type
#define D18F3x04_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x04_Command_OFFSET                                 0
#define D18F3x04_Command_WIDTH                                  16
#define D18F3x04_Command_MASK                                   0xffff
#define D18F3x04_Status_OFFSET                                  16
#define D18F3x04_Status_WIDTH                                   16
#define D18F3x04_Status_MASK                                    0xffff0000

/// D18F3x04
typedef union {
  struct {                                                              ///<
    UINT32                                                  Command:16; ///<
    UINT32                                                   Status:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x04_STRUCT;

// **** D18F3x08 Register Definition ****
// Address
#define D18F3x08_ADDRESS                                        0x8

// Type
#define D18F3x08_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x08_RevID_OFFSET                                   0
#define D18F3x08_RevID_WIDTH                                    8
#define D18F3x08_RevID_MASK                                     0xff
#define D18F3x08_ClassCode_OFFSET                               8
#define D18F3x08_ClassCode_WIDTH                                24
#define D18F3x08_ClassCode_MASK                                 0xffffff00

/// D18F3x08
typedef union {
  struct {                                                              ///<
    UINT32                                                    RevID:8 ; ///<
    UINT32                                                ClassCode:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x08_STRUCT;

// **** D18F3x0C Register Definition ****
// Address
#define D18F3x0C_ADDRESS                                        0xc

// Type
#define D18F3x0C_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x0C_HeaderTypeReg_OFFSET                           0
#define D18F3x0C_HeaderTypeReg_WIDTH                            32
#define D18F3x0C_HeaderTypeReg_MASK                             0xffffffff

/// D18F3x0C
typedef union {
  struct {                                                              ///<
    UINT32                                            HeaderTypeReg:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x0C_STRUCT;

// **** D18F3x34 Register Definition ****
// Address
#define D18F3x34_ADDRESS                                        0x34

// Type
#define D18F3x34_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x34_CapPtr_OFFSET                                  0
#define D18F3x34_CapPtr_WIDTH                                   8
#define D18F3x34_CapPtr_MASK                                    0xff
#define D18F3x34_Reserved_31_8_OFFSET                           8
#define D18F3x34_Reserved_31_8_WIDTH                            24
#define D18F3x34_Reserved_31_8_MASK                             0xffffff00

/// D18F3x34
typedef union {
  struct {                                                              ///<
    UINT32                                                   CapPtr:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x34_STRUCT;

// **** D18F3x40 Register Definition ****
// Address
#define D18F3x40_ADDRESS                                        0x40

// Type
#define D18F3x40_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x40_Unused_4_0_OFFSET                              0
#define D18F3x40_Unused_4_0_WIDTH                               5
#define D18F3x40_Unused_4_0_MASK                                0x1f
#define D18F3x40_SyncPktEn_OFFSET                               5
#define D18F3x40_SyncPktEn_WIDTH                                1
#define D18F3x40_SyncPktEn_MASK                                 0x20
#define D18F3x40_Unused_7_6_OFFSET                              6
#define D18F3x40_Unused_7_6_WIDTH                               2
#define D18F3x40_Unused_7_6_MASK                                0xc0
#define D18F3x40_MstrAbortEn_OFFSET                             8
#define D18F3x40_MstrAbortEn_WIDTH                              1
#define D18F3x40_MstrAbortEn_MASK                               0x100
#define D18F3x40_TgtAbortEn_OFFSET                              9
#define D18F3x40_TgtAbortEn_WIDTH                               1
#define D18F3x40_TgtAbortEn_MASK                                0x200
#define D18F3x40_Unused_10_10_OFFSET                            10
#define D18F3x40_Unused_10_10_WIDTH                             1
#define D18F3x40_Unused_10_10_MASK                              0x400
#define D18F3x40_AtomicRMWEn_OFFSET                             11
#define D18F3x40_AtomicRMWEn_WIDTH                              1
#define D18F3x40_AtomicRMWEn_MASK                               0x800
#define D18F3x40_WDTRptEn_OFFSET                                12
#define D18F3x40_WDTRptEn_WIDTH                                 1
#define D18F3x40_WDTRptEn_MASK                                  0x1000
#define D18F3x40_Unused_15_13_OFFSET                            13
#define D18F3x40_Unused_15_13_WIDTH                             3
#define D18F3x40_Unused_15_13_MASK                              0xe000
#define D18F3x40_NbIntProtEn_OFFSET                             16
#define D18F3x40_NbIntProtEn_WIDTH                              1
#define D18F3x40_NbIntProtEn_MASK                               0x10000
#define D18F3x40_CpPktDatEn_OFFSET                              17
#define D18F3x40_CpPktDatEn_WIDTH                               1
#define D18F3x40_CpPktDatEn_MASK                                0x20000
#define D18F3x40_Unused_24_18_OFFSET                            18
#define D18F3x40_Unused_24_18_WIDTH                             7
#define D18F3x40_Unused_24_18_MASK                              0x1fc0000
#define D18F3x40_UsPwDatErrEn_OFFSET                            25
#define D18F3x40_UsPwDatErrEn_WIDTH                             1
#define D18F3x40_UsPwDatErrEn_MASK                              0x2000000
#define D18F3x40_NbArrayParEn_OFFSET                            26
#define D18F3x40_NbArrayParEn_WIDTH                             1
#define D18F3x40_NbArrayParEn_MASK                              0x4000000
#define D18F3x40_Unused_29_27_OFFSET                            27
#define D18F3x40_Unused_29_27_WIDTH                             3
#define D18F3x40_Unused_29_27_MASK                              0x38000000
#define D18F3x40_Unused_30_30_OFFSET                            30
#define D18F3x40_Unused_30_30_WIDTH                             1
#define D18F3x40_Unused_30_30_MASK                              0x40000000
#define D18F3x40_McaCpuDatErrEn_OFFSET                          31
#define D18F3x40_McaCpuDatErrEn_WIDTH                           1
#define D18F3x40_McaCpuDatErrEn_MASK                            0x80000000

/// D18F3x40
typedef union {
  struct {                                                              ///<
    UINT32                                               Unused_4_0:5 ; ///<
    UINT32                                                SyncPktEn:1 ; ///<
    UINT32                                               Unused_7_6:2 ; ///<
    UINT32                                              MstrAbortEn:1 ; ///<
    UINT32                                               TgtAbortEn:1 ; ///<
    UINT32                                             Unused_10_10:1 ; ///<
    UINT32                                              AtomicRMWEn:1 ; ///<
    UINT32                                                 WDTRptEn:1 ; ///<
    UINT32                                             Unused_15_13:3 ; ///<
    UINT32                                              NbIntProtEn:1 ; ///<
    UINT32                                               CpPktDatEn:1 ; ///<
    UINT32                                             Unused_24_18:7 ; ///<
    UINT32                                             UsPwDatErrEn:1 ; ///<
    UINT32                                             NbArrayParEn:1 ; ///<
    UINT32                                             Unused_29_27:3 ; ///<
    UINT32                                             Unused_30_30:1 ; ///<
    UINT32                                           McaCpuDatErrEn:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x40_STRUCT;

// **** D18F3x44 Register Definition ****
// Address
#define D18F3x44_ADDRESS                                        0x44

// Type
#define D18F3x44_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x44_Reserved_0_0_OFFSET                            0
#define D18F3x44_Reserved_0_0_WIDTH                             1
#define D18F3x44_Reserved_0_0_MASK                              0x1
#define D18F3x44_CpuRdDatErrEn_OFFSET                           1
#define D18F3x44_CpuRdDatErrEn_WIDTH                            1
#define D18F3x44_CpuRdDatErrEn_MASK                             0x2
#define D18F3x44_SyncPktGenDis_OFFSET                           3
#define D18F3x44_SyncPktGenDis_WIDTH                            1
#define D18F3x44_SyncPktGenDis_MASK                             0x8
#define D18F3x44_SyncPktPropDis_OFFSET                          4
#define D18F3x44_SyncPktPropDis_WIDTH                           1
#define D18F3x44_SyncPktPropDis_MASK                            0x10
#define D18F3x44_IoMstAbortDis_OFFSET                           5
#define D18F3x44_IoMstAbortDis_WIDTH                            1
#define D18F3x44_IoMstAbortDis_MASK                             0x20
#define D18F3x44_CpuErrDis_OFFSET                               6
#define D18F3x44_CpuErrDis_WIDTH                                1
#define D18F3x44_CpuErrDis_MASK                                 0x40
#define D18F3x44_IoErrDis_OFFSET                                7
#define D18F3x44_IoErrDis_WIDTH                                 1
#define D18F3x44_IoErrDis_MASK                                  0x80
#define D18F3x44_WDTDis_OFFSET                                  8
#define D18F3x44_WDTDis_WIDTH                                   1
#define D18F3x44_WDTDis_MASK                                    0x100
#define D18F3x44_WDTCntSel_2_0__OFFSET                          9
#define D18F3x44_WDTCntSel_2_0__WIDTH                           3
#define D18F3x44_WDTCntSel_2_0__MASK                            0xe00
#define D18F3x44_WDTBaseSel_OFFSET                              12
#define D18F3x44_WDTBaseSel_WIDTH                               2
#define D18F3x44_WDTBaseSel_MASK                                0x3000
#define D18F3x44_GenCrcErrByte0_OFFSET                          16
#define D18F3x44_GenCrcErrByte0_WIDTH                           1
#define D18F3x44_GenCrcErrByte0_MASK                            0x10000
#define D18F3x44_GenCrcErrByte1_OFFSET                          17
#define D18F3x44_GenCrcErrByte1_WIDTH                           1
#define D18F3x44_GenCrcErrByte1_MASK                            0x20000
#define D18F3x44_GenSubLinkSel_OFFSET                           18
#define D18F3x44_GenSubLinkSel_WIDTH                            2
#define D18F3x44_GenSubLinkSel_MASK                             0xc0000
#define D18F3x44_Reserved_23_22_WIDTH                           2
#define D18F3x44_Reserved_23_22_MASK                            0xc00000
#define D18F3x44_IoRdDatErrEn_OFFSET                            24
#define D18F3x44_IoRdDatErrEn_WIDTH                             1
#define D18F3x44_IoRdDatErrEn_MASK                              0x1000000
#define D18F3x44_DisPciCfgCpuErrRsp_OFFSET                      25
#define D18F3x44_DisPciCfgCpuErrRsp_WIDTH                       1
#define D18F3x44_DisPciCfgCpuErrRsp_MASK                        0x2000000
#define D18F3x44_FlagMcaCorrErr_OFFSET                          26
#define D18F3x44_FlagMcaCorrErr_WIDTH                           1
#define D18F3x44_FlagMcaCorrErr_MASK                            0x4000000
#define D18F3x44_NbMcaToMstCpuEn_OFFSET                         27
#define D18F3x44_NbMcaToMstCpuEn_WIDTH                          1
#define D18F3x44_NbMcaToMstCpuEn_MASK                           0x8000000
#define D18F3x44_DisTgtAbortCpuErrRsp_OFFSET                    28
#define D18F3x44_DisTgtAbortCpuErrRsp_WIDTH                     1
#define D18F3x44_DisTgtAbortCpuErrRsp_MASK                      0x10000000
#define D18F3x44_DisMstAbortCpuErrRsp_OFFSET                    29
#define D18F3x44_DisMstAbortCpuErrRsp_WIDTH                     1
#define D18F3x44_DisMstAbortCpuErrRsp_MASK                      0x20000000
#define D18F3x44_SyncOnDramAdrParErrEn_OFFSET                   30
#define D18F3x44_SyncOnDramAdrParErrEn_WIDTH                    1
#define D18F3x44_SyncOnDramAdrParErrEn_MASK                     0x40000000
#define D18F3x44_NbMcaLogEn_OFFSET                              31
#define D18F3x44_NbMcaLogEn_WIDTH                               1
#define D18F3x44_NbMcaLogEn_MASK                                0x80000000

/// D18F3x44
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                            CpuRdDatErrEn:1 ; ///<
    UINT32                                            SyncOnUcEccEn:1 ; ///<
    UINT32                                            SyncPktGenDis:1 ; ///<
    UINT32                                           SyncPktPropDis:1 ; ///<
    UINT32                                            IoMstAbortDis:1 ; ///<
    UINT32                                                CpuErrDis:1 ; ///<
    UINT32                                                 IoErrDis:1 ; ///<
    UINT32                                                   WDTDis:1 ; ///<
    UINT32                                           WDTCntSel_2_0_:3 ; ///<
    UINT32                                               WDTBaseSel:2 ; ///<
    UINT32                                               :2 ; ///<
    UINT32                                           GenCrcErrByte0:1 ; ///<
    UINT32                                           GenCrcErrByte1:1 ; ///<
    UINT32                                            GenSubLinkSel:2 ; ///<
    UINT32                                              :1 ; ///<
    UINT32                                           :1 ; ///<
    UINT32                                           Reserved_23_22:2 ; ///<
    UINT32                                             IoRdDatErrEn:1 ; ///<
    UINT32                                       DisPciCfgCpuErrRsp:1 ; ///<
    UINT32                                           FlagMcaCorrErr:1 ; ///<
    UINT32                                          NbMcaToMstCpuEn:1 ; ///<
    UINT32                                     DisTgtAbortCpuErrRsp:1 ; ///<
    UINT32                                     DisMstAbortCpuErrRsp:1 ; ///<
    UINT32                                    SyncOnDramAdrParErrEn:1 ; ///<
    UINT32                                               NbMcaLogEn:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x44_STRUCT;

// **** D18F3x48 Register Definition ****
// Address
#define D18F3x48_ADDRESS                                        0x48

// Type
#define D18F3x48_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x48_ErrorCode_OFFSET                               0
#define D18F3x48_ErrorCode_WIDTH                                16
#define D18F3x48_ErrorCode_MASK                                 0xffff
#define D18F3x48_ErrorCodeExt_OFFSET                            16
#define D18F3x48_ErrorCodeExt_WIDTH                             5
#define D18F3x48_ErrorCodeExt_MASK                              0x1f0000
#define D18F3x48_Reserved_23_21_OFFSET                          21
#define D18F3x48_Reserved_23_21_WIDTH                           3
#define D18F3x48_Reserved_23_21_MASK                            0xe00000
#define D18F3x48_Reserved_31_24_OFFSET                          24
#define D18F3x48_Reserved_31_24_WIDTH                           8
#define D18F3x48_Reserved_31_24_MASK                            0xff000000

/// D18F3x48
typedef union {
  struct {                                                              ///<
    UINT32                                                ErrorCode:16; ///<
    UINT32                                             ErrorCodeExt:5 ; ///<
    UINT32                                           Reserved_23_21:3 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x48_STRUCT;

// **** D18F3x4C Register Definition ****
// Address
#define D18F3x4C_ADDRESS                                        0x4c

// Type
#define D18F3x4C_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x4C_ErrCoreId_OFFSET                               0
#define D18F3x4C_ErrCoreId_WIDTH                                4
#define D18F3x4C_ErrCoreId_MASK                                 0xf
#define D18F3x4C_Reserved_39_37_OFFSET                          5
#define D18F3x4C_Reserved_39_37_WIDTH                           3
#define D18F3x4C_Reserved_39_37_MASK                            0xe0
#define D18F3x4C_Reserved_40_40_OFFSET                          8
#define D18F3x4C_Reserved_40_40_WIDTH                           1
#define D18F3x4C_Reserved_40_40_MASK                            0x100
#define D18F3x4C_SubLink_OFFSET                                 9
#define D18F3x4C_SubLink_WIDTH                                  1
#define D18F3x4C_SubLink_MASK                                   0x200
#define D18F3x4C_Reserved_43_42_OFFSET                          10
#define D18F3x4C_Reserved_43_42_WIDTH                           2
#define D18F3x4C_Reserved_43_42_MASK                            0xc00
#define D18F3x4C_Reserved_54_45_OFFSET                          13
#define D18F3x4C_Reserved_54_45_WIDTH                           10
#define D18F3x4C_Reserved_54_45_MASK                            0x7fe000
#define D18F3x4C_Reserved_55_55_OFFSET                          23
#define D18F3x4C_Reserved_55_55_WIDTH                           1
#define D18F3x4C_Reserved_55_55_MASK                            0x800000
#define D18F3x4C_ErrCoreIdVal_OFFSET                            24
#define D18F3x4C_ErrCoreIdVal_WIDTH                             1
#define D18F3x4C_ErrCoreIdVal_MASK                              0x1000000
#define D18F3x4C_PCC_OFFSET                                     25
#define D18F3x4C_PCC_WIDTH                                      1
#define D18F3x4C_PCC_MASK                                       0x2000000
#define D18F3x4C_AddrV_OFFSET                                   26
#define D18F3x4C_AddrV_WIDTH                                    1
#define D18F3x4C_AddrV_MASK                                     0x4000000
#define D18F3x4C_MiscV_OFFSET                                   27
#define D18F3x4C_MiscV_WIDTH                                    1
#define D18F3x4C_MiscV_MASK                                     0x8000000
#define D18F3x4C_En_OFFSET                                      28
#define D18F3x4C_En_WIDTH                                       1
#define D18F3x4C_En_MASK                                        0x10000000
#define D18F3x4C_UC_OFFSET                                      29
#define D18F3x4C_UC_WIDTH                                       1
#define D18F3x4C_UC_MASK                                        0x20000000
#define D18F3x4C_Overflow_OFFSET                                30
#define D18F3x4C_Overflow_WIDTH                                 1
#define D18F3x4C_Overflow_MASK                                  0x40000000
#define D18F3x4C_Val_OFFSET                                     31
#define D18F3x4C_Val_WIDTH                                      1
#define D18F3x4C_Val_MASK                                       0x80000000

/// D18F3x4C
typedef union {
  struct {                                                              ///<
    UINT32                                                ErrCoreId:4 ; ///<
    UINT32                                                     Link:1 ; ///<
    UINT32                                           Reserved_39_37:3 ; ///<
    UINT32                                           Reserved_40_40:1 ; ///<
    UINT32                                                  SubLink:1 ; ///<
    UINT32                                           Reserved_43_42:2 ; ///<
    UINT32                                           Reserved_44_44:1 ; ///<
    UINT32                                           Reserved_54_45:10; ///<
    UINT32                                           Reserved_55_55:1 ; ///<
    UINT32                                             ErrCoreIdVal:1 ; ///<
    UINT32                                                      PCC:1 ; ///<
    UINT32                                                    AddrV:1 ; ///<
    UINT32                                                    MiscV:1 ; ///<
    UINT32                                                       En:1 ; ///<
    UINT32                                                       UC:1 ; ///<
    UINT32                                                 Overflow:1 ; ///<
    UINT32                                                      Val:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x4C_STRUCT;

// **** D18F3x50 Register Definition ****
// Address
#define D18F3x50_ADDRESS                                        0x50

// Type
#define D18F3x50_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x50_Reserved_0_0_OFFSET                            0
#define D18F3x50_Reserved_0_0_WIDTH                             1
#define D18F3x50_Reserved_0_0_MASK                              0x1
#define D18F3x50_ErrAddr_31_1__OFFSET                           1
#define D18F3x50_ErrAddr_31_1__WIDTH                            31
#define D18F3x50_ErrAddr_31_1__MASK                             0xfffffffe

/// D18F3x50
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                            ErrAddr_31_1_:31; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x50_STRUCT;

// **** D18F3x54 Register Definition ****
// Address
#define D18F3x54_ADDRESS                                        0x54

// Type
#define D18F3x54_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x54_ErrAddr_47_32__OFFSET                          0
#define D18F3x54_ErrAddr_47_32__WIDTH                           16
#define D18F3x54_ErrAddr_47_32__MASK                            0xffff
#define D18F3x54_Reserved_63_48_OFFSET                          16
#define D18F3x54_Reserved_63_48_WIDTH                           16
#define D18F3x54_Reserved_63_48_MASK                            0xffff0000

/// D18F3x54
typedef union {
  struct {                                                              ///<
    UINT32                                           ErrAddr_47_32_:16; ///<
    UINT32                                           Reserved_63_48:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x54_STRUCT;

// **** D18F3x64 Register Definition ****
// Address
#define D18F3x64_ADDRESS                                        0x64

// Type
#define D18F3x64_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x64_HtcEn_OFFSET                                   0
#define D18F3x64_HtcEn_WIDTH                                    1
#define D18F3x64_HtcEn_MASK                                     0x1
#define D18F3x64_Reserved_3_1_OFFSET                            1
#define D18F3x64_Reserved_3_1_WIDTH                             3
#define D18F3x64_Reserved_3_1_MASK                              0xe
#define D18F3x64_HtcAct_OFFSET                                  4
#define D18F3x64_HtcAct_WIDTH                                   1
#define D18F3x64_HtcAct_MASK                                    0x10
#define D18F3x64_HtcActSts_OFFSET                               5
#define D18F3x64_HtcActSts_WIDTH                                1
#define D18F3x64_HtcActSts_MASK                                 0x20
#define D18F3x64_PslApicHiEn_OFFSET                             6
#define D18F3x64_PslApicHiEn_WIDTH                              1
#define D18F3x64_PslApicHiEn_MASK                               0x40
#define D18F3x64_PslApicLoEn_OFFSET                             7
#define D18F3x64_PslApicLoEn_WIDTH                              1
#define D18F3x64_PslApicLoEn_MASK                               0x80
#define D18F3x64_Reserved_15_8_OFFSET                           8
#define D18F3x64_Reserved_15_8_WIDTH                            8
#define D18F3x64_Reserved_15_8_MASK                             0xff00
#define D18F3x64_HtcTmpLmt_OFFSET                               16
#define D18F3x64_HtcTmpLmt_WIDTH                                7
#define D18F3x64_HtcTmpLmt_MASK                                 0x7f0000
#define D18F3x64_HtcSlewSel_OFFSET                              23
#define D18F3x64_HtcSlewSel_WIDTH                               1
#define D18F3x64_HtcSlewSel_MASK                                0x800000
#define D18F3x64_HtcHystLmt_OFFSET                              24
#define D18F3x64_HtcHystLmt_WIDTH                               4
#define D18F3x64_HtcHystLmt_MASK                                0xf000000
#define D18F3x64_HtcPstateLimit_OFFSET                          28
#define D18F3x64_HtcPstateLimit_WIDTH                           3
#define D18F3x64_HtcPstateLimit_MASK                            0x70000000
#define D18F3x64_Reserved_31_31_OFFSET                          31
#define D18F3x64_Reserved_31_31_WIDTH                           1
#define D18F3x64_Reserved_31_31_MASK                            0x80000000

/// D18F3x64
typedef union {
  struct {                                                              ///<
    UINT32                                                    HtcEn:1 ; ///<
    UINT32                                             Reserved_3_1:3 ; ///<
    UINT32                                                   HtcAct:1 ; ///<
    UINT32                                                HtcActSts:1 ; ///<
    UINT32                                              PslApicHiEn:1 ; ///<
    UINT32                                              PslApicLoEn:1 ; ///<
    UINT32                                            Reserved_15_8:8 ; ///<
    UINT32                                                HtcTmpLmt:7 ; ///<
    UINT32                                               HtcSlewSel:1 ; ///<
    UINT32                                               HtcHystLmt:4 ; ///<
    UINT32                                           HtcPstateLimit:3 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x64_STRUCT;

// **** D18F3x68 Register Definition ****
// Address
#define D18F3x68_ADDRESS                                        0x68

// Type
#define D18F3x68_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x68_Reserved_4_0_OFFSET                            0
#define D18F3x68_Reserved_4_0_WIDTH                             5
#define D18F3x68_Reserved_4_0_MASK                              0x1f
#define D18F3x68_SwPstateLimitEn_OFFSET                         5
#define D18F3x68_SwPstateLimitEn_WIDTH                          1
#define D18F3x68_SwPstateLimitEn_MASK                           0x20
#define D18F3x68_Reserved_27_6_OFFSET                           6
#define D18F3x68_Reserved_27_6_WIDTH                            22
#define D18F3x68_Reserved_27_6_MASK                             0xfffffc0
#define D18F3x68_SwPstateLimit_OFFSET                           28
#define D18F3x68_SwPstateLimit_WIDTH                            3
#define D18F3x68_SwPstateLimit_MASK                             0x70000000
#define D18F3x68_Reserved_31_31_OFFSET                          31
#define D18F3x68_Reserved_31_31_WIDTH                           1
#define D18F3x68_Reserved_31_31_MASK                            0x80000000

/// D18F3x68
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_4_0:5 ; ///<
    UINT32                                          SwPstateLimitEn:1 ; ///<
    UINT32                                            Reserved_27_6:22; ///<
    UINT32                                            SwPstateLimit:3 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x68_STRUCT;

// **** D18F3x6C Register Definition ****
// Address
#define D18F3x6C_ADDRESS                                        0x6c

// Type
#define D18F3x6C_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x6C_UpReqDBC_OFFSET                                0
#define D18F3x6C_UpReqDBC_WIDTH                                 3
#define D18F3x6C_UpReqDBC_MASK                                  0x7
#define D18F3x6C_Reserved_3_3_OFFSET                            3
#define D18F3x6C_Reserved_3_3_WIDTH                             1
#define D18F3x6C_Reserved_3_3_MASK                              0x8
#define D18F3x6C_DnReqDBC_OFFSET                                4
#define D18F3x6C_DnReqDBC_WIDTH                                 2
#define D18F3x6C_DnReqDBC_MASK                                  0x30
#define D18F3x6C_DnRspDBC_OFFSET                                6
#define D18F3x6C_DnRspDBC_WIDTH                                 2
#define D18F3x6C_DnRspDBC_MASK                                  0xc0
#define D18F3x6C_Reserved_15_8_OFFSET                           8
#define D18F3x6C_Reserved_15_8_WIDTH                            8
#define D18F3x6C_Reserved_15_8_MASK                             0xff00
#define D18F3x6C_UpRspDBC_OFFSET                                16
#define D18F3x6C_UpRspDBC_WIDTH                                 3
#define D18F3x6C_UpRspDBC_MASK                                  0x70000
#define D18F3x6C_Reserved_27_19_OFFSET                          19
#define D18F3x6C_Reserved_27_19_WIDTH                           9
#define D18F3x6C_Reserved_27_19_MASK                            0xff80000
#define D18F3x6C_IsocRspDBC_OFFSET                              28
#define D18F3x6C_IsocRspDBC_WIDTH                               3
#define D18F3x6C_IsocRspDBC_MASK                                0x70000000
#define D18F3x6C_Reserved_31_31_OFFSET                          31
#define D18F3x6C_Reserved_31_31_WIDTH                           1
#define D18F3x6C_Reserved_31_31_MASK                            0x80000000

/// D18F3x6C
typedef union {
  struct {                                                              ///<
    UINT32                                                 UpReqDBC:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                 DnReqDBC:2 ; ///<
    UINT32                                                 DnRspDBC:2 ; ///<
    UINT32                                            Reserved_15_8:8 ; ///<
    UINT32                                                 UpRspDBC:3 ; ///<
    UINT32                                           Reserved_27_19:9 ; ///<
    UINT32                                               IsocRspDBC:3 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x6C_STRUCT;

// **** D18F3x70 Register Definition ****
// Address
#define D18F3x70_ADDRESS                                        0x70

// Type
#define D18F3x70_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x70_UpReqCBC_OFFSET                                0
#define D18F3x70_UpReqCBC_WIDTH                                 3
#define D18F3x70_UpReqCBC_MASK                                  0x7
#define D18F3x70_Reserved_3_3_OFFSET                            3
#define D18F3x70_Reserved_3_3_WIDTH                             1
#define D18F3x70_Reserved_3_3_MASK                              0x8
#define D18F3x70_DnReqCBC_OFFSET                                4
#define D18F3x70_DnReqCBC_WIDTH                                 2
#define D18F3x70_DnReqCBC_MASK                                  0x30
#define D18F3x70_DnRspCBC_OFFSET                                6
#define D18F3x70_DnRspCBC_WIDTH                                 2
#define D18F3x70_DnRspCBC_MASK                                  0xc0
#define D18F3x70_UpPreqCBC_OFFSET                               8
#define D18F3x70_UpPreqCBC_WIDTH                                3
#define D18F3x70_UpPreqCBC_MASK                                 0x700
#define D18F3x70_Reserved_11_11_OFFSET                          11
#define D18F3x70_Reserved_11_11_WIDTH                           1
#define D18F3x70_Reserved_11_11_MASK                            0x800
#define D18F3x70_DnPreqCBC_OFFSET                               12
#define D18F3x70_DnPreqCBC_WIDTH                                3
#define D18F3x70_DnPreqCBC_MASK                                 0x7000
#define D18F3x70_Reserved_15_15_OFFSET                          15
#define D18F3x70_Reserved_15_15_WIDTH                           1
#define D18F3x70_Reserved_15_15_MASK                            0x8000
#define D18F3x70_UpRspCBC_OFFSET                                16
#define D18F3x70_UpRspCBC_WIDTH                                 3
#define D18F3x70_UpRspCBC_MASK                                  0x70000
#define D18F3x70_Reserved_19_19_OFFSET                          19
#define D18F3x70_Reserved_19_19_WIDTH                           1
#define D18F3x70_Reserved_19_19_MASK                            0x80000
#define D18F3x70_IsocReqCBC_OFFSET                              20
#define D18F3x70_IsocReqCBC_WIDTH                               3
#define D18F3x70_IsocReqCBC_MASK                                0x700000
#define D18F3x70_Reserved_23_23_OFFSET                          23
#define D18F3x70_Reserved_23_23_WIDTH                           1
#define D18F3x70_Reserved_23_23_MASK                            0x800000
#define D18F3x70_IsocPreqCBC_OFFSET                             24
#define D18F3x70_IsocPreqCBC_WIDTH                              3
#define D18F3x70_IsocPreqCBC_MASK                               0x7000000
#define D18F3x70_Reserved_27_27_OFFSET                          27
#define D18F3x70_Reserved_27_27_WIDTH                           1
#define D18F3x70_Reserved_27_27_MASK                            0x8000000
#define D18F3x70_IsocRspCBC_OFFSET                              28
#define D18F3x70_IsocRspCBC_WIDTH                               3
#define D18F3x70_IsocRspCBC_MASK                                0x70000000
#define D18F3x70_Reserved_31_31_OFFSET                          31
#define D18F3x70_Reserved_31_31_WIDTH                           1
#define D18F3x70_Reserved_31_31_MASK                            0x80000000

/// D18F3x70
typedef union {
  struct {                                                              ///<
    UINT32                                                 UpReqCBC:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                 DnReqCBC:2 ; ///<
    UINT32                                                 DnRspCBC:2 ; ///<
    UINT32                                                UpPreqCBC:3 ; ///<
    UINT32                                           Reserved_11_11:1 ; ///<
    UINT32                                                DnPreqCBC:3 ; ///<
    UINT32                                           Reserved_15_15:1 ; ///<
    UINT32                                                 UpRspCBC:3 ; ///<
    UINT32                                           Reserved_19_19:1 ; ///<
    UINT32                                               IsocReqCBC:3 ; ///<
    UINT32                                           Reserved_23_23:1 ; ///<
    UINT32                                              IsocPreqCBC:3 ; ///<
    UINT32                                           Reserved_27_27:1 ; ///<
    UINT32                                               IsocRspCBC:3 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x70_STRUCT;

// **** D18F3x74 Register Definition ****
// Address
#define D18F3x74_ADDRESS                                        0x74

// Type
#define D18F3x74_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x74_UpReqCBC_OFFSET                                0
#define D18F3x74_UpReqCBC_WIDTH                                 3
#define D18F3x74_UpReqCBC_MASK                                  0x7
#define D18F3x74_Reserved_3_3_OFFSET                            3
#define D18F3x74_Reserved_3_3_WIDTH                             1
#define D18F3x74_Reserved_3_3_MASK                              0x8
#define D18F3x74_DnReqCBC_OFFSET                                4
#define D18F3x74_DnReqCBC_WIDTH                                 3
#define D18F3x74_DnReqCBC_MASK                                  0x70
#define D18F3x74_Reserved_7_7_OFFSET                            7
#define D18F3x74_Reserved_7_7_WIDTH                             1
#define D18F3x74_Reserved_7_7_MASK                              0x80
#define D18F3x74_UpPreqCBC_OFFSET                               8
#define D18F3x74_UpPreqCBC_WIDTH                                3
#define D18F3x74_UpPreqCBC_MASK                                 0x700
#define D18F3x74_Reserved_11_11_OFFSET                          11
#define D18F3x74_Reserved_11_11_WIDTH                           1
#define D18F3x74_Reserved_11_11_MASK                            0x800
#define D18F3x74_DnPreqCBC_OFFSET                               12
#define D18F3x74_DnPreqCBC_WIDTH                                3
#define D18F3x74_DnPreqCBC_MASK                                 0x7000
#define D18F3x74_Reserved_15_15_OFFSET                          15
#define D18F3x74_Reserved_15_15_WIDTH                           1
#define D18F3x74_Reserved_15_15_MASK                            0x8000
#define D18F3x74_ProbeCBC_OFFSET                                16
#define D18F3x74_ProbeCBC_WIDTH                                 4
#define D18F3x74_ProbeCBC_MASK                                  0xf0000
#define D18F3x74_IsocReqCBC_OFFSET                              20
#define D18F3x74_IsocReqCBC_WIDTH                               4
#define D18F3x74_IsocReqCBC_MASK                                0xf00000
#define D18F3x74_IsocPreqCBC_OFFSET                             24
#define D18F3x74_IsocPreqCBC_WIDTH                              3
#define D18F3x74_IsocPreqCBC_MASK                               0x7000000
#define D18F3x74_Reserved_27_27_OFFSET                          27
#define D18F3x74_Reserved_27_27_WIDTH                           1
#define D18F3x74_Reserved_27_27_MASK                            0x8000000
#define D18F3x74_DRReqCBC_OFFSET                                28
#define D18F3x74_DRReqCBC_WIDTH                                 4
#define D18F3x74_DRReqCBC_MASK                                  0xf0000000

/// D18F3x74
typedef union {
  struct {                                                              ///<
    UINT32                                                 UpReqCBC:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                                 DnReqCBC:3 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                                UpPreqCBC:3 ; ///<
    UINT32                                           Reserved_11_11:1 ; ///<
    UINT32                                                DnPreqCBC:3 ; ///<
    UINT32                                           Reserved_15_15:1 ; ///<
    UINT32                                                 ProbeCBC:4 ; ///<
    UINT32                                               IsocReqCBC:4 ; ///<
    UINT32                                              IsocPreqCBC:3 ; ///<
    UINT32                                           Reserved_27_27:1 ; ///<
    UINT32                                                 DRReqCBC:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x74_STRUCT;

// **** D18F3x78 Register Definition ****
// Address
#define D18F3x78_ADDRESS                                        0x78

// Type
#define D18F3x78_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x78_RspCBC_OFFSET                                  0
#define D18F3x78_RspCBC_WIDTH                                   5
#define D18F3x78_RspCBC_MASK                                    0x1f
#define D18F3x78_Reserved_7_5_OFFSET                            5
#define D18F3x78_Reserved_7_5_WIDTH                             3
#define D18F3x78_Reserved_7_5_MASK                              0xe0
#define D18F3x78_ProbeCBC_OFFSET                                8
#define D18F3x78_ProbeCBC_WIDTH                                 5
#define D18F3x78_ProbeCBC_MASK                                  0x1f00
#define D18F3x78_Reserved_15_13_OFFSET                          13
#define D18F3x78_Reserved_15_13_WIDTH                           3
#define D18F3x78_Reserved_15_13_MASK                            0xe000
#define D18F3x78_RspDBC_OFFSET                                  16
#define D18F3x78_RspDBC_WIDTH                                   6
#define D18F3x78_RspDBC_MASK                                    0x3f0000
#define D18F3x78_Reserved_31_22_OFFSET                          22
#define D18F3x78_Reserved_31_22_WIDTH                           10
#define D18F3x78_Reserved_31_22_MASK                            0xffc00000

/// D18F3x78
typedef union {
  struct {                                                              ///<
    UINT32                                                   RspCBC:5 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                                 ProbeCBC:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                                   RspDBC:6 ; ///<
    UINT32                                           Reserved_31_22:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x78_STRUCT;

// **** D18F3x7C Register Definition ****
// Address
#define D18F3x7C_ADDRESS                                        0x7c

// Type
#define D18F3x7C_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x7C_Xbar2SriFreeListCBC_OFFSET                     0
#define D18F3x7C_Xbar2SriFreeListCBC_WIDTH                      5
#define D18F3x7C_Xbar2SriFreeListCBC_MASK                       0x1f
#define D18F3x7C_Reserved_7_5_OFFSET                            5
#define D18F3x7C_Reserved_7_5_WIDTH                             3
#define D18F3x7C_Reserved_7_5_MASK                              0xe0
#define D18F3x7C_Sri2XbarFreeXreqCBC_OFFSET                     8
#define D18F3x7C_Sri2XbarFreeXreqCBC_WIDTH                      4
#define D18F3x7C_Sri2XbarFreeXreqCBC_MASK                       0xf00
#define D18F3x7C_Sri2XbarFreeRspCBC_OFFSET                      12
#define D18F3x7C_Sri2XbarFreeRspCBC_WIDTH                       4
#define D18F3x7C_Sri2XbarFreeRspCBC_MASK                        0xf000
#define D18F3x7C_Sri2XbarFreeXreqDBC_OFFSET                     16
#define D18F3x7C_Sri2XbarFreeXreqDBC_WIDTH                      4
#define D18F3x7C_Sri2XbarFreeXreqDBC_MASK                       0xf0000
#define D18F3x7C_Sri2XbarFreeRspDBC_OFFSET                      20
#define D18F3x7C_Sri2XbarFreeRspDBC_WIDTH                       3
#define D18F3x7C_Sri2XbarFreeRspDBC_MASK                        0x700000
#define D18F3x7C_ExtSrqFreeList_OFFSET                          23
#define D18F3x7C_ExtSrqFreeList_WIDTH                           4
#define D18F3x7C_ExtSrqFreeList_MASK                            0x7800000
#define D18F3x7C_Reserved_27_27_OFFSET                          27
#define D18F3x7C_Reserved_27_27_WIDTH                           1
#define D18F3x7C_Reserved_27_27_MASK                            0x8000000
#define D18F3x7C_Xbar2SriFreeListCBInc_OFFSET                   28
#define D18F3x7C_Xbar2SriFreeListCBInc_WIDTH                    3
#define D18F3x7C_Xbar2SriFreeListCBInc_MASK                     0x70000000
#define D18F3x7C_Reserved_31_31_OFFSET                          31
#define D18F3x7C_Reserved_31_31_WIDTH                           1
#define D18F3x7C_Reserved_31_31_MASK                            0x80000000

/// D18F3x7C
typedef union {
  struct {                                                              ///<
    UINT32                                      Xbar2SriFreeListCBC:5 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                      Sri2XbarFreeXreqCBC:4 ; ///<
    UINT32                                       Sri2XbarFreeRspCBC:4 ; ///<
    UINT32                                      Sri2XbarFreeXreqDBC:4 ; ///<
    UINT32                                       Sri2XbarFreeRspDBC:3 ; ///<
    UINT32                                           ExtSrqFreeList:4 ; ///<
    UINT32                                           Reserved_27_27:1 ; ///<
    UINT32                                    Xbar2SriFreeListCBInc:3 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x7C_STRUCT;

// **** D18F3x80 Register Definition ****
// Address
#define D18F3x80_ADDRESS                                        0x80

// Type
#define D18F3x80_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x80_CpuPrbEnSmafAct0_OFFSET                        0
#define D18F3x80_CpuPrbEnSmafAct0_WIDTH                         1
#define D18F3x80_CpuPrbEnSmafAct0_MASK                          0x1
#define D18F3x80_NbLowPwrEnSmafAct0_OFFSET                      1
#define D18F3x80_NbLowPwrEnSmafAct0_WIDTH                       1
#define D18F3x80_NbLowPwrEnSmafAct0_MASK                        0x2
#define D18F3x80_NbGateEnSmafAct0_OFFSET                        2
#define D18F3x80_NbGateEnSmafAct0_WIDTH                         1
#define D18F3x80_NbGateEnSmafAct0_MASK                          0x4
#define D18F3x80_Reserved_4_3_OFFSET                            3
#define D18F3x80_Reserved_4_3_WIDTH                             2
#define D18F3x80_Reserved_4_3_MASK                              0x18
#define D18F3x80_ClkDivisorSmafAct0_OFFSET                      5
#define D18F3x80_ClkDivisorSmafAct0_WIDTH                       3
#define D18F3x80_ClkDivisorSmafAct0_MASK                        0xe0
#define D18F3x80_CpuPrbEnSmafAct1_OFFSET                        8
#define D18F3x80_CpuPrbEnSmafAct1_WIDTH                         1
#define D18F3x80_CpuPrbEnSmafAct1_MASK                          0x100
#define D18F3x80_NbLowPwrEnSmafAct1_OFFSET                      9
#define D18F3x80_NbLowPwrEnSmafAct1_WIDTH                       1
#define D18F3x80_NbLowPwrEnSmafAct1_MASK                        0x200
#define D18F3x80_NbGateEnSmafAct1_OFFSET                        10
#define D18F3x80_NbGateEnSmafAct1_WIDTH                         1
#define D18F3x80_NbGateEnSmafAct1_MASK                          0x400
#define D18F3x80_Reserved_12_11_OFFSET                          11
#define D18F3x80_Reserved_12_11_WIDTH                           2
#define D18F3x80_Reserved_12_11_MASK                            0x1800
#define D18F3x80_ClkDivisorSmafAct1_OFFSET                      13
#define D18F3x80_ClkDivisorSmafAct1_WIDTH                       3
#define D18F3x80_ClkDivisorSmafAct1_MASK                        0xe000
#define D18F3x80_CpuPrbEnSmafAct2_OFFSET                        16
#define D18F3x80_CpuPrbEnSmafAct2_WIDTH                         1
#define D18F3x80_CpuPrbEnSmafAct2_MASK                          0x10000
#define D18F3x80_NbLowPwrEnSmafAct2_OFFSET                      17
#define D18F3x80_NbLowPwrEnSmafAct2_WIDTH                       1
#define D18F3x80_NbLowPwrEnSmafAct2_MASK                        0x20000
#define D18F3x80_NbGateEnSmafAct2_OFFSET                        18
#define D18F3x80_NbGateEnSmafAct2_WIDTH                         1
#define D18F3x80_NbGateEnSmafAct2_MASK                          0x40000
#define D18F3x80_Reserved_20_19_OFFSET                          19
#define D18F3x80_Reserved_20_19_WIDTH                           2
#define D18F3x80_Reserved_20_19_MASK                            0x180000
#define D18F3x80_ClkDivisorSmafAct2_OFFSET                      21
#define D18F3x80_ClkDivisorSmafAct2_WIDTH                       3
#define D18F3x80_ClkDivisorSmafAct2_MASK                        0xe00000
#define D18F3x80_CpuPrbEnSmafAct3_OFFSET                        24
#define D18F3x80_CpuPrbEnSmafAct3_WIDTH                         1
#define D18F3x80_CpuPrbEnSmafAct3_MASK                          0x1000000
#define D18F3x80_NbLowPwrEnSmafAct3_OFFSET                      25
#define D18F3x80_NbLowPwrEnSmafAct3_WIDTH                       1
#define D18F3x80_NbLowPwrEnSmafAct3_MASK                        0x2000000
#define D18F3x80_NbGateEnSmafAct3_OFFSET                        26
#define D18F3x80_NbGateEnSmafAct3_WIDTH                         1
#define D18F3x80_NbGateEnSmafAct3_MASK                          0x4000000
#define D18F3x80_Reserved_28_27_OFFSET                          27
#define D18F3x80_Reserved_28_27_WIDTH                           2
#define D18F3x80_Reserved_28_27_MASK                            0x18000000
#define D18F3x80_ClkDivisorSmafAct3_OFFSET                      29
#define D18F3x80_ClkDivisorSmafAct3_WIDTH                       3
#define D18F3x80_ClkDivisorSmafAct3_MASK                        0xe0000000

/// D18F3x80
typedef union {
  struct {                                                              ///<
    UINT32                                         CpuPrbEnSmafAct0:1 ; ///<
    UINT32                                       NbLowPwrEnSmafAct0:1 ; ///<
    UINT32                                         NbGateEnSmafAct0:1 ; ///<
    UINT32                                             Reserved_4_3:2 ; ///<
    UINT32                                       ClkDivisorSmafAct0:3 ; ///<
    UINT32                                         CpuPrbEnSmafAct1:1 ; ///<
    UINT32                                       NbLowPwrEnSmafAct1:1 ; ///<
    UINT32                                         NbGateEnSmafAct1:1 ; ///<
    UINT32                                           Reserved_12_11:2 ; ///<
    UINT32                                       ClkDivisorSmafAct1:3 ; ///<
    UINT32                                         CpuPrbEnSmafAct2:1 ; ///<
    UINT32                                       NbLowPwrEnSmafAct2:1 ; ///<
    UINT32                                         NbGateEnSmafAct2:1 ; ///<
    UINT32                                           Reserved_20_19:2 ; ///<
    UINT32                                       ClkDivisorSmafAct2:3 ; ///<
    UINT32                                         CpuPrbEnSmafAct3:1 ; ///<
    UINT32                                       NbLowPwrEnSmafAct3:1 ; ///<
    UINT32                                         NbGateEnSmafAct3:1 ; ///<
    UINT32                                           Reserved_28_27:2 ; ///<
    UINT32                                       ClkDivisorSmafAct3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x80_STRUCT;

// **** D18F3x84 Register Definition ****
// Address
#define D18F3x84_ADDRESS                                        0x84

// Type
#define D18F3x84_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x84_CpuPrbEnSmafAct4_OFFSET                        0
#define D18F3x84_CpuPrbEnSmafAct4_WIDTH                         1
#define D18F3x84_CpuPrbEnSmafAct4_MASK                          0x1
#define D18F3x84_NbLowPwrEnSmafAct4_OFFSET                      1
#define D18F3x84_NbLowPwrEnSmafAct4_WIDTH                       1
#define D18F3x84_NbLowPwrEnSmafAct4_MASK                        0x2
#define D18F3x84_NbGateEnSmafAct4_OFFSET                        2
#define D18F3x84_NbGateEnSmafAct4_WIDTH                         1
#define D18F3x84_NbGateEnSmafAct4_MASK                          0x4
#define D18F3x84_Reserved_4_3_OFFSET                            3
#define D18F3x84_Reserved_4_3_WIDTH                             2
#define D18F3x84_Reserved_4_3_MASK                              0x18
#define D18F3x84_ClkDivisorSmafAct4_OFFSET                      5
#define D18F3x84_ClkDivisorSmafAct4_WIDTH                       3
#define D18F3x84_ClkDivisorSmafAct4_MASK                        0xe0
#define D18F3x84_CpuPrbEnSmafAct5_OFFSET                        8
#define D18F3x84_CpuPrbEnSmafAct5_WIDTH                         1
#define D18F3x84_CpuPrbEnSmafAct5_MASK                          0x100
#define D18F3x84_NbLowPwrEnSmafAct5_OFFSET                      9
#define D18F3x84_NbLowPwrEnSmafAct5_WIDTH                       1
#define D18F3x84_NbLowPwrEnSmafAct5_MASK                        0x200
#define D18F3x84_NbGateEnSmafAct5_OFFSET                        10
#define D18F3x84_NbGateEnSmafAct5_WIDTH                         1
#define D18F3x84_NbGateEnSmafAct5_MASK                          0x400
#define D18F3x84_Reserved_12_11_OFFSET                          11
#define D18F3x84_Reserved_12_11_WIDTH                           2
#define D18F3x84_Reserved_12_11_MASK                            0x1800
#define D18F3x84_ClkDivisorSmafAct5_OFFSET                      13
#define D18F3x84_ClkDivisorSmafAct5_WIDTH                       3
#define D18F3x84_ClkDivisorSmafAct5_MASK                        0xe000
#define D18F3x84_CpuPrbEnSmafAct6_OFFSET                        16
#define D18F3x84_CpuPrbEnSmafAct6_WIDTH                         1
#define D18F3x84_CpuPrbEnSmafAct6_MASK                          0x10000
#define D18F3x84_NbLowPwrEnSmafAct6_OFFSET                      17
#define D18F3x84_NbLowPwrEnSmafAct6_WIDTH                       1
#define D18F3x84_NbLowPwrEnSmafAct6_MASK                        0x20000
#define D18F3x84_NbGateEnSmafAct6_OFFSET                        18
#define D18F3x84_NbGateEnSmafAct6_WIDTH                         1
#define D18F3x84_NbGateEnSmafAct6_MASK                          0x40000
#define D18F3x84_Reserved_20_19_OFFSET                          19
#define D18F3x84_Reserved_20_19_WIDTH                           2
#define D18F3x84_Reserved_20_19_MASK                            0x180000
#define D18F3x84_ClkDivisorSmafAct6_OFFSET                      21
#define D18F3x84_ClkDivisorSmafAct6_WIDTH                       3
#define D18F3x84_ClkDivisorSmafAct6_MASK                        0xe00000
#define D18F3x84_CpuPrbEnSmafAct7_OFFSET                        24
#define D18F3x84_CpuPrbEnSmafAct7_WIDTH                         1
#define D18F3x84_CpuPrbEnSmafAct7_MASK                          0x1000000
#define D18F3x84_NbLowPwrEnSmafAct7_OFFSET                      25
#define D18F3x84_NbLowPwrEnSmafAct7_WIDTH                       1
#define D18F3x84_NbLowPwrEnSmafAct7_MASK                        0x2000000
#define D18F3x84_NbGateEnSmafAct7_OFFSET                        26
#define D18F3x84_NbGateEnSmafAct7_WIDTH                         1
#define D18F3x84_NbGateEnSmafAct7_MASK                          0x4000000
#define D18F3x84_Reserved_28_27_OFFSET                          27
#define D18F3x84_Reserved_28_27_WIDTH                           2
#define D18F3x84_Reserved_28_27_MASK                            0x18000000
#define D18F3x84_ClkDivisorSmafAct7_OFFSET                      29
#define D18F3x84_ClkDivisorSmafAct7_WIDTH                       3
#define D18F3x84_ClkDivisorSmafAct7_MASK                        0xe0000000

/// D18F3x84
typedef union {
  struct {                                                              ///<
    UINT32                                         CpuPrbEnSmafAct4:1 ; ///<
    UINT32                                       NbLowPwrEnSmafAct4:1 ; ///<
    UINT32                                         NbGateEnSmafAct4:1 ; ///<
    UINT32                                             Reserved_4_3:2 ; ///<
    UINT32                                       ClkDivisorSmafAct4:3 ; ///<
    UINT32                                         CpuPrbEnSmafAct5:1 ; ///<
    UINT32                                       NbLowPwrEnSmafAct5:1 ; ///<
    UINT32                                         NbGateEnSmafAct5:1 ; ///<
    UINT32                                           Reserved_12_11:2 ; ///<
    UINT32                                       ClkDivisorSmafAct5:3 ; ///<
    UINT32                                         CpuPrbEnSmafAct6:1 ; ///<
    UINT32                                       NbLowPwrEnSmafAct6:1 ; ///<
    UINT32                                         NbGateEnSmafAct6:1 ; ///<
    UINT32                                           Reserved_20_19:2 ; ///<
    UINT32                                       ClkDivisorSmafAct6:3 ; ///<
    UINT32                                         CpuPrbEnSmafAct7:1 ; ///<
    UINT32                                       NbLowPwrEnSmafAct7:1 ; ///<
    UINT32                                         NbGateEnSmafAct7:1 ; ///<
    UINT32                                           Reserved_28_27:2 ; ///<
    UINT32                                       ClkDivisorSmafAct7:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x84_STRUCT;

// **** D18F3x88 Register Definition ****
// Address
#define D18F3x88_ADDRESS                                        0x88

// Type
#define D18F3x88_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x88_Reserved_30_0_OFFSET                           0
#define D18F3x88_Reserved_30_0_WIDTH                            31
#define D18F3x88_Reserved_30_0_MASK                             0x7fffffff
#define D18F3x88_DisCohLdtCfg_OFFSET                            31
#define D18F3x88_DisCohLdtCfg_WIDTH                             1
#define D18F3x88_DisCohLdtCfg_MASK                              0x80000000

/// D18F3x88
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_30_0:31; ///<
    UINT32                                             DisCohLdtCfg:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x88_STRUCT;

// **** D18F3x8C Register Definition ****
// Address
#define D18F3x8C_ADDRESS                                        0x8c

// Type
#define D18F3x8C_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3x8C_Reserved_35_32_OFFSET                          0
#define D18F3x8C_Reserved_35_32_WIDTH                           4
#define D18F3x8C_Reserved_35_32_MASK                            0xf
#define D18F3x8C_DisDatMsk_OFFSET                               4
#define D18F3x8C_DisDatMsk_WIDTH                                1
#define D18F3x8C_DisDatMsk_MASK                                 0x10
#define D18F3x8C_Reserved_44_37_OFFSET                          5
#define D18F3x8C_Reserved_44_37_WIDTH                           8
#define D18F3x8C_Reserved_44_37_MASK                            0x1fe0
#define D18F3x8C_DisUsSysMgtReqToNcHt_OFFSET                    13
#define D18F3x8C_DisUsSysMgtReqToNcHt_WIDTH                     1
#define D18F3x8C_DisUsSysMgtReqToNcHt_MASK                      0x2000
#define D18F3x8C_EnableCf8ExtCfg_OFFSET                         14
#define D18F3x8C_EnableCf8ExtCfg_WIDTH                          1
#define D18F3x8C_EnableCf8ExtCfg_MASK                           0x4000
#define D18F3x8C_Reserved_49_47_OFFSET                          15
#define D18F3x8C_Reserved_49_47_WIDTH                           3
#define D18F3x8C_Reserved_49_47_MASK                            0x38000
#define D18F3x8C_DisOrderRdRsp_OFFSET                           18
#define D18F3x8C_DisOrderRdRsp_WIDTH                            1
#define D18F3x8C_DisOrderRdRsp_MASK                             0x40000
#define D18F3x8C_Reserved_53_51_OFFSET                          19
#define D18F3x8C_Reserved_53_51_WIDTH                           3
#define D18F3x8C_Reserved_53_51_MASK                            0x380000
#define D18F3x8C_InitApicIdCpuIdLo_OFFSET                       22
#define D18F3x8C_InitApicIdCpuIdLo_WIDTH                        1
#define D18F3x8C_InitApicIdCpuIdLo_MASK                         0x400000
#define D18F3x8C_Reserved_63_55_OFFSET                          23
#define D18F3x8C_Reserved_63_55_WIDTH                           9
#define D18F3x8C_Reserved_63_55_MASK                            0xff800000

/// D18F3x8C
typedef union {
  struct {                                                              ///<
    UINT32                                           Reserved_35_32:4 ; ///<
    UINT32                                                DisDatMsk:1 ; ///<
    UINT32                                           Reserved_44_37:8 ; ///<
    UINT32                                     DisUsSysMgtReqToNcHt:1 ; ///<
    UINT32                                          EnableCf8ExtCfg:1 ; ///<
    UINT32                                           Reserved_49_47:3 ; ///<
    UINT32                                            DisOrderRdRsp:1 ; ///<
    UINT32                                           Reserved_53_51:3 ; ///<
    UINT32                                        InitApicIdCpuIdLo:1 ; ///<
    UINT32                                           Reserved_63_55:9 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x8C_STRUCT;

// **** D18F3xA0 Register Definition ****
// Address
#define D18F3xA0_ADDRESS                                        0xa0

// Type
#define D18F3xA0_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3xA0_PsiVid_6_0__OFFSET                             0
#define D18F3xA0_PsiVid_6_0__WIDTH                              7
#define D18F3xA0_PsiVid_6_0__MASK                               0x7f
#define D18F3xA0_PsiVidEn_OFFSET                                7
#define D18F3xA0_PsiVidEn_WIDTH                                 1
#define D18F3xA0_PsiVidEn_MASK                                  0x80
#define D18F3xA0_PsiVid_7__OFFSET                               8
#define D18F3xA0_PsiVid_7__WIDTH                                1
#define D18F3xA0_PsiVid_7__MASK                                 0x100
#define D18F3xA0_Reserved_10_9_OFFSET                           9
#define D18F3xA0_Reserved_10_9_WIDTH                            2
#define D18F3xA0_Reserved_10_9_MASK                             0x600
#define D18F3xA0_PllLockTime_OFFSET                             11
#define D18F3xA0_PllLockTime_WIDTH                              3
#define D18F3xA0_PllLockTime_MASK                               0x3800
#define D18F3xA0_Svi2HighFreqSel_OFFSET                         14
#define D18F3xA0_Svi2HighFreqSel_WIDTH                          1
#define D18F3xA0_Svi2HighFreqSel_MASK                           0x4000
#define D18F3xA0_Reserved_15_15_OFFSET                          15
#define D18F3xA0_Reserved_15_15_WIDTH                           1
#define D18F3xA0_Reserved_15_15_MASK                            0x8000
#define D18F3xA0_ConfigId_OFFSET                                16
#define D18F3xA0_ConfigId_WIDTH                                 12
#define D18F3xA0_ConfigId_MASK                                  0xfff0000
#define D18F3xA0_Reserved_30_28_OFFSET                          28
#define D18F3xA0_Reserved_30_28_WIDTH                           3
#define D18F3xA0_Reserved_30_28_MASK                            0x70000000
#define D18F3xA0_CofVidProg_OFFSET                              31
#define D18F3xA0_CofVidProg_WIDTH                               1
#define D18F3xA0_CofVidProg_MASK                                0x80000000

/// D18F3xA0
typedef union {
  struct {                                                              ///<
    UINT32                                              PsiVid_6_0_:7 ; ///<
    UINT32                                                 PsiVidEn:1 ; ///<
    UINT32                                                PsiVid_7_:1 ; ///<
    UINT32                                            Reserved_10_9:2 ; ///<
    UINT32                                              PllLockTime:3 ; ///<
    UINT32                                          Svi2HighFreqSel:1 ; ///<
    UINT32                                           Reserved_15_15:1 ; ///<
    UINT32                                                 ConfigId:12; ///<
    UINT32                                           Reserved_30_28:3 ; ///<
    UINT32                                               CofVidProg:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3xA0_STRUCT;

// **** D18F3xA4 Register Definition ****
// Address
#define D18F3xA4_ADDRESS                                        0xa4

// Type
#define D18F3xA4_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3xA4_PerStepTimeUp_OFFSET                           0
#define D18F3xA4_PerStepTimeUp_WIDTH                            5
#define D18F3xA4_PerStepTimeUp_MASK                             0x1f
#define D18F3xA4_TmpMaxDiffUp_OFFSET                            5
#define D18F3xA4_TmpMaxDiffUp_WIDTH                             2
#define D18F3xA4_TmpMaxDiffUp_MASK                              0x60
#define D18F3xA4_TmpSlewDnEn_OFFSET                             7
#define D18F3xA4_TmpSlewDnEn_WIDTH                              1
#define D18F3xA4_TmpSlewDnEn_MASK                               0x80
#define D18F3xA4_PerStepTimeDn_OFFSET                           8
#define D18F3xA4_PerStepTimeDn_WIDTH                            5
#define D18F3xA4_PerStepTimeDn_MASK                             0x1f00
#define D18F3xA4_Reserved_15_13_OFFSET                          13
#define D18F3xA4_Reserved_15_13_WIDTH                           3
#define D18F3xA4_Reserved_15_13_MASK                            0xe000
#define D18F3xA4_CurTmpTjSel_OFFSET                             16
#define D18F3xA4_CurTmpTjSel_WIDTH                              2
#define D18F3xA4_CurTmpTjSel_MASK                               0x30000
#define D18F3xA4_Reserved_19_18_OFFSET                          18
#define D18F3xA4_Reserved_19_18_WIDTH                           2
#define D18F3xA4_Reserved_19_18_MASK                            0xc0000
#define D18F3xA4_TcenPwrDnCc6En_OFFSET                          20
#define D18F3xA4_TcenPwrDnCc6En_WIDTH                           1
#define D18F3xA4_TcenPwrDnCc6En_MASK                            0x100000
#define D18F3xA4_CurTmp_OFFSET                                  21
#define D18F3xA4_CurTmp_WIDTH                                   11
#define D18F3xA4_CurTmp_MASK                                    0xffe00000

/// D18F3xA4
typedef union {
  struct {                                                              ///<
    UINT32                                            PerStepTimeUp:5 ; ///<
    UINT32                                             TmpMaxDiffUp:2 ; ///<
    UINT32                                              TmpSlewDnEn:1 ; ///<
    UINT32                                            PerStepTimeDn:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                              CurTmpTjSel:2 ; ///<
    UINT32                                           Reserved_19_18:2 ; ///<
    UINT32                                           TcenPwrDnCc6En:1 ; ///<
    UINT32                                                   CurTmp:11; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3xA4_STRUCT;

// **** D18F3xA8 Register Definition ****
// Address
#define D18F3xA8_ADDRESS                                        0xa8

// Type
#define D18F3xA8_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3xA8_Reserved_28_0_OFFSET                           0
#define D18F3xA8_Reserved_28_0_WIDTH                            29
#define D18F3xA8_Reserved_28_0_MASK                             0x1fffffff
#define D18F3xA8_PopDownPstate_OFFSET                           29
#define D18F3xA8_PopDownPstate_WIDTH                            3
#define D18F3xA8_PopDownPstate_MASK                             0xe0000000

/// D18F3xA8
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_28_0:29; ///<
    UINT32                                            PopDownPstate:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3xA8_STRUCT;


// **** D18F3xD4 Register Definition ****
// Address
#define D18F3xD4_ADDRESS                                        0xd4

// Type
#define D18F3xD4_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3xD4_MaxSwPstateCpuCof_OFFSET                       0
#define D18F3xD4_MaxSwPstateCpuCof_WIDTH                        6
#define D18F3xD4_MaxSwPstateCpuCof_MASK                         0x3f
#define D18F3xD4_Reserved_7_6_OFFSET                            6
#define D18F3xD4_Reserved_7_6_WIDTH                             2
#define D18F3xD4_Reserved_7_6_MASK                              0xc0
#define D18F3xD4_ClkRampHystSel_OFFSET                          8
#define D18F3xD4_ClkRampHystSel_WIDTH                           4
#define D18F3xD4_ClkRampHystSel_MASK                            0xf00
#define D18F3xD4_ClkRampHystCtl_OFFSET                          12
#define D18F3xD4_ClkRampHystCtl_WIDTH                           1
#define D18F3xD4_ClkRampHystCtl_MASK                            0x1000
#define D18F3xD4_Reserved_13_13_OFFSET                          13
#define D18F3xD4_Reserved_13_13_WIDTH                           1
#define D18F3xD4_Reserved_13_13_MASK                            0x2000
#define D18F3xD4_CacheFlushImmOnAllHalt_OFFSET                  14
#define D18F3xD4_CacheFlushImmOnAllHalt_WIDTH                   1
#define D18F3xD4_CacheFlushImmOnAllHalt_MASK                    0x4000
#define D18F3xD4_Reserved_17_15_OFFSET                          15
#define D18F3xD4_Reserved_17_15_WIDTH                           3
#define D18F3xD4_Reserved_17_15_MASK                            0x38000
#define D18F3xD4_Reserved_19_18_OFFSET                          18
#define D18F3xD4_Reserved_19_18_WIDTH                           2
#define D18F3xD4_Reserved_19_18_MASK                            0xc0000
#define D18F3xD4_PowerStepDown_OFFSET                           20
#define D18F3xD4_PowerStepDown_WIDTH                            4
#define D18F3xD4_PowerStepDown_MASK                             0xf00000
#define D18F3xD4_PowerStepUp_OFFSET                             24
#define D18F3xD4_PowerStepUp_WIDTH                              4
#define D18F3xD4_PowerStepUp_MASK                               0xf000000
#define D18F3xD4_NbClkDiv_OFFSET                                28
#define D18F3xD4_NbClkDiv_WIDTH                                 3
#define D18F3xD4_NbClkDiv_MASK                                  0x70000000
#define D18F3xD4_NbClkDivApplyAll_OFFSET                        31
#define D18F3xD4_NbClkDivApplyAll_WIDTH                         1
#define D18F3xD4_NbClkDivApplyAll_MASK                          0x80000000

/// D18F3xD4
typedef union {
  struct {                                                              ///<
    UINT32                                        MaxSwPstateCpuCof:6 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                           ClkRampHystSel:4 ; ///<
    UINT32                                           ClkRampHystCtl:1 ; ///<
    UINT32                                           Reserved_13_13:1 ; ///<
    UINT32                                   CacheFlushImmOnAllHalt:1 ; ///<
    UINT32                                           Reserved_17_15:3 ; ///<
    UINT32                                           Reserved_19_18:2 ; ///<
    UINT32                                            PowerStepDown:4 ; ///<
    UINT32                                              PowerStepUp:4 ; ///<
    UINT32                                                 NbClkDiv:3 ; ///<
    UINT32                                         NbClkDivApplyAll:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3xD4_STRUCT;

// **** D18F3xD8 Register Definition ****
// Address
#define D18F3xD8_ADDRESS                                        0xd8

// Type
#define D18F3xD8_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3xD8_Reserved_3_0_OFFSET                            0
#define D18F3xD8_Reserved_3_0_WIDTH                             4
#define D18F3xD8_Reserved_3_0_MASK                              0xf
#define D18F3xD8_VSRampSlamTime_OFFSET                          4
#define D18F3xD8_VSRampSlamTime_WIDTH                           3
#define D18F3xD8_VSRampSlamTime_MASK                            0x70
#define D18F3xD8_Reserved_31_7_OFFSET                           7
#define D18F3xD8_Reserved_31_7_WIDTH                            25
#define D18F3xD8_Reserved_31_7_MASK                             0xffffff80

/// D18F3xD8
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_3_0:4 ; ///<
    UINT32                                           VSRampSlamTime:3 ; ///<
    UINT32                                            Reserved_31_7:25; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3xD8_STRUCT;

// **** D18F3xDC Register Definition ****
// Address
#define D18F3xDC_ADDRESS                                        0xdc

// Type
#define D18F3xDC_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3xDC_Reserved_7_0_OFFSET                            0
#define D18F3xDC_Reserved_7_0_WIDTH                             8
#define D18F3xDC_Reserved_7_0_MASK                              0xff
#define D18F3xDC_PstateMaxVal_OFFSET                            8
#define D18F3xDC_PstateMaxVal_WIDTH                             3
#define D18F3xDC_PstateMaxVal_MASK                              0x700
#define D18F3xDC_Reserved_11_11_OFFSET                          11
#define D18F3xDC_Reserved_11_11_WIDTH                           1
#define D18F3xDC_Reserved_11_11_MASK                            0x800
#define D18F3xDC_NbsynPtrAdj_OFFSET                             12
#define D18F3xDC_NbsynPtrAdj_WIDTH                              3
#define D18F3xDC_NbsynPtrAdj_MASK                               0x7000
#define D18F3xDC_Reserved_15_15_OFFSET                          15
#define D18F3xDC_Reserved_15_15_WIDTH                           1
#define D18F3xDC_Reserved_15_15_MASK                            0x8000
#define D18F3xDC_CacheFlushOnHaltCtl_OFFSET                     16
#define D18F3xDC_CacheFlushOnHaltCtl_WIDTH                      3
#define D18F3xDC_CacheFlushOnHaltCtl_MASK                       0x70000
#define D18F3xDC_CacheFlushOnHaltTmr_OFFSET                     19
#define D18F3xDC_CacheFlushOnHaltTmr_WIDTH                      7
#define D18F3xDC_CacheFlushOnHaltTmr_MASK                       0x3f80000
#define D18F3xDC_IgnCpuPrbEn_OFFSET                             26
#define D18F3xDC_IgnCpuPrbEn_WIDTH                              1
#define D18F3xDC_IgnCpuPrbEn_MASK                               0x4000000
#define D18F3xDC_Reserved_31_27_OFFSET                          27
#define D18F3xDC_Reserved_31_27_WIDTH                           5
#define D18F3xDC_Reserved_31_27_MASK                            0xf8000000

/// D18F3xDC
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_7_0:8 ; ///<
    UINT32                                             PstateMaxVal:3 ; ///<
    UINT32                                           Reserved_11_11:1 ; ///<
    UINT32                                              NbsynPtrAdj:3 ; ///<
    UINT32                                           Reserved_15_15:1 ; ///<
    UINT32                                      CacheFlushOnHaltCtl:3 ; ///<
    UINT32                                      CacheFlushOnHaltTmr:7 ; ///<
    UINT32                                              IgnCpuPrbEn:1 ; ///<
    UINT32                                           Reserved_31_27:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3xDC_STRUCT;

// **** D18F3xE4 Register Definition ****
// Address
#define D18F3xE4_ADDRESS                                        0xe4

// Type
#define D18F3xE4_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3xE4_Reserved_0_0_OFFSET                            0
#define D18F3xE4_Reserved_0_0_WIDTH                             1
#define D18F3xE4_Reserved_0_0_MASK                              0x1
#define D18F3xE4_Thermtp_OFFSET                                 1
#define D18F3xE4_Thermtp_WIDTH                                  1
#define D18F3xE4_Thermtp_MASK                                   0x2
#define D18F3xE4_Reserved_2_2_OFFSET                            2
#define D18F3xE4_Reserved_2_2_WIDTH                             1
#define D18F3xE4_Reserved_2_2_MASK                              0x4
#define D18F3xE4_ThermtpSense_OFFSET                            3
#define D18F3xE4_ThermtpSense_WIDTH                             1
#define D18F3xE4_ThermtpSense_MASK                              0x8
#define D18F3xE4_Reserved_4_4_OFFSET                            4
#define D18F3xE4_Reserved_4_4_WIDTH                             1
#define D18F3xE4_Reserved_4_4_MASK                              0x10
#define D18F3xE4_ThermtpEn_OFFSET                               5
#define D18F3xE4_ThermtpEn_WIDTH                                1
#define D18F3xE4_ThermtpEn_MASK                                 0x20
#define D18F3xE4_Reserved_30_6_OFFSET                           6
#define D18F3xE4_Reserved_30_6_WIDTH                            25
#define D18F3xE4_Reserved_30_6_MASK                             0x7fffffc0
#define D18F3xE4_SwThermtp_OFFSET                               31
#define D18F3xE4_SwThermtp_WIDTH                                1
#define D18F3xE4_SwThermtp_MASK                                 0x80000000

/// D18F3xE4
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                  Thermtp:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                             ThermtpSense:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                                ThermtpEn:1 ; ///<
    UINT32                                            Reserved_30_6:25; ///<
    UINT32                                                SwThermtp:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3xE4_STRUCT;

// **** D18F3xE8 Register Definition ****
// Address
#define D18F3xE8_ADDRESS                                        0xe8

// Type
#define D18F3xE8_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3xE8_Reserved_0_0_OFFSET                            0
#define D18F3xE8_Reserved_0_0_WIDTH                             1
#define D18F3xE8_Reserved_0_0_MASK                              0x1
#define D18F3xE8_DualNode_OFFSET                                1
#define D18F3xE8_DualNode_WIDTH                                 1
#define D18F3xE8_DualNode_MASK                                  0x2
#define D18F3xE8_EightNode_OFFSET                               2
#define D18F3xE8_EightNode_WIDTH                                1
#define D18F3xE8_EightNode_MASK                                 0x4
#define D18F3xE8_ECC_OFFSET                                     3
#define D18F3xE8_ECC_WIDTH                                      1
#define D18F3xE8_ECC_MASK                                       0x8
#define D18F3xE8_ChipKill_OFFSET                                4
#define D18F3xE8_ChipKill_WIDTH                                 1
#define D18F3xE8_ChipKill_MASK                                  0x10
#define D18F3xE8_Reserved_7_5_OFFSET                            5
#define D18F3xE8_Reserved_7_5_WIDTH                             3
#define D18F3xE8_Reserved_7_5_MASK                              0xe0
#define D18F3xE8_MctCap_OFFSET                                  8
#define D18F3xE8_MctCap_WIDTH                                   1
#define D18F3xE8_MctCap_MASK                                    0x100
#define D18F3xE8_SvmCapable_OFFSET                              9
#define D18F3xE8_SvmCapable_WIDTH                               1
#define D18F3xE8_SvmCapable_MASK                                0x200
#define D18F3xE8_HtcCapable_OFFSET                              10
#define D18F3xE8_HtcCapable_WIDTH                               1
#define D18F3xE8_HtcCapable_MASK                                0x400
#define D18F3xE8_Reserved_11_11_OFFSET                          11
#define D18F3xE8_Reserved_11_11_WIDTH                           1
#define D18F3xE8_Reserved_11_11_MASK                            0x800
#define D18F3xE8_Reserved_13_12_OFFSET                          12
#define D18F3xE8_Reserved_13_12_WIDTH                           2
#define D18F3xE8_Reserved_13_12_MASK                            0x3000
#define D18F3xE8_MultVidPlane_OFFSET                            14
#define D18F3xE8_MultVidPlane_WIDTH                             1
#define D18F3xE8_MultVidPlane_MASK                              0x4000
#define D18F3xE8_Reserved_15_15_OFFSET                          15
#define D18F3xE8_Reserved_15_15_WIDTH                           1
#define D18F3xE8_Reserved_15_15_MASK                            0x8000
#define D18F3xE8_Reserved_18_16_OFFSET                          16
#define D18F3xE8_Reserved_18_16_WIDTH                           3
#define D18F3xE8_Reserved_18_16_MASK                            0x70000
#define D18F3xE8_x2Apic_OFFSET                                  19
#define D18F3xE8_x2Apic_WIDTH                                   1
#define D18F3xE8_x2Apic_MASK                                    0x80000
#define D18F3xE8_Reserved_23_20_OFFSET                          20
#define D18F3xE8_Reserved_23_20_WIDTH                           4
#define D18F3xE8_Reserved_23_20_MASK                            0xf00000
#define D18F3xE8_MemPstateCap_OFFSET                            24
#define D18F3xE8_MemPstateCap_WIDTH                             1
#define D18F3xE8_MemPstateCap_MASK                              0x1000000
#define D18F3xE8_L3Capable_OFFSET                               25
#define D18F3xE8_L3Capable_WIDTH                                1
#define D18F3xE8_L3Capable_MASK                                 0x2000000
#define D18F3xE8_Reserved_28_26_OFFSET                          26
#define D18F3xE8_Reserved_28_26_WIDTH                           3
#define D18F3xE8_Reserved_28_26_MASK                            0x1c000000
#define D18F3xE8_Reserved_31_29_OFFSET                          29
#define D18F3xE8_Reserved_31_29_WIDTH                           3
#define D18F3xE8_Reserved_31_29_MASK                            0xe0000000

/// D18F3xE8
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                 DualNode:1 ; ///<
    UINT32                                                EightNode:1 ; ///<
    UINT32                                                      ECC:1 ; ///<
    UINT32                                                 ChipKill:1 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                                   MctCap:1 ; ///<
    UINT32                                               SvmCapable:1 ; ///<
    UINT32                                               HtcCapable:1 ; ///<
    UINT32                                           Reserved_11_11:1 ; ///<
    UINT32                                           Reserved_13_12:2 ; ///<
    UINT32                                             MultVidPlane:1 ; ///<
    UINT32                                           Reserved_15_15:1 ; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                                   x2Apic:1 ; ///<
    UINT32                                           Reserved_23_20:4 ; ///<
    UINT32                                             MemPstateCap:1 ; ///<
    UINT32                                                L3Capable:1 ; ///<
    UINT32                                           Reserved_28_26:3 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3xE8_STRUCT;

// **** D18F3xFC Register Definition ****
// Address
#define D18F3xFC_ADDRESS                                        0xfc

// Type
#define D18F3xFC_TYPE                                           TYPE_D18F3
// Field Data
#define D18F3xFC_Stepping_OFFSET                                0
#define D18F3xFC_Stepping_WIDTH                                 4
#define D18F3xFC_Stepping_MASK                                  0xf
#define D18F3xFC_BaseModel_OFFSET                               4
#define D18F3xFC_BaseModel_WIDTH                                4
#define D18F3xFC_BaseModel_MASK                                 0xf0
#define D18F3xFC_BaseFamily_OFFSET                              8
#define D18F3xFC_BaseFamily_WIDTH                               4
#define D18F3xFC_BaseFamily_MASK                                0xf00
#define D18F3xFC_Reserved_15_12_OFFSET                          12
#define D18F3xFC_Reserved_15_12_WIDTH                           4
#define D18F3xFC_Reserved_15_12_MASK                            0xf000
#define D18F3xFC_ExtModel_OFFSET                                16
#define D18F3xFC_ExtModel_WIDTH                                 4
#define D18F3xFC_ExtModel_MASK                                  0xf0000
#define D18F3xFC_ExtFamily_OFFSET                               20
#define D18F3xFC_ExtFamily_WIDTH                                8
#define D18F3xFC_ExtFamily_MASK                                 0xff00000
#define D18F3xFC_Reserved_31_28_OFFSET                          28
#define D18F3xFC_Reserved_31_28_WIDTH                           4
#define D18F3xFC_Reserved_31_28_MASK                            0xf0000000

/// D18F3xFC
typedef union {
  struct {                                                              ///<
    UINT32                                                 Stepping:4 ; ///<
    UINT32                                                BaseModel:4 ; ///<
    UINT32                                               BaseFamily:4 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                                 ExtModel:4 ; ///<
    UINT32                                                ExtFamily:8 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3xFC_STRUCT;

// **** D18F3x140 Register Definition ****
// Address
#define D18F3x140_ADDRESS                                       0x140

// Type
#define D18F3x140_TYPE                                          TYPE_D18F3
// Field Data
#define D18F3x140_UpReqTok_OFFSET                               0
#define D18F3x140_UpReqTok_WIDTH                                2
#define D18F3x140_UpReqTok_MASK                                 0x3
#define D18F3x140_DnReqTok_OFFSET                               2
#define D18F3x140_DnReqTok_WIDTH                                2
#define D18F3x140_DnReqTok_MASK                                 0xc
#define D18F3x140_UpPreqTok_OFFSET                              4
#define D18F3x140_UpPreqTok_WIDTH                               2
#define D18F3x140_UpPreqTok_MASK                                0x30
#define D18F3x140_DnPreqTok_OFFSET                              6
#define D18F3x140_DnPreqTok_WIDTH                               2
#define D18F3x140_DnPreqTok_MASK                                0xc0
#define D18F3x140_UpRspTok_OFFSET                               8
#define D18F3x140_UpRspTok_WIDTH                                2
#define D18F3x140_UpRspTok_MASK                                 0x300
#define D18F3x140_DnRspTok_OFFSET                               10
#define D18F3x140_DnRspTok_WIDTH                                2
#define D18F3x140_DnRspTok_MASK                                 0xc00
#define D18F3x140_IsocReqTok_OFFSET                             12
#define D18F3x140_IsocReqTok_WIDTH                              2
#define D18F3x140_IsocReqTok_MASK                               0x3000
#define D18F3x140_IsocPreqTok_OFFSET                            14
#define D18F3x140_IsocPreqTok_WIDTH                             2
#define D18F3x140_IsocPreqTok_MASK                              0xc000
#define D18F3x140_IsocRspTok_OFFSET                             16
#define D18F3x140_IsocRspTok_WIDTH                              2
#define D18F3x140_IsocRspTok_MASK                               0x30000
#define D18F3x140_Reserved_19_18_OFFSET                         18
#define D18F3x140_Reserved_19_18_WIDTH                          2
#define D18F3x140_Reserved_19_18_MASK                           0xc0000
#define D18F3x140_FreeTok_OFFSET                                20
#define D18F3x140_FreeTok_WIDTH                                 4
#define D18F3x140_FreeTok_MASK                                  0xf00000
#define D18F3x140_Reserved_31_24_OFFSET                         24
#define D18F3x140_Reserved_31_24_WIDTH                          8
#define D18F3x140_Reserved_31_24_MASK                           0xff000000

/// D18F3x140
typedef union {
  struct {                                                              ///<
    UINT32                                                 UpReqTok:2 ; ///<
    UINT32                                                 DnReqTok:2 ; ///<
    UINT32                                                UpPreqTok:2 ; ///<
    UINT32                                                DnPreqTok:2 ; ///<
    UINT32                                                 UpRspTok:2 ; ///<
    UINT32                                                 DnRspTok:2 ; ///<
    UINT32                                               IsocReqTok:2 ; ///<
    UINT32                                              IsocPreqTok:2 ; ///<
    UINT32                                               IsocRspTok:2 ; ///<
    UINT32                                           Reserved_19_18:2 ; ///<
    UINT32                                                  FreeTok:4 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x140_STRUCT;

// **** D18F3x144 Register Definition ****
// Address
#define D18F3x144_ADDRESS                                       0x144

// Type
#define D18F3x144_TYPE                                          TYPE_D18F3
// Field Data
#define D18F3x144_RspTok_OFFSET                                 0
#define D18F3x144_RspTok_WIDTH                                  4
#define D18F3x144_RspTok_MASK                                   0xf
#define D18F3x144_ProbeTok_OFFSET                               4
#define D18F3x144_ProbeTok_WIDTH                                4
#define D18F3x144_ProbeTok_MASK                                 0xf0
#define D18F3x144_Reserved_31_8_OFFSET                          8
#define D18F3x144_Reserved_31_8_WIDTH                           24
#define D18F3x144_Reserved_31_8_MASK                            0xffffff00

/// D18F3x144
typedef union {
  struct {                                                              ///<
    UINT32                                                   RspTok:4 ; ///<
    UINT32                                                 ProbeTok:4 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x144_STRUCT;

// **** D18F3x148 Register Definition ****
// Address
#define D18F3x148_ADDRESS                                       0x148

// Type
#define D18F3x148_TYPE                                          TYPE_D18F3
// Field Data
#define D18F3x148_ReqTok0_OFFSET                                0
#define D18F3x148_ReqTok0_WIDTH                                 2
#define D18F3x148_ReqTok0_MASK                                  0x3
#define D18F3x148_PReqTok0_OFFSET                               2
#define D18F3x148_PReqTok0_WIDTH                                2
#define D18F3x148_PReqTok0_MASK                                 0xc
#define D18F3x148_RspTok0_OFFSET                                4
#define D18F3x148_RspTok0_WIDTH                                 2
#define D18F3x148_RspTok0_MASK                                  0x30
#define D18F3x148_ProbeTok0_OFFSET                              6
#define D18F3x148_ProbeTok0_WIDTH                               2
#define D18F3x148_ProbeTok0_MASK                                0xc0
#define D18F3x148_IsocReqTok0_OFFSET                            8
#define D18F3x148_IsocReqTok0_WIDTH                             2
#define D18F3x148_IsocReqTok0_MASK                              0x300
#define D18F3x148_IsocPreqTok0_OFFSET                           10
#define D18F3x148_IsocPreqTok0_WIDTH                            2
#define D18F3x148_IsocPreqTok0_MASK                             0xc00
#define D18F3x148_IsocRspTok0_OFFSET                            12
#define D18F3x148_IsocRspTok0_WIDTH                             2
#define D18F3x148_IsocRspTok0_MASK                              0x3000
#define D18F3x148_FreeTok_1_0__OFFSET                           14
#define D18F3x148_FreeTok_1_0__WIDTH                            2
#define D18F3x148_FreeTok_1_0__MASK                             0xc000
#define D18F3x148_ReqTok1_OFFSET                                16
#define D18F3x148_ReqTok1_WIDTH                                 2
#define D18F3x148_ReqTok1_MASK                                  0x30000
#define D18F3x148_PReqTok1_OFFSET                               18
#define D18F3x148_PReqTok1_WIDTH                                2
#define D18F3x148_PReqTok1_MASK                                 0xc0000
#define D18F3x148_RspTok1_OFFSET                                20
#define D18F3x148_RspTok1_WIDTH                                 2
#define D18F3x148_RspTok1_MASK                                  0x300000
#define D18F3x148_ProbeTok1_OFFSET                              22
#define D18F3x148_ProbeTok1_WIDTH                               2
#define D18F3x148_ProbeTok1_MASK                                0xc00000
#define D18F3x148_IsocReqTok1_OFFSET                            24
#define D18F3x148_IsocReqTok1_WIDTH                             1
#define D18F3x148_IsocReqTok1_MASK                              0x1000000
#define D18F3x148_Reserved_25_25_OFFSET                         25
#define D18F3x148_Reserved_25_25_WIDTH                          1
#define D18F3x148_Reserved_25_25_MASK                           0x2000000
#define D18F3x148_IsocPreqTok1_OFFSET                           26
#define D18F3x148_IsocPreqTok1_WIDTH                            1
#define D18F3x148_IsocPreqTok1_MASK                             0x4000000
#define D18F3x148_Reserved_27_27_OFFSET                         27
#define D18F3x148_Reserved_27_27_WIDTH                          1
#define D18F3x148_Reserved_27_27_MASK                           0x8000000
#define D18F3x148_IsocRspTok1_OFFSET                            28
#define D18F3x148_IsocRspTok1_WIDTH                             1
#define D18F3x148_IsocRspTok1_MASK                              0x10000000
#define D18F3x148_Reserved_29_29_OFFSET                         29
#define D18F3x148_Reserved_29_29_WIDTH                          1
#define D18F3x148_Reserved_29_29_MASK                           0x20000000
#define D18F3x148_FreeTok_3_2__OFFSET                           30
#define D18F3x148_FreeTok_3_2__WIDTH                            2
#define D18F3x148_FreeTok_3_2__MASK                             0xc0000000

/// D18F3x148
typedef union {
  struct {                                                              ///<
    UINT32                                                  ReqTok0:2 ; ///<
    UINT32                                                 PReqTok0:2 ; ///<
    UINT32                                                  RspTok0:2 ; ///<
    UINT32                                                ProbeTok0:2 ; ///<
    UINT32                                              IsocReqTok0:2 ; ///<
    UINT32                                             IsocPreqTok0:2 ; ///<
    UINT32                                              IsocRspTok0:2 ; ///<
    UINT32                                             FreeTok_1_0_:2 ; ///<
    UINT32                                                  ReqTok1:2 ; ///<
    UINT32                                                 PReqTok1:2 ; ///<
    UINT32                                                  RspTok1:2 ; ///<
    UINT32                                                ProbeTok1:2 ; ///<
    UINT32                                              IsocReqTok1:1 ; ///<
    UINT32                                           Reserved_25_25:1 ; ///<
    UINT32                                             IsocPreqTok1:1 ; ///<
    UINT32                                           Reserved_27_27:1 ; ///<
    UINT32                                              IsocRspTok1:1 ; ///<
    UINT32                                           Reserved_29_29:1 ; ///<
    UINT32                                             FreeTok_3_2_:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x148_STRUCT;

// **** D18F3x17C Register Definition ****
// Address
#define D18F3x17C_ADDRESS                                       0x17c

// Type
#define D18F3x17C_TYPE                                          TYPE_D18F3
// Field Data
#define D18F3x17C_SPQPrbFreeCBC_OFFSET                          0
#define D18F3x17C_SPQPrbFreeCBC_WIDTH                           4
#define D18F3x17C_SPQPrbFreeCBC_MASK                            0xf
#define D18F3x17C_Reserved_31_4_OFFSET                          4
#define D18F3x17C_Reserved_31_4_WIDTH                           28
#define D18F3x17C_Reserved_31_4_MASK                            0xfffffff0

/// D18F3x17C
typedef union {
  struct {                                                              ///<
    UINT32                                            SPQPrbFreeCBC:4 ; ///<
    UINT32                                            Reserved_31_4:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x17C_STRUCT;

// **** D18F3x180 Register Definition ****
// Address
#define D18F3x180_ADDRESS                                       0x180

// Type
#define D18F3x180_TYPE                                          TYPE_D18F3
// Field Data
#define D18F3x180_Reserved_1_0_OFFSET                           0
#define D18F3x180_Reserved_1_0_WIDTH                            2
#define D18F3x180_Reserved_1_0_MASK                             0x3
#define D18F3x180_WDTCntSel_3__OFFSET                           2
#define D18F3x180_WDTCntSel_3__WIDTH                            1
#define D18F3x180_WDTCntSel_3__MASK                             0x4
#define D18F3x180_ChgDatErrToTgtAbort_OFFSET                    3
#define D18F3x180_ChgDatErrToTgtAbort_WIDTH                     1
#define D18F3x180_ChgDatErrToTgtAbort_MASK                      0x8
#define D18F3x180_ChgMstAbortToNoErr_OFFSET                     4
#define D18F3x180_ChgMstAbortToNoErr_WIDTH                      1
#define D18F3x180_ChgMstAbortToNoErr_MASK                       0x10
#define D18F3x180_DisPciCfgCpuMstAbortRsp_OFFSET                5
#define D18F3x180_DisPciCfgCpuMstAbortRsp_WIDTH                 1
#define D18F3x180_DisPciCfgCpuMstAbortRsp_MASK                  0x20
#define D18F3x180_SyncFloodOnDatErr_OFFSET                      6
#define D18F3x180_SyncFloodOnDatErr_WIDTH                       1
#define D18F3x180_SyncFloodOnDatErr_MASK                        0x40
#define D18F3x180_SyncFloodOnTgtAbortErr_OFFSET                 7
#define D18F3x180_SyncFloodOnTgtAbortErr_WIDTH                  1
#define D18F3x180_SyncFloodOnTgtAbortErr_MASK                   0x80
#define D18F3x180_PwP2pDatErrLclPropDis_OFFSET                  18
#define D18F3x180_PwP2pDatErrLclPropDis_WIDTH                   1
#define D18F3x180_PwP2pDatErrLclPropDis_MASK                    0x40000
#define D18F3x180_PwP2pDatErrRmtPropDis_OFFSET                  19
#define D18F3x180_PwP2pDatErrRmtPropDis_WIDTH                   1
#define D18F3x180_PwP2pDatErrRmtPropDis_MASK                    0x80000
#define D18F3x180_SyncFloodOnL3LeakErr_OFFSET                   20
#define D18F3x180_SyncFloodOnL3LeakErr_WIDTH                    1
#define D18F3x180_SyncFloodOnL3LeakErr_MASK                     0x100000
#define D18F3x180_SyncFloodOnCpuLeakErr_OFFSET                  21
#define D18F3x180_SyncFloodOnCpuLeakErr_WIDTH                   1
#define D18F3x180_SyncFloodOnCpuLeakErr_MASK                    0x200000
#define D18F3x180_SyncFloodOnTblWalkErr_OFFSET                  22
#define D18F3x180_SyncFloodOnTblWalkErr_WIDTH                   1
#define D18F3x180_SyncFloodOnTblWalkErr_MASK                    0x400000
#define D18F3x180_Reserved_23_23_OFFSET                         23
#define D18F3x180_Reserved_23_23_WIDTH                          1
#define D18F3x180_Reserved_23_23_MASK                           0x800000
#define D18F3x180_McaLogErrAddrWdtErr_OFFSET                    24
#define D18F3x180_McaLogErrAddrWdtErr_WIDTH                     1
#define D18F3x180_McaLogErrAddrWdtErr_MASK                      0x1000000
#define D18F3x180_Reserved_25_25_OFFSET                         25
#define D18F3x180_Reserved_25_25_WIDTH                          1
#define D18F3x180_Reserved_25_25_MASK                           0x2000000
#define D18F3x180_ChgUcToCeEn_OFFSET                            26
#define D18F3x180_ChgUcToCeEn_WIDTH                             1
#define D18F3x180_ChgUcToCeEn_MASK                              0x4000000
#define D18F3x180_Reserved_31_27_OFFSET                         27
#define D18F3x180_Reserved_31_27_WIDTH                          5
#define D18F3x180_Reserved_31_27_MASK                           0xf8000000

/// D18F3x180
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_1_0:2 ; ///<
    UINT32                                             WDTCntSel_3_:1 ; ///<
    UINT32                                      ChgDatErrToTgtAbort:1 ; ///<
    UINT32                                       ChgMstAbortToNoErr:1 ; ///<
    UINT32                                  DisPciCfgCpuMstAbortRsp:1 ; ///<
    UINT32                                        SyncFloodOnDatErr:1 ; ///<
    UINT32                                   SyncFloodOnTgtAbortErr:1 ; ///<
    UINT32                                      :1 ; ///<
    UINT32                                     :1 ; ///<
    UINT32                                             :1 ; ///<
    UINT32                                           :7 ; ///<
    UINT32                                    PwP2pDatErrLclPropDis:1 ; ///<
    UINT32                                    PwP2pDatErrRmtPropDis:1 ; ///<
    UINT32                                     SyncFloodOnL3LeakErr:1 ; ///<
    UINT32                                    SyncFloodOnCpuLeakErr:1 ; ///<
    UINT32                                    SyncFloodOnTblWalkErr:1 ; ///<
    UINT32                                           Reserved_23_23:1 ; ///<
    UINT32                                      McaLogErrAddrWdtErr:1 ; ///<
    UINT32                                           Reserved_25_25:1 ; ///<
    UINT32                                              ChgUcToCeEn:1 ; ///<
    UINT32                                           Reserved_31_27:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x180_STRUCT;

// **** D18F3x190 Register Definition ****
// Address
#define D18F3x190_ADDRESS                                       0x190

// Type
#define D18F3x190_TYPE                                          TYPE_D18F3
// Field Data
#define D18F3x190_DisCore_OFFSET                                0
#define D18F3x190_DisCore_WIDTH                                 32
#define D18F3x190_DisCore_MASK                                  0xffffffff

/// D18F3x190
typedef union {
  struct {                                                              ///<
    UINT32                                                  DisCore:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x190_STRUCT;

// **** D18F3x1A0 Register Definition ****
// Address
#define D18F3x1A0_ADDRESS                                       0x1a0

// Type
#define D18F3x1A0_TYPE                                          TYPE_D18F3
// Field Data
#define D18F3x1A0_CpuCmdBufCnt_OFFSET                           0
#define D18F3x1A0_CpuCmdBufCnt_WIDTH                            3
#define D18F3x1A0_CpuCmdBufCnt_MASK                             0x7
#define D18F3x1A0_Reserved_3_3_OFFSET                           3
#define D18F3x1A0_Reserved_3_3_WIDTH                            1
#define D18F3x1A0_Reserved_3_3_MASK                             0x8
#define D18F3x1A0_Reserved_8_4_OFFSET                           4
#define D18F3x1A0_Reserved_8_4_WIDTH                            5
#define D18F3x1A0_Reserved_8_4_MASK                             0x1f0
#define D18F3x1A0_Reserved_11_9_OFFSET                          9
#define D18F3x1A0_Reserved_11_9_WIDTH                           3
#define D18F3x1A0_Reserved_11_9_MASK                            0xe00
#define D18F3x1A0_Reserved_14_12_OFFSET                         12
#define D18F3x1A0_Reserved_14_12_WIDTH                          3
#define D18F3x1A0_Reserved_14_12_MASK                           0x7000
#define D18F3x1A0_Reserved_15_15_OFFSET                         15
#define D18F3x1A0_Reserved_15_15_WIDTH                          1
#define D18F3x1A0_Reserved_15_15_MASK                           0x8000
#define D18F3x1A0_CpuToNbFreeBufCnt_OFFSET                      16
#define D18F3x1A0_CpuToNbFreeBufCnt_WIDTH                       2
#define D18F3x1A0_CpuToNbFreeBufCnt_MASK                        0x30000
#define D18F3x1A0_Reserved_31_18_OFFSET                         18
#define D18F3x1A0_Reserved_31_18_WIDTH                          14
#define D18F3x1A0_Reserved_31_18_MASK                           0xfffc0000

/// D18F3x1A0
typedef union {
  struct {                                                              ///<
    UINT32                                             CpuCmdBufCnt:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                             Reserved_8_4:5 ; ///<
    UINT32                                            Reserved_11_9:3 ; ///<
    UINT32                                           Reserved_14_12:3 ; ///<
    UINT32                                           Reserved_15_15:1 ; ///<
    UINT32                                        CpuToNbFreeBufCnt:2 ; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x1A0_STRUCT;

// **** D18F3x1CC Register Definition ****
// Address
#define D18F3x1CC_ADDRESS                                       0x1cc

// Type
#define D18F3x1CC_TYPE                                          TYPE_D18F3
// Field Data
#define D18F3x1CC_LvtOffset_OFFSET                              0
#define D18F3x1CC_LvtOffset_WIDTH                               4
#define D18F3x1CC_LvtOffset_MASK                                0xf
#define D18F3x1CC_Reserved_7_4_OFFSET                           4
#define D18F3x1CC_Reserved_7_4_WIDTH                            4
#define D18F3x1CC_Reserved_7_4_MASK                             0xf0
#define D18F3x1CC_LvtOffsetVal_OFFSET                           8
#define D18F3x1CC_LvtOffsetVal_WIDTH                            1
#define D18F3x1CC_LvtOffsetVal_MASK                             0x100
#define D18F3x1CC_Reserved_31_9_OFFSET                          9
#define D18F3x1CC_Reserved_31_9_WIDTH                           23
#define D18F3x1CC_Reserved_31_9_MASK                            0xfffffe00

/// D18F3x1CC
typedef union {
  struct {                                                              ///<
    UINT32                                                LvtOffset:4 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                             LvtOffsetVal:1 ; ///<
    UINT32                                            Reserved_31_9:23; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x1CC_STRUCT;


// **** D18F3x1FC Register Definition ****
// Address
#define D18F3x1FC_ADDRESS                                       0x1fc

// Type
#define D18F3x1FC_TYPE                                          TYPE_D18F3
// Field Data
#define D18F3x1FC_DiDtMode_OFFSET                               0
#define D18F3x1FC_DiDtMode_WIDTH                                1
#define D18F3x1FC_DiDtMode_MASK                                 0x1
#define D18F3x1FC_DiDtCfg0_OFFSET                               1
#define D18F3x1FC_DiDtCfg0_WIDTH                                5
#define D18F3x1FC_DiDtCfg0_MASK                                 0x3e
#define D18F3x1FC_DiDtCfg1_OFFSET                               6
#define D18F3x1FC_DiDtCfg1_WIDTH                                8
#define D18F3x1FC_DiDtCfg1_MASK                                 0x3fc0
#define D18F3x1FC_DiDtCfg2_OFFSET                               14
#define D18F3x1FC_DiDtCfg2_WIDTH                                2
#define D18F3x1FC_DiDtCfg2_MASK                                 0xc000
#define D18F3x1FC_Reserved_16_16_OFFSET                         16
#define D18F3x1FC_Reserved_16_16_WIDTH                          1
#define D18F3x1FC_Reserved_16_16_MASK                           0x10000
#define D18F3x1FC_DiDtCfg4_OFFSET                               17
#define D18F3x1FC_DiDtCfg4_WIDTH                                3
#define D18F3x1FC_DiDtCfg4_MASK                                 0xe0000
#define D18F3x1FC_Reserved_23_20_OFFSET                         20
#define D18F3x1FC_Reserved_23_20_WIDTH                          4
#define D18F3x1FC_Reserved_23_20_MASK                           0xf00000
#define D18F3x1FC_SWDllCapTableEn_OFFSET                        24
#define D18F3x1FC_SWDllCapTableEn_WIDTH                         1
#define D18F3x1FC_SWDllCapTableEn_MASK                          0x1000000
#define D18F3x1FC_DllProcFreqCtlIndex2Rate50_OFFSET             25
#define D18F3x1FC_DllProcFreqCtlIndex2Rate50_WIDTH              4
#define D18F3x1FC_DllProcFreqCtlIndex2Rate50_MASK               0x1e000000

/// D18F3x1FC
typedef union {
  struct {                                                              ///<
    UINT32                                                 DiDtMode:1 ; ///<
    UINT32                                                 DiDtCfg0:5 ; ///<
    UINT32                                                 DiDtCfg1:8 ; ///<
    UINT32                                                 DiDtCfg2:2 ; ///<
    UINT32                                           Reserved_16_16:1 ; ///<
    UINT32                                                 DiDtCfg4:3 ; ///<
    UINT32                                           Reserved_23_20:4 ; ///<
    UINT32                                          SWDllCapTableEn:1 ; ///<
    UINT32                               DllProcFreqCtlIndex2Rate50:4 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F3x1FC_STRUCT;

// **** D18F4x00 Register Definition ****
// Address
#define D18F4x00_ADDRESS                                        0x0

// Type
#define D18F4x00_TYPE                                           TYPE_D18F4
// Field Data
#define D18F4x00_VendorID_OFFSET                                0
#define D18F4x00_VendorID_WIDTH                                 16
#define D18F4x00_VendorID_MASK                                  0xffff
#define D18F4x00_DeviceID_OFFSET                                16
#define D18F4x00_DeviceID_WIDTH                                 16
#define D18F4x00_DeviceID_MASK                                  0xffff0000

/// D18F4x00
typedef union {
  struct {                                                              ///<
    UINT32                                                 VendorID:16; ///<
    UINT32                                                 DeviceID:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F4x00_STRUCT;

// **** D18F4x04 Register Definition ****
// Address
#define D18F4x04_ADDRESS                                        0x4

// Type
#define D18F4x04_TYPE                                           TYPE_D18F4
// Field Data
#define D18F4x04_Command_OFFSET                                 0
#define D18F4x04_Command_WIDTH                                  16
#define D18F4x04_Command_MASK                                   0xffff
#define D18F4x04_Status_OFFSET                                  16
#define D18F4x04_Status_WIDTH                                   16
#define D18F4x04_Status_MASK                                    0xffff0000

/// D18F4x04
typedef union {
  struct {                                                              ///<
    UINT32                                                  Command:16; ///<
    UINT32                                                   Status:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F4x04_STRUCT;

// **** D18F4x08 Register Definition ****
// Address
#define D18F4x08_ADDRESS                                        0x8

// Type
#define D18F4x08_TYPE                                           TYPE_D18F4
// Field Data
#define D18F4x08_RevID_OFFSET                                   0
#define D18F4x08_RevID_WIDTH                                    8
#define D18F4x08_RevID_MASK                                     0xff
#define D18F4x08_ClassCode_OFFSET                               8
#define D18F4x08_ClassCode_WIDTH                                24
#define D18F4x08_ClassCode_MASK                                 0xffffff00

/// D18F4x08
typedef union {
  struct {                                                              ///<
    UINT32                                                    RevID:8 ; ///<
    UINT32                                                ClassCode:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F4x08_STRUCT;

// **** D18F4x0C Register Definition ****
// Address
#define D18F4x0C_ADDRESS                                        0xc

// Type
#define D18F4x0C_TYPE                                           TYPE_D18F4
// Field Data
#define D18F4x0C_HeaderTypeReg_OFFSET                           0
#define D18F4x0C_HeaderTypeReg_WIDTH                            32
#define D18F4x0C_HeaderTypeReg_MASK                             0xffffffff

/// D18F4x0C
typedef union {
  struct {                                                              ///<
    UINT32                                            HeaderTypeReg:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F4x0C_STRUCT;

// **** D18F4x34 Register Definition ****
// Address
#define D18F4x34_ADDRESS                                        0x34

// Type
#define D18F4x34_TYPE                                           TYPE_D18F4
// Field Data
#define D18F4x34_CapPtr_OFFSET                                  0
#define D18F4x34_CapPtr_WIDTH                                   8
#define D18F4x34_CapPtr_MASK                                    0xff
#define D18F4x34_Reserved_31_8_OFFSET                           8
#define D18F4x34_Reserved_31_8_WIDTH                            24
#define D18F4x34_Reserved_31_8_MASK                             0xffffff00

/// D18F4x34
typedef union {
  struct {                                                              ///<
    UINT32                                                   CapPtr:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F4x34_STRUCT;

// **** D18F4x108 Register Definition ****
// Address
#define D18F4x108_ADDRESS                                       0x108

// Type
#define D18F4x108_TYPE                                          TYPE_D18F4
// Field Data
#define D18F4x108_Reserved_31_0_OFFSET                          0
#define D18F4x108_Reserved_31_0_WIDTH                           32
#define D18F4x108_Reserved_31_0_MASK                            0xffffffff

/// D18F4x108
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_31_0:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F4x108_STRUCT;

// **** D18F4x10C Register Definition ****
// Address
#define D18F4x10C_ADDRESS                                       0x10c

// Type
#define D18F4x10C_TYPE                                          TYPE_D18F4
// Field Data
#define D18F4x10C_NodeTdpLimit_OFFSET                           0
#define D18F4x10C_NodeTdpLimit_WIDTH                            12
#define D18F4x10C_NodeTdpLimit_MASK                             0xfff
#define D18F4x10C_Reserved_31_12_OFFSET                         12
#define D18F4x10C_Reserved_31_12_WIDTH                          20
#define D18F4x10C_Reserved_31_12_MASK                           0xfffff000

/// D18F4x10C
typedef union {
  struct {                                                              ///<
    UINT32                                             NodeTdpLimit:12; ///<
    UINT32                                           Reserved_31_12:20; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F4x10C_STRUCT;

// **** D18F4x110 Register Definition ****
// Address
#define D18F4x110_ADDRESS                                       0x110

// Type
#define D18F4x110_TYPE                                          TYPE_D18F4
// Field Data
#define D18F4x110_CSampleTimer_OFFSET                           0
#define D18F4x110_CSampleTimer_WIDTH                            12
#define D18F4x110_CSampleTimer_MASK                             0xfff
#define D18F4x110_Reserved_12_12_OFFSET                         12
#define D18F4x110_Reserved_12_12_WIDTH                          1
#define D18F4x110_Reserved_12_12_MASK                           0x1000
#define D18F4x110_MinResTmr_OFFSET                              13
#define D18F4x110_MinResTmr_WIDTH                               8
#define D18F4x110_MinResTmr_MASK                                0x1fe000
#define D18F4x110_Reserved_31_21_OFFSET                         21
#define D18F4x110_Reserved_31_21_WIDTH                          11
#define D18F4x110_Reserved_31_21_MASK                           0xffe00000

/// D18F4x110
typedef union {
  struct {                                                              ///<
    UINT32                                             CSampleTimer:12; ///<
    UINT32                                           Reserved_12_12:1 ; ///<
    UINT32                                                MinResTmr:8 ; ///<
    UINT32                                           Reserved_31_21:11; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F4x110_STRUCT;

// **** D18F4x118 Register Definition ****
// Address
#define D18F4x118_ADDRESS                                       0x118

// Type
#define D18F4x118_TYPE                                          TYPE_D18F4
// Field Data
#define D18F4x118_CpuPrbEnCstAct0_OFFSET                        0
#define D18F4x118_CpuPrbEnCstAct0_WIDTH                         1
#define D18F4x118_CpuPrbEnCstAct0_MASK                          0x1
#define D18F4x118_CacheFlushEnCstAct0_OFFSET                    1
#define D18F4x118_CacheFlushEnCstAct0_WIDTH                     1
#define D18F4x118_CacheFlushEnCstAct0_MASK                      0x2
#define D18F4x118_CacheFlushTmrSelCstAct0_OFFSET                2
#define D18F4x118_CacheFlushTmrSelCstAct0_WIDTH                 2
#define D18F4x118_CacheFlushTmrSelCstAct0_MASK                  0xc
#define D18F4x118_Reserved_4_4_OFFSET                           4
#define D18F4x118_Reserved_4_4_WIDTH                            1
#define D18F4x118_Reserved_4_4_MASK                             0x10
#define D18F4x118_ClkDivisorCstAct0_OFFSET                      5
#define D18F4x118_ClkDivisorCstAct0_WIDTH                       3
#define D18F4x118_ClkDivisorCstAct0_MASK                        0xe0
#define D18F4x118_PwrGateEnCstAct0_OFFSET                       8
#define D18F4x118_PwrGateEnCstAct0_WIDTH                        1
#define D18F4x118_PwrGateEnCstAct0_MASK                         0x100
#define D18F4x118_PwrOffEnCstAct0_OFFSET                        9
#define D18F4x118_PwrOffEnCstAct0_WIDTH                         1
#define D18F4x118_PwrOffEnCstAct0_MASK                          0x200
#define D18F4x118_NbPwrGate0_OFFSET                             10
#define D18F4x118_NbPwrGate0_WIDTH                              1
#define D18F4x118_NbPwrGate0_MASK                               0x400
#define D18F4x118_NbClkGate0_OFFSET                             11
#define D18F4x118_NbClkGate0_WIDTH                              1
#define D18F4x118_NbClkGate0_MASK                               0x800
#define D18F4x118_SelfRefr0_OFFSET                              12
#define D18F4x118_SelfRefr0_WIDTH                               1
#define D18F4x118_SelfRefr0_MASK                                0x1000
#define D18F4x118_SelfRefrEarly0_OFFSET                         13
#define D18F4x118_SelfRefrEarly0_WIDTH                          1
#define D18F4x118_SelfRefrEarly0_MASK                           0x2000
#define D18F4x118_Reserved_15_14_OFFSET                         14
#define D18F4x118_Reserved_15_14_WIDTH                          2
#define D18F4x118_Reserved_15_14_MASK                           0xc000
#define D18F4x118_CpuPrbEnCstAct1_OFFSET                        16
#define D18F4x118_CpuPrbEnCstAct1_WIDTH                         1
#define D18F4x118_CpuPrbEnCstAct1_MASK                          0x10000
#define D18F4x118_CacheFlushEnCstAct1_OFFSET                    17
#define D18F4x118_CacheFlushEnCstAct1_WIDTH                     1
#define D18F4x118_CacheFlushEnCstAct1_MASK                      0x20000
#define D18F4x118_CacheFlushTmrSelCstAct1_OFFSET                18
#define D18F4x118_CacheFlushTmrSelCstAct1_WIDTH                 2
#define D18F4x118_CacheFlushTmrSelCstAct1_MASK                  0xc0000
#define D18F4x118_Reserved_20_20_OFFSET                         20
#define D18F4x118_Reserved_20_20_WIDTH                          1
#define D18F4x118_Reserved_20_20_MASK                           0x100000
#define D18F4x118_ClkDivisorCstAct1_OFFSET                      21
#define D18F4x118_ClkDivisorCstAct1_WIDTH                       3
#define D18F4x118_ClkDivisorCstAct1_MASK                        0xe00000
#define D18F4x118_PwrGateEnCstAct1_OFFSET                       24
#define D18F4x118_PwrGateEnCstAct1_WIDTH                        1
#define D18F4x118_PwrGateEnCstAct1_MASK                         0x1000000
#define D18F4x118_PwrOffEnCstAct1_OFFSET                        25
#define D18F4x118_PwrOffEnCstAct1_WIDTH                         1
#define D18F4x118_PwrOffEnCstAct1_MASK                          0x2000000
#define D18F4x118_NbPwrGate1_OFFSET                             26
#define D18F4x118_NbPwrGate1_WIDTH                              1
#define D18F4x118_NbPwrGate1_MASK                               0x4000000
#define D18F4x118_NbClkGate1_OFFSET                             27
#define D18F4x118_NbClkGate1_WIDTH                              1
#define D18F4x118_NbClkGate1_MASK                               0x8000000
#define D18F4x118_SelfRefr1_OFFSET                              28
#define D18F4x118_SelfRefr1_WIDTH                               1
#define D18F4x118_SelfRefr1_MASK                                0x10000000
#define D18F4x118_SelfRefrEarly1_OFFSET                         29
#define D18F4x118_SelfRefrEarly1_WIDTH                          1
#define D18F4x118_SelfRefrEarly1_MASK                           0x20000000
#define D18F4x118_Reserved_31_30_OFFSET                         30
#define D18F4x118_Reserved_31_30_WIDTH                          2
#define D18F4x118_Reserved_31_30_MASK                           0xc0000000

/// D18F4x118
typedef union {
  struct {                                                              ///<
    UINT32                                          CpuPrbEnCstAct0:1 ; ///<
    UINT32                                      CacheFlushEnCstAct0:1 ; ///<
    UINT32                                  CacheFlushTmrSelCstAct0:2 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                        ClkDivisorCstAct0:3 ; ///<
    UINT32                                         PwrGateEnCstAct0:1 ; ///<
    UINT32                                          PwrOffEnCstAct0:1 ; ///<
    UINT32                                               NbPwrGate0:1 ; ///<
    UINT32                                               NbClkGate0:1 ; ///<
    UINT32                                                SelfRefr0:1 ; ///<
    UINT32                                           SelfRefrEarly0:1 ; ///<
    UINT32                                           Reserved_15_14:2 ; ///<
    UINT32                                          CpuPrbEnCstAct1:1 ; ///<
    UINT32                                      CacheFlushEnCstAct1:1 ; ///<
    UINT32                                  CacheFlushTmrSelCstAct1:2 ; ///<
    UINT32                                           Reserved_20_20:1 ; ///<
    UINT32                                        ClkDivisorCstAct1:3 ; ///<
    UINT32                                         PwrGateEnCstAct1:1 ; ///<
    UINT32                                          PwrOffEnCstAct1:1 ; ///<
    UINT32                                               NbPwrGate1:1 ; ///<
    UINT32                                               NbClkGate1:1 ; ///<
    UINT32                                                SelfRefr1:1 ; ///<
    UINT32                                           SelfRefrEarly1:1 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F4x118_STRUCT;

// **** D18F4x11C Register Definition ****
// Address
#define D18F4x11C_ADDRESS                                       0x11c

// Type
#define D18F4x11C_TYPE                                          TYPE_D18F4
// Field Data
#define D18F4x11C_CpuPrbEnCstAct2_OFFSET                        0
#define D18F4x11C_CpuPrbEnCstAct2_WIDTH                         1
#define D18F4x11C_CpuPrbEnCstAct2_MASK                          0x1
#define D18F4x11C_CacheFlushEnCstAct2_OFFSET                    1
#define D18F4x11C_CacheFlushEnCstAct2_WIDTH                     1
#define D18F4x11C_CacheFlushEnCstAct2_MASK                      0x2
#define D18F4x11C_CacheFlushTmrSelCstAct2_OFFSET                2
#define D18F4x11C_CacheFlushTmrSelCstAct2_WIDTH                 2
#define D18F4x11C_CacheFlushTmrSelCstAct2_MASK                  0xc
#define D18F4x11C_Reserved_4_4_OFFSET                           4
#define D18F4x11C_Reserved_4_4_WIDTH                            1
#define D18F4x11C_Reserved_4_4_MASK                             0x10
#define D18F4x11C_ClkDivisorCstAct2_OFFSET                      5
#define D18F4x11C_ClkDivisorCstAct2_WIDTH                       3
#define D18F4x11C_ClkDivisorCstAct2_MASK                        0xe0
#define D18F4x11C_PwrGateEnCstAct2_OFFSET                       8
#define D18F4x11C_PwrGateEnCstAct2_WIDTH                        1
#define D18F4x11C_PwrGateEnCstAct2_MASK                         0x100
#define D18F4x11C_PwrOffEnCstAct2_OFFSET                        9
#define D18F4x11C_PwrOffEnCstAct2_WIDTH                         1
#define D18F4x11C_PwrOffEnCstAct2_MASK                          0x200
#define D18F4x11C_NbPwrGate2_OFFSET                             10
#define D18F4x11C_NbPwrGate2_WIDTH                              1
#define D18F4x11C_NbPwrGate2_MASK                               0x400
#define D18F4x11C_NbClkGate2_OFFSET                             11
#define D18F4x11C_NbClkGate2_WIDTH                              1
#define D18F4x11C_NbClkGate2_MASK                               0x800
#define D18F4x11C_SelfRefr2_OFFSET                              12
#define D18F4x11C_SelfRefr2_WIDTH                               1
#define D18F4x11C_SelfRefr2_MASK                                0x1000
#define D18F4x11C_SelfRefrEarly2_OFFSET                         13
#define D18F4x11C_SelfRefrEarly2_WIDTH                          1
#define D18F4x11C_SelfRefrEarly2_MASK                           0x2000
#define D18F4x11C_Reserved_31_14_OFFSET                         14
#define D18F4x11C_Reserved_31_14_WIDTH                          18
#define D18F4x11C_Reserved_31_14_MASK                           0xffffc000

/// D18F4x11C
typedef union {
  struct {                                                              ///<
    UINT32                                          CpuPrbEnCstAct2:1 ; ///<
    UINT32                                      CacheFlushEnCstAct2:1 ; ///<
    UINT32                                  CacheFlushTmrSelCstAct2:2 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                                        ClkDivisorCstAct2:3 ; ///<
    UINT32                                         PwrGateEnCstAct2:1 ; ///<
    UINT32                                          PwrOffEnCstAct2:1 ; ///<
    UINT32                                               NbPwrGate2:1 ; ///<
    UINT32                                               NbClkGate2:1 ; ///<
    UINT32                                                SelfRefr2:1 ; ///<
    UINT32                                           SelfRefrEarly2:1 ; ///<
    UINT32                                           Reserved_31_14:18; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F4x11C_STRUCT;

// **** D18F4x124 Register Definition ****
// Address
#define D18F4x124_ADDRESS                                       0x124

// Type
#define D18F4x124_TYPE                                          TYPE_D18F4
// Field Data
#define D18F4x124_Reserved_21_0_OFFSET                          0
#define D18F4x124_Reserved_21_0_WIDTH                           22
#define D18F4x124_Reserved_21_0_MASK                            0x3fffff
#define D18F4x124_IntMonPC6En_OFFSET                            22
#define D18F4x124_IntMonPC6En_WIDTH                             1
#define D18F4x124_IntMonPC6En_MASK                              0x400000
#define D18F4x124_IntMonPC6Limit_OFFSET                         23
#define D18F4x124_IntMonPC6Limit_WIDTH                          4
#define D18F4x124_IntMonPC6Limit_MASK                           0x7800000
#define D18F4x124_Reserved_31_27_OFFSET                         27
#define D18F4x124_Reserved_31_27_WIDTH                          5
#define D18F4x124_Reserved_31_27_MASK                           0xf8000000

/// D18F4x124
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_21_0:22; ///<
    UINT32                                              IntMonPC6En:1 ; ///<
    UINT32                                           IntMonPC6Limit:4 ; ///<
    UINT32                                           Reserved_31_27:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F4x124_STRUCT;

// **** D18F4x128 Register Definition ****
// Address
#define D18F4x128_ADDRESS                                       0x128

// Type
#define D18F4x128_TYPE                                          TYPE_D18F4
// Field Data
#define D18F4x128_Reserved_0_0_OFFSET                           0
#define D18F4x128_Reserved_0_0_WIDTH                            1
#define D18F4x128_Reserved_0_0_MASK                             0x1
#define D18F4x128_CoreCstatePolicy_OFFSET                       1
#define D18F4x128_CoreCstatePolicy_WIDTH                        1
#define D18F4x128_CoreCstatePolicy_MASK                         0x2
#define D18F4x128_HaltCstateIndex_OFFSET                        2
#define D18F4x128_HaltCstateIndex_WIDTH                         3
#define D18F4x128_HaltCstateIndex_MASK                          0x1c
#define D18F4x128_CacheFlushTmr_OFFSET                          5
#define D18F4x128_CacheFlushTmr_WIDTH                           7
#define D18F4x128_CacheFlushTmr_MASK                            0xfe0
#define D18F4x128_Reserved_17_12_OFFSET                         12
#define D18F4x128_Reserved_17_12_WIDTH                          6
#define D18F4x128_Reserved_17_12_MASK                           0x3f000
#define D18F4x128_CacheFlushSucMonThreshold_OFFSET              18
#define D18F4x128_CacheFlushSucMonThreshold_WIDTH               3
#define D18F4x128_CacheFlushSucMonThreshold_MASK                0x1c0000
#define D18F4x128_Reserved_30_21_OFFSET                         21
#define D18F4x128_Reserved_30_21_WIDTH                          10
#define D18F4x128_Reserved_30_21_MASK                           0x7fe00000
#define D18F4x128_CstateMsgDis_OFFSET                           31
#define D18F4x128_CstateMsgDis_WIDTH                            1
#define D18F4x128_CstateMsgDis_MASK                             0x80000000

/// D18F4x128
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                         CoreCstatePolicy:1 ; ///<
    UINT32                                          HaltCstateIndex:3 ; ///<
    UINT32                                            CacheFlushTmr:7 ; ///<
    UINT32                                           Reserved_17_12:6 ; ///<
    UINT32                                CacheFlushSucMonThreshold:3 ; ///<
    UINT32                                           Reserved_30_21:10; ///<
    UINT32                                             CstateMsgDis:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F4x128_STRUCT;

// **** D18F4x13C Register Definition ****
// Address
#define D18F4x13C_ADDRESS                                       0x13c

// Type
#define D18F4x13C_TYPE                                          TYPE_D18F4
// Field Data
#define D18F4x13C_SmuPstateLimitEn_OFFSET                       0
#define D18F4x13C_SmuPstateLimitEn_WIDTH                        1
#define D18F4x13C_SmuPstateLimitEn_MASK                         0x1
#define D18F4x13C_SmuPstateLimit_OFFSET                         1
#define D18F4x13C_SmuPstateLimit_WIDTH                          3
#define D18F4x13C_SmuPstateLimit_MASK                           0xe
#define D18F4x13C_Reserved_31_4_OFFSET                          4
#define D18F4x13C_Reserved_31_4_WIDTH                           28
#define D18F4x13C_Reserved_31_4_MASK                            0xfffffff0

/// D18F4x13C
typedef union {
  struct {                                                              ///<
    UINT32                                         SmuPstateLimitEn:1 ; ///<
    UINT32                                           SmuPstateLimit:3 ; ///<
    UINT32                                            Reserved_31_4:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F4x13C_STRUCT;

// **** D18F4x15C Register Definition ****
// Address
#define D18F4x15C_ADDRESS                                       0x15c

// Type
#define D18F4x15C_TYPE                                          TYPE_D18F4
// Field Data
#define D18F4x15C_BoostSrc_OFFSET                               0
#define D18F4x15C_BoostSrc_WIDTH                                2
#define D18F4x15C_BoostSrc_MASK                                 0x3
#define D18F4x15C_NumBoostStates_OFFSET                         2
#define D18F4x15C_NumBoostStates_WIDTH                          3
#define D18F4x15C_NumBoostStates_MASK                           0x1c
#define D18F4x15C_Reserved_6_5_OFFSET                           5
#define D18F4x15C_Reserved_6_5_WIDTH                            2
#define D18F4x15C_Reserved_6_5_MASK                             0x60
#define D18F4x15C_ApmMasterEn_OFFSET                            7
#define D18F4x15C_ApmMasterEn_WIDTH                             1
#define D18F4x15C_ApmMasterEn_MASK                              0x80
#define D18F4x15C_Reserved_27_8_OFFSET                          8
#define D18F4x15C_Reserved_27_8_WIDTH                           20
#define D18F4x15C_Reserved_27_8_MASK                            0xfffff00
#define D18F4x15C_Reserved_30_28_OFFSET                         28
#define D18F4x15C_Reserved_30_28_WIDTH                          3
#define D18F4x15C_Reserved_30_28_MASK                           0x70000000
#define D18F4x15C_BoostLock_OFFSET                              31
#define D18F4x15C_BoostLock_WIDTH                               1
#define D18F4x15C_BoostLock_MASK                                0x80000000

/// D18F4x15C
typedef union {
  struct {                                                              ///<
    UINT32                                                 BoostSrc:2 ; ///<
    UINT32                                           NumBoostStates:3 ; ///<
    UINT32                                             Reserved_6_5:2 ; ///<
    UINT32                                              ApmMasterEn:1 ; ///<
    UINT32                                            Reserved_27_8:20; ///<
    UINT32                                           Reserved_30_28:3 ; ///<
    UINT32                                                BoostLock:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F4x15C_STRUCT;


// **** D18F4x164 Register Definition ****
// Address
#define D18F4x164_ADDRESS                                       0x164

// Type
#define D18F4x164_TYPE                                          TYPE_D18F4
// Field Data
#define D18F4x164_FixedErrata_OFFSET                            0
#define D18F4x164_FixedErrata_WIDTH                             32
#define D18F4x164_FixedErrata_MASK                              0xffffffff

/// D18F4x164
typedef union {
  struct {                                                              ///<
    UINT32                                              FixedErrata:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F4x164_STRUCT;

// **** D18F4x16C Register Definition ****
// Address
#define D18F4x16C_ADDRESS                                       0x16c

// Type
#define D18F4x16C_TYPE                                          TYPE_D18F4
// Field Data
#define D18F4x16C_CstateBoost_OFFSET                            6
#define D18F4x16C_CstateBoost_WIDTH                             3
#define D18F4x16C_CstateBoost_MASK                              0x1c0
#define D18F4x16C_CstateCnt_OFFSET                              9
#define D18F4x16C_CstateCnt_WIDTH                               3
#define D18F4x16C_CstateCnt_MASK                                0xe00
#define D18F4x16C_Reserved_31_12_OFFSET                         12
#define D18F4x16C_Reserved_31_12_WIDTH                          20
#define D18F4x16C_Reserved_31_12_MASK                           0xfffff000

/// D18F4x16C
typedef union {
  struct {                                                              ///<
    UINT32                                             :6 ; ///<
    UINT32                                              CstateBoost:3 ; ///<
    UINT32                                                CstateCnt:3 ; ///<
    UINT32                                           Reserved_31_12:20; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F4x16C_STRUCT;


// **** D18F5x00 Register Definition ****
// Address
#define D18F5x00_ADDRESS                                        0x0

// Type
#define D18F5x00_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x00_VendorID_OFFSET                                0
#define D18F5x00_VendorID_WIDTH                                 16
#define D18F5x00_VendorID_MASK                                  0xffff
#define D18F5x00_DeviceID_OFFSET                                16
#define D18F5x00_DeviceID_WIDTH                                 16
#define D18F5x00_DeviceID_MASK                                  0xffff0000

/// D18F5x00
typedef union {
  struct {                                                              ///<
    UINT32                                                 VendorID:16; ///<
    UINT32                                                 DeviceID:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x00_STRUCT;

// **** D18F5x04 Register Definition ****
// Address
#define D18F5x04_ADDRESS                                        0x4

// Type
#define D18F5x04_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x04_Command_OFFSET                                 0
#define D18F5x04_Command_WIDTH                                  16
#define D18F5x04_Command_MASK                                   0xffff
#define D18F5x04_Status_OFFSET                                  16
#define D18F5x04_Status_WIDTH                                   16
#define D18F5x04_Status_MASK                                    0xffff0000

/// D18F5x04
typedef union {
  struct {                                                              ///<
    UINT32                                                  Command:16; ///<
    UINT32                                                   Status:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x04_STRUCT;

// **** D18F5x08 Register Definition ****
// Address
#define D18F5x08_ADDRESS                                        0x8

// Type
#define D18F5x08_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x08_RevID_OFFSET                                   0
#define D18F5x08_RevID_WIDTH                                    8
#define D18F5x08_RevID_MASK                                     0xff
#define D18F5x08_ClassCode_OFFSET                               8
#define D18F5x08_ClassCode_WIDTH                                24
#define D18F5x08_ClassCode_MASK                                 0xffffff00

/// D18F5x08
typedef union {
  struct {                                                              ///<
    UINT32                                                    RevID:8 ; ///<
    UINT32                                                ClassCode:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x08_STRUCT;

// **** D18F5x0C Register Definition ****
// Address
#define D18F5x0C_ADDRESS                                        0xc

// Type
#define D18F5x0C_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x0C_HeaderTypeReg_OFFSET                           0
#define D18F5x0C_HeaderTypeReg_WIDTH                            32
#define D18F5x0C_HeaderTypeReg_MASK                             0xffffffff

/// D18F5x0C
typedef union {
  struct {                                                              ///<
    UINT32                                            HeaderTypeReg:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x0C_STRUCT;

// **** D18F5x34 Register Definition ****
// Address
#define D18F5x34_ADDRESS                                        0x34

// Type
#define D18F5x34_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x34_CapPtr_OFFSET                                  0
#define D18F5x34_CapPtr_WIDTH                                   8
#define D18F5x34_CapPtr_MASK                                    0xff
#define D18F5x34_Reserved_31_8_OFFSET                           8
#define D18F5x34_Reserved_31_8_WIDTH                            24
#define D18F5x34_Reserved_31_8_MASK                             0xffffff00

/// D18F5x34
typedef union {
  struct {                                                              ///<
    UINT32                                                   CapPtr:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x34_STRUCT;

// **** D18F5x40 Register Definition ****
// Address
#define D18F5x40_ADDRESS                                        0x40

// Type
#define D18F5x40_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x40_EventSelect_7_0__OFFSET                        0
#define D18F5x40_EventSelect_7_0__WIDTH                         8
#define D18F5x40_EventSelect_7_0__MASK                          0xff
#define D18F5x40_UnitMask_OFFSET                                8
#define D18F5x40_UnitMask_WIDTH                                 8
#define D18F5x40_UnitMask_MASK                                  0xff00
#define D18F5x40_Reserved_18_16_OFFSET                          16
#define D18F5x40_Reserved_18_16_WIDTH                           3
#define D18F5x40_Reserved_18_16_MASK                            0x70000
#define D18F5x40_Reserved_19_19_OFFSET                          19
#define D18F5x40_Reserved_19_19_WIDTH                           1
#define D18F5x40_Reserved_19_19_MASK                            0x80000
#define D18F5x40_Int_OFFSET                                     20
#define D18F5x40_Int_WIDTH                                      1
#define D18F5x40_Int_MASK                                       0x100000
#define D18F5x40_Reserved_21_21_OFFSET                          21
#define D18F5x40_Reserved_21_21_WIDTH                           1
#define D18F5x40_Reserved_21_21_MASK                            0x200000
#define D18F5x40_En_OFFSET                                      22
#define D18F5x40_En_WIDTH                                       1
#define D18F5x40_En_MASK                                        0x400000
#define D18F5x40_Reserved_31_23_OFFSET                          23
#define D18F5x40_Reserved_31_23_WIDTH                           9
#define D18F5x40_Reserved_31_23_MASK                            0xff800000

/// D18F5x40
typedef union {
  struct {                                                              ///<
    UINT32                                         EventSelect_7_0_:8 ; ///<
    UINT32                                                 UnitMask:8 ; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                           Reserved_19_19:1 ; ///<
    UINT32                                                      Int:1 ; ///<
    UINT32                                           Reserved_21_21:1 ; ///<
    UINT32                                                       En:1 ; ///<
    UINT32                                           Reserved_31_23:9 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x40_STRUCT;

// **** D18F5x44 Register Definition ****
// Address
#define D18F5x44_ADDRESS                                        0x44

// Type
#define D18F5x44_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x44_EventSelect_11_8__OFFSET                       0
#define D18F5x44_EventSelect_11_8__WIDTH                        4
#define D18F5x44_EventSelect_11_8__MASK                         0xf
#define D18F5x44_Reserved_63_36_OFFSET                          4
#define D18F5x44_Reserved_63_36_WIDTH                           28
#define D18F5x44_Reserved_63_36_MASK                            0xfffffff0

/// D18F5x44
typedef union {
  struct {                                                              ///<
    UINT32                                        EventSelect_11_8_:4 ; ///<
    UINT32                                           Reserved_63_36:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x44_STRUCT;

// **** D18F5x48 Register Definition ****
// Address
#define D18F5x48_ADDRESS                                        0x48

// Type
#define D18F5x48_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x48_CTR_31_0__OFFSET                               0
#define D18F5x48_CTR_31_0__WIDTH                                32
#define D18F5x48_CTR_31_0__MASK                                 0xffffffff

/// D18F5x48
typedef union {
  struct {                                                              ///<
    UINT32                                                CTR_31_0_:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x48_STRUCT;

// **** D18F5x4C Register Definition ****
// Address
#define D18F5x4C_ADDRESS                                        0x4c

// Type
#define D18F5x4C_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x4C_CTR_47_32__OFFSET                              0
#define D18F5x4C_CTR_47_32__WIDTH                               16
#define D18F5x4C_CTR_47_32__MASK                                0xffff
#define D18F5x4C_RAZ_63_48_OFFSET                               16
#define D18F5x4C_RAZ_63_48_WIDTH                                16
#define D18F5x4C_RAZ_63_48_MASK                                 0xffff0000

/// D18F5x4C
typedef union {
  struct {                                                              ///<
    UINT32                                               CTR_47_32_:16; ///<
    UINT32                                                RAZ_63_48:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x4C_STRUCT;

// **** D18F5x50 Register Definition ****
// Address
#define D18F5x50_ADDRESS                                        0x50

// Type
#define D18F5x50_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x50_EventSelect_7_0__OFFSET                        0
#define D18F5x50_EventSelect_7_0__WIDTH                         8
#define D18F5x50_EventSelect_7_0__MASK                          0xff
#define D18F5x50_UnitMask_OFFSET                                8
#define D18F5x50_UnitMask_WIDTH                                 8
#define D18F5x50_UnitMask_MASK                                  0xff00
#define D18F5x50_Reserved_18_16_OFFSET                          16
#define D18F5x50_Reserved_18_16_WIDTH                           3
#define D18F5x50_Reserved_18_16_MASK                            0x70000
#define D18F5x50_Reserved_19_19_OFFSET                          19
#define D18F5x50_Reserved_19_19_WIDTH                           1
#define D18F5x50_Reserved_19_19_MASK                            0x80000
#define D18F5x50_Int_OFFSET                                     20
#define D18F5x50_Int_WIDTH                                      1
#define D18F5x50_Int_MASK                                       0x100000
#define D18F5x50_Reserved_21_21_OFFSET                          21
#define D18F5x50_Reserved_21_21_WIDTH                           1
#define D18F5x50_Reserved_21_21_MASK                            0x200000
#define D18F5x50_En_OFFSET                                      22
#define D18F5x50_En_WIDTH                                       1
#define D18F5x50_En_MASK                                        0x400000
#define D18F5x50_Reserved_31_23_OFFSET                          23
#define D18F5x50_Reserved_31_23_WIDTH                           9
#define D18F5x50_Reserved_31_23_MASK                            0xff800000

/// D18F5x50
typedef union {
  struct {                                                              ///<
    UINT32                                         EventSelect_7_0_:8 ; ///<
    UINT32                                                 UnitMask:8 ; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                           Reserved_19_19:1 ; ///<
    UINT32                                                      Int:1 ; ///<
    UINT32                                           Reserved_21_21:1 ; ///<
    UINT32                                                       En:1 ; ///<
    UINT32                                           Reserved_31_23:9 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x50_STRUCT;

// **** D18F5x54 Register Definition ****
// Address
#define D18F5x54_ADDRESS                                        0x54

// Type
#define D18F5x54_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x54_EventSelect_11_8__OFFSET                       0
#define D18F5x54_EventSelect_11_8__WIDTH                        4
#define D18F5x54_EventSelect_11_8__MASK                         0xf
#define D18F5x54_Reserved_63_36_OFFSET                          4
#define D18F5x54_Reserved_63_36_WIDTH                           28
#define D18F5x54_Reserved_63_36_MASK                            0xfffffff0

/// D18F5x54
typedef union {
  struct {                                                              ///<
    UINT32                                        EventSelect_11_8_:4 ; ///<
    UINT32                                           Reserved_63_36:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x54_STRUCT;

// **** D18F5x58 Register Definition ****
// Address
#define D18F5x58_ADDRESS                                        0x58

// Type
#define D18F5x58_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x58_CTR_31_0__OFFSET                               0
#define D18F5x58_CTR_31_0__WIDTH                                32
#define D18F5x58_CTR_31_0__MASK                                 0xffffffff

/// D18F5x58
typedef union {
  struct {                                                              ///<
    UINT32                                                CTR_31_0_:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x58_STRUCT;

// **** D18F5x5C Register Definition ****
// Address
#define D18F5x5C_ADDRESS                                        0x5c

// Type
#define D18F5x5C_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x5C_CTR_47_32__OFFSET                              0
#define D18F5x5C_CTR_47_32__WIDTH                               16
#define D18F5x5C_CTR_47_32__MASK                                0xffff
#define D18F5x5C_RAZ_63_48_OFFSET                               16
#define D18F5x5C_RAZ_63_48_WIDTH                                16
#define D18F5x5C_RAZ_63_48_MASK                                 0xffff0000

/// D18F5x5C
typedef union {
  struct {                                                              ///<
    UINT32                                               CTR_47_32_:16; ///<
    UINT32                                                RAZ_63_48:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x5C_STRUCT;

// **** D18F5x60 Register Definition ****
// Address
#define D18F5x60_ADDRESS                                        0x60

// Type
#define D18F5x60_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x60_EventSelect_7_0__OFFSET                        0
#define D18F5x60_EventSelect_7_0__WIDTH                         8
#define D18F5x60_EventSelect_7_0__MASK                          0xff
#define D18F5x60_UnitMask_OFFSET                                8
#define D18F5x60_UnitMask_WIDTH                                 8
#define D18F5x60_UnitMask_MASK                                  0xff00
#define D18F5x60_Reserved_18_16_OFFSET                          16
#define D18F5x60_Reserved_18_16_WIDTH                           3
#define D18F5x60_Reserved_18_16_MASK                            0x70000
#define D18F5x60_Reserved_19_19_OFFSET                          19
#define D18F5x60_Reserved_19_19_WIDTH                           1
#define D18F5x60_Reserved_19_19_MASK                            0x80000
#define D18F5x60_Int_OFFSET                                     20
#define D18F5x60_Int_WIDTH                                      1
#define D18F5x60_Int_MASK                                       0x100000
#define D18F5x60_Reserved_21_21_OFFSET                          21
#define D18F5x60_Reserved_21_21_WIDTH                           1
#define D18F5x60_Reserved_21_21_MASK                            0x200000
#define D18F5x60_En_OFFSET                                      22
#define D18F5x60_En_WIDTH                                       1
#define D18F5x60_En_MASK                                        0x400000
#define D18F5x60_Reserved_31_23_OFFSET                          23
#define D18F5x60_Reserved_31_23_WIDTH                           9
#define D18F5x60_Reserved_31_23_MASK                            0xff800000

/// D18F5x60
typedef union {
  struct {                                                              ///<
    UINT32                                         EventSelect_7_0_:8 ; ///<
    UINT32                                                 UnitMask:8 ; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                           Reserved_19_19:1 ; ///<
    UINT32                                                      Int:1 ; ///<
    UINT32                                           Reserved_21_21:1 ; ///<
    UINT32                                                       En:1 ; ///<
    UINT32                                           Reserved_31_23:9 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x60_STRUCT;

// **** D18F5x64 Register Definition ****
// Address
#define D18F5x64_ADDRESS                                        0x64

// Type
#define D18F5x64_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x64_EventSelect_11_8__OFFSET                       0
#define D18F5x64_EventSelect_11_8__WIDTH                        4
#define D18F5x64_EventSelect_11_8__MASK                         0xf
#define D18F5x64_Reserved_63_36_OFFSET                          4
#define D18F5x64_Reserved_63_36_WIDTH                           28
#define D18F5x64_Reserved_63_36_MASK                            0xfffffff0

/// D18F5x64
typedef union {
  struct {                                                              ///<
    UINT32                                        EventSelect_11_8_:4 ; ///<
    UINT32                                           Reserved_63_36:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x64_STRUCT;

// **** D18F5x68 Register Definition ****
// Address
#define D18F5x68_ADDRESS                                        0x68

// Type
#define D18F5x68_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x68_CTR_31_0__OFFSET                               0
#define D18F5x68_CTR_31_0__WIDTH                                32
#define D18F5x68_CTR_31_0__MASK                                 0xffffffff

/// D18F5x68
typedef union {
  struct {                                                              ///<
    UINT32                                                CTR_31_0_:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x68_STRUCT;

// **** D18F5x6C Register Definition ****
// Address
#define D18F5x6C_ADDRESS                                        0x6c

// Type
#define D18F5x6C_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x6C_CTR_47_32__OFFSET                              0
#define D18F5x6C_CTR_47_32__WIDTH                               16
#define D18F5x6C_CTR_47_32__MASK                                0xffff
#define D18F5x6C_RAZ_63_48_OFFSET                               16
#define D18F5x6C_RAZ_63_48_WIDTH                                16
#define D18F5x6C_RAZ_63_48_MASK                                 0xffff0000

/// D18F5x6C
typedef union {
  struct {                                                              ///<
    UINT32                                               CTR_47_32_:16; ///<
    UINT32                                                RAZ_63_48:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x6C_STRUCT;

// **** D18F5x70 Register Definition ****
// Address
#define D18F5x70_ADDRESS                                        0x70

// Type
#define D18F5x70_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x70_EventSelect_7_0__OFFSET                        0
#define D18F5x70_EventSelect_7_0__WIDTH                         8
#define D18F5x70_EventSelect_7_0__MASK                          0xff
#define D18F5x70_UnitMask_OFFSET                                8
#define D18F5x70_UnitMask_WIDTH                                 8
#define D18F5x70_UnitMask_MASK                                  0xff00
#define D18F5x70_Reserved_18_16_OFFSET                          16
#define D18F5x70_Reserved_18_16_WIDTH                           3
#define D18F5x70_Reserved_18_16_MASK                            0x70000
#define D18F5x70_Reserved_19_19_OFFSET                          19
#define D18F5x70_Reserved_19_19_WIDTH                           1
#define D18F5x70_Reserved_19_19_MASK                            0x80000
#define D18F5x70_Int_OFFSET                                     20
#define D18F5x70_Int_WIDTH                                      1
#define D18F5x70_Int_MASK                                       0x100000
#define D18F5x70_Reserved_21_21_OFFSET                          21
#define D18F5x70_Reserved_21_21_WIDTH                           1
#define D18F5x70_Reserved_21_21_MASK                            0x200000
#define D18F5x70_En_OFFSET                                      22
#define D18F5x70_En_WIDTH                                       1
#define D18F5x70_En_MASK                                        0x400000
#define D18F5x70_Reserved_31_23_OFFSET                          23
#define D18F5x70_Reserved_31_23_WIDTH                           9
#define D18F5x70_Reserved_31_23_MASK                            0xff800000

/// D18F5x70
typedef union {
  struct {                                                              ///<
    UINT32                                         EventSelect_7_0_:8 ; ///<
    UINT32                                                 UnitMask:8 ; ///<
    UINT32                                           Reserved_18_16:3 ; ///<
    UINT32                                           Reserved_19_19:1 ; ///<
    UINT32                                                      Int:1 ; ///<
    UINT32                                           Reserved_21_21:1 ; ///<
    UINT32                                                       En:1 ; ///<
    UINT32                                           Reserved_31_23:9 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x70_STRUCT;

// **** D18F5x74 Register Definition ****
// Address
#define D18F5x74_ADDRESS                                        0x74

// Type
#define D18F5x74_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x74_EventSelect_11_8__OFFSET                       0
#define D18F5x74_EventSelect_11_8__WIDTH                        4
#define D18F5x74_EventSelect_11_8__MASK                         0xf
#define D18F5x74_Reserved_63_36_OFFSET                          4
#define D18F5x74_Reserved_63_36_WIDTH                           28
#define D18F5x74_Reserved_63_36_MASK                            0xfffffff0

/// D18F5x74
typedef union {
  struct {                                                              ///<
    UINT32                                        EventSelect_11_8_:4 ; ///<
    UINT32                                           Reserved_63_36:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x74_STRUCT;

// **** D18F5x78 Register Definition ****
// Address
#define D18F5x78_ADDRESS                                        0x78

// Type
#define D18F5x78_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x78_CTR_31_0__OFFSET                               0
#define D18F5x78_CTR_31_0__WIDTH                                32
#define D18F5x78_CTR_31_0__MASK                                 0xffffffff

/// D18F5x78
typedef union {
  struct {                                                              ///<
    UINT32                                                CTR_31_0_:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x78_STRUCT;

// **** D18F5x7C Register Definition ****
// Address
#define D18F5x7C_ADDRESS                                        0x7c

// Type
#define D18F5x7C_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x7C_CTR_47_32__OFFSET                              0
#define D18F5x7C_CTR_47_32__WIDTH                               16
#define D18F5x7C_CTR_47_32__MASK                                0xffff
#define D18F5x7C_RAZ_63_48_OFFSET                               16
#define D18F5x7C_RAZ_63_48_WIDTH                                16
#define D18F5x7C_RAZ_63_48_MASK                                 0xffff0000

/// D18F5x7C
typedef union {
  struct {                                                              ///<
    UINT32                                               CTR_47_32_:16; ///<
    UINT32                                                RAZ_63_48:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x7C_STRUCT;

// **** D18F5x80 Register Definition ****
// Address
#define D18F5x80_ADDRESS                                        0x80

// Type
#define D18F5x80_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x80_Enabled_OFFSET                                 0
#define D18F5x80_Enabled_WIDTH                                  4
#define D18F5x80_Enabled_MASK                                   0xf
#define D18F5x80_Reserved_15_4_OFFSET                           4
#define D18F5x80_Reserved_15_4_WIDTH                            12
#define D18F5x80_Reserved_15_4_MASK                             0xfff0
#define D18F5x80_DualCore_OFFSET                                16
#define D18F5x80_DualCore_WIDTH                                 4
#define D18F5x80_DualCore_MASK                                  0xf0000
#define D18F5x80_Reserved_31_20_OFFSET                          20
#define D18F5x80_Reserved_31_20_WIDTH                           12
#define D18F5x80_Reserved_31_20_MASK                            0xfff00000

/// D18F5x80
typedef union {
  struct {                                                              ///<
    UINT32                                                  Enabled:4 ; ///<
    UINT32                                            Reserved_15_4:12; ///<
    UINT32                                                 DualCore:4 ; ///<
    UINT32                                           Reserved_31_20:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x80_STRUCT;

// **** D18F5x84 Register Definition ****
// Address
#define D18F5x84_ADDRESS                                        0x84

// Type
#define D18F5x84_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x84_CmpCap_OFFSET                                  0
#define D18F5x84_CmpCap_WIDTH                                   8
#define D18F5x84_CmpCap_MASK                                    0xff
#define D18F5x84_Reserved_11_8_OFFSET                           8
#define D18F5x84_Reserved_11_8_WIDTH                            4
#define D18F5x84_Reserved_11_8_MASK                             0xf00
#define D18F5x84_DctEn_OFFSET                                   12
#define D18F5x84_DctEn_WIDTH                                    2
#define D18F5x84_DctEn_MASK                                     0x3000
#define D18F5x84_Reserved_15_14_OFFSET                          14
#define D18F5x84_Reserved_15_14_WIDTH                           2
#define D18F5x84_Reserved_15_14_MASK                            0xc000
#define D18F5x84_DdrMaxRate_OFFSET                              16
#define D18F5x84_DdrMaxRate_WIDTH                               5
#define D18F5x84_DdrMaxRate_MASK                                0x1f0000
#define D18F5x84_Reserved_23_21_OFFSET                          21
#define D18F5x84_Reserved_23_21_WIDTH                           3
#define D18F5x84_Reserved_23_21_MASK                            0xe00000
#define D18F5x84_DdrMaxRateEnf_OFFSET                           24
#define D18F5x84_DdrMaxRateEnf_WIDTH                            5
#define D18F5x84_DdrMaxRateEnf_MASK                             0x1f000000
#define D18F5x84_Reserved_31_29_OFFSET                          29
#define D18F5x84_Reserved_31_29_WIDTH                           3
#define D18F5x84_Reserved_31_29_MASK                            0xe0000000

/// D18F5x84
typedef union {
  struct {                                                              ///<
    UINT32                                                   CmpCap:8 ; ///<
    UINT32                                            Reserved_11_8:4 ; ///<
    UINT32                                                    DctEn:2 ; ///<
    UINT32                                           Reserved_15_14:2 ; ///<
    UINT32                                               DdrMaxRate:5 ; ///<
    UINT32                                           Reserved_23_21:3 ; ///<
    UINT32                                            DdrMaxRateEnf:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x84_STRUCT;

// **** D18F5x88 Register Definition ****
// Address
#define D18F5x88_ADDRESS                                        0x88

// Type
#define D18F5x88_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5x88_Reserved_1_0_OFFSET                            0
#define D18F5x88_Reserved_1_0_WIDTH                             2
#define D18F5x88_Reserved_1_0_MASK                              0x3
#define D18F5x88_IntStpClkHaltExitEn_OFFSET                     2
#define D18F5x88_IntStpClkHaltExitEn_WIDTH                      1
#define D18F5x88_IntStpClkHaltExitEn_MASK                       0x4

/// D18F5x88
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_1_0:2 ; ///<
    UINT32                                      IntStpClkHaltExitEn:1 ; ///<
    UINT32                                            :29; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x88_STRUCT;

// **** D18F5xE0 Register Definition ****
// Address
#define D18F5xE0_ADDRESS                                        0xe0

// Type
#define D18F5xE0_TYPE                                           TYPE_D18F5
// Field Data
#define D18F5xE0_RunAvgRange_OFFSET                             0
#define D18F5xE0_RunAvgRange_WIDTH                              4
#define D18F5xE0_RunAvgRange_MASK                               0xf
#define D18F5xE0_Reserved_31_4_OFFSET                           4
#define D18F5xE0_Reserved_31_4_WIDTH                            28
#define D18F5xE0_Reserved_31_4_MASK                             0xfffffff0

/// D18F5xE0
typedef union {
  struct {                                                              ///<
    UINT32                                              RunAvgRange:4 ; ///<
    UINT32                                            Reserved_31_4:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5xE0_STRUCT;


// **** D18F5x128 Register Definition ****
// Address
#define D18F5x128_ADDRESS                                       0x128

// Type
#define D18F5x128_TYPE                                          TYPE_D18F5
// Field Data
#define D18F5x128_PC6Vid_6_0__OFFSET                            0
#define D18F5x128_PC6Vid_6_0__WIDTH                             7
#define D18F5x128_PC6Vid_6_0__MASK                              0x7f
#define D18F5x128_PllRegTime_OFFSET                             7
#define D18F5x128_PllRegTime_WIDTH                              2
#define D18F5x128_PllRegTime_MASK                               0x180
#define D18F5x128_FastSlamTimeDown_OFFSET                       9
#define D18F5x128_FastSlamTimeDown_WIDTH                        1
#define D18F5x128_FastSlamTimeDown_MASK                         0x200
#define D18F5x128_PllVddOutUpTime_OFFSET                        10
#define D18F5x128_PllVddOutUpTime_WIDTH                         2
#define D18F5x128_PllVddOutUpTime_MASK                          0xc00
#define D18F5x128_PwrGateTmr_OFFSET                             12
#define D18F5x128_PwrGateTmr_WIDTH                              2
#define D18F5x128_PwrGateTmr_MASK                               0x3000
#define D18F5x128_PC6PwrDwnRegEn_OFFSET                         14
#define D18F5x128_PC6PwrDwnRegEn_WIDTH                          1
#define D18F5x128_PC6PwrDwnRegEn_MASK                           0x4000
#define D18F5x128_CC6PwrDwnRegEn_OFFSET                         15
#define D18F5x128_CC6PwrDwnRegEn_WIDTH                          1
#define D18F5x128_CC6PwrDwnRegEn_MASK                           0x8000
#define D18F5x128_Reserved_20_16_OFFSET                         16
#define D18F5x128_Reserved_20_16_WIDTH                          5
#define D18F5x128_Reserved_20_16_MASK                           0x1f0000
#define D18F5x128_PC6Vid_7__OFFSET                              21
#define D18F5x128_PC6Vid_7__WIDTH                               1
#define D18F5x128_PC6Vid_7__MASK                                0x200000
#define D18F5x128_NbPllPwrDwnRegEn_OFFSET                       22
#define D18F5x128_NbPllPwrDwnRegEn_WIDTH                        1
#define D18F5x128_NbPllPwrDwnRegEn_MASK                         0x400000
#define D18F5x128_Reserved_31_23_OFFSET                         23
#define D18F5x128_Reserved_31_23_WIDTH                          9
#define D18F5x128_Reserved_31_23_MASK                           0xff800000

/// D18F5x128
typedef union {
  struct {                                                              ///<
    UINT32                                              PC6Vid_6_0_:7 ; ///<
    UINT32                                               PllRegTime:2 ; ///<
    UINT32                                         FastSlamTimeDown:1 ; ///<
    UINT32                                          PllVddOutUpTime:2 ; ///<
    UINT32                                               PwrGateTmr:2 ; ///<
    UINT32                                           PC6PwrDwnRegEn:1 ; ///<
    UINT32                                           CC6PwrDwnRegEn:1 ; ///<
    UINT32                                           Reserved_20_16:5 ; ///<
    UINT32                                                PC6Vid_7_:1 ; ///<
    UINT32                                         NbPllPwrDwnRegEn:1 ; ///<
    UINT32                                           Reserved_31_23:9 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x128_STRUCT;

// **** D18F5x12C Register Definition ****
// Address
#define D18F5x12C_ADDRESS                                       0x12c

// Type
#define D18F5x12C_TYPE                                          TYPE_D18F5
// Field Data
#define D18F5x12C_CoreOffsetTrim_OFFSET                         0
#define D18F5x12C_CoreOffsetTrim_WIDTH                          2
#define D18F5x12C_CoreOffsetTrim_MASK                           0x3
#define D18F5x12C_CoreLoadLineTrim_OFFSET                       2
#define D18F5x12C_CoreLoadLineTrim_WIDTH                        3
#define D18F5x12C_CoreLoadLineTrim_MASK                         0x1c
#define D18F5x12C_CorePsi1En_OFFSET                             5
#define D18F5x12C_CorePsi1En_WIDTH                              1
#define D18F5x12C_CorePsi1En_MASK                               0x20
#define D18F5x12C_Reserved_29_7_OFFSET                          7
#define D18F5x12C_Reserved_29_7_WIDTH                           23
#define D18F5x12C_Reserved_29_7_MASK                            0x3fffff80
#define D18F5x12C_WaitVidCompDis_OFFSET                         30
#define D18F5x12C_WaitVidCompDis_WIDTH                          1
#define D18F5x12C_WaitVidCompDis_MASK                           0x40000000
#define D18F5x12C_Svi2CmdBusy_OFFSET                            31
#define D18F5x12C_Svi2CmdBusy_WIDTH                             1
#define D18F5x12C_Svi2CmdBusy_MASK                              0x80000000

/// D18F5x12C
typedef union {
  struct {                                                              ///<
    UINT32                                           CoreOffsetTrim:2 ; ///<
    UINT32                                         CoreLoadLineTrim:3 ; ///<
    UINT32                                               CorePsi1En:1 ; ///<
    UINT32                                                  :1 ; ///<
    UINT32                                            Reserved_29_7:23; ///<
    UINT32                                           WaitVidCompDis:1 ; ///<
    UINT32                                              Svi2CmdBusy:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x12C_STRUCT;


// **** D18F5x160 Register Definition ****
// Address
#define D18F5x160_ADDRESS                                       0x160

// Type
#define D18F5x160_TYPE                                          TYPE_D18F5
// Field Data
#define D18F5x160_NbPstateEn_OFFSET                             0
#define D18F5x160_NbPstateEn_WIDTH                              1
#define D18F5x160_NbPstateEn_MASK                               0x1
#define D18F5x160_NbFid_OFFSET                                  1
#define D18F5x160_NbFid_WIDTH                                   6
#define D18F5x160_NbFid_MASK                                    0x7e
#define D18F5x160_NbDid_OFFSET                                  7
#define D18F5x160_NbDid_WIDTH                                   1
#define D18F5x160_NbDid_MASK                                    0x80
#define D18F5x160_Reserved_9_8_OFFSET                           8
#define D18F5x160_Reserved_9_8_WIDTH                            2
#define D18F5x160_Reserved_9_8_MASK                             0x300
#define D18F5x160_NbVid_6_0__OFFSET                             10
#define D18F5x160_NbVid_6_0__WIDTH                              7
#define D18F5x160_NbVid_6_0__MASK                               0x1fc00
#define D18F5x160_Reserved_17_17_OFFSET                         17
#define D18F5x160_Reserved_17_17_WIDTH                          1
#define D18F5x160_Reserved_17_17_MASK                           0x20000
#define D18F5x160_MemPstate_OFFSET                              18
#define D18F5x160_MemPstate_WIDTH                               1
#define D18F5x160_MemPstate_MASK                                0x40000
#define D18F5x160_Reserved_20_19_OFFSET                         19
#define D18F5x160_Reserved_20_19_WIDTH                          2
#define D18F5x160_Reserved_20_19_MASK                           0x180000
#define D18F5x160_NbVid_7__OFFSET                               21
#define D18F5x160_NbVid_7__WIDTH                                1
#define D18F5x160_NbVid_7__MASK                                 0x200000
#define D18F5x160_NbIddDiv_OFFSET                               22
#define D18F5x160_NbIddDiv_WIDTH                                2
#define D18F5x160_NbIddDiv_MASK                                 0xc00000
#define D18F5x160_NbIddValue_OFFSET                             24
#define D18F5x160_NbIddValue_WIDTH                              8
#define D18F5x160_NbIddValue_MASK                               0xff000000

/// D18F5x160
typedef union {
  struct {                                                              ///<
    UINT32                                               NbPstateEn:1 ; ///<
    UINT32                                                    NbFid:6 ; ///<
    UINT32                                                    NbDid:1 ; ///<
    UINT32                                             Reserved_9_8:2 ; ///<
    UINT32                                               NbVid_6_0_:7 ; ///<
    UINT32                                           Reserved_17_17:1 ; ///<
    UINT32                                                MemPstate:1 ; ///<
    UINT32                                           Reserved_20_19:2 ; ///<
    UINT32                                                 NbVid_7_:1 ; ///<
    UINT32                                                 NbIddDiv:2 ; ///<
    UINT32                                               NbIddValue:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x160_STRUCT;

// **** D18F5x164 Register Definition ****
// Address
#define D18F5x164_ADDRESS                                       0x164

// Type
#define D18F5x164_TYPE                                          TYPE_D18F5
// Field Data
#define D18F5x164_NbPstateEn_OFFSET                             0
#define D18F5x164_NbPstateEn_WIDTH                              1
#define D18F5x164_NbPstateEn_MASK                               0x1
#define D18F5x164_NbFid_OFFSET                                  1
#define D18F5x164_NbFid_WIDTH                                   6
#define D18F5x164_NbFid_MASK                                    0x7e
#define D18F5x164_NbDid_OFFSET                                  7
#define D18F5x164_NbDid_WIDTH                                   1
#define D18F5x164_NbDid_MASK                                    0x80
#define D18F5x164_Reserved_9_8_OFFSET                           8
#define D18F5x164_Reserved_9_8_WIDTH                            2
#define D18F5x164_Reserved_9_8_MASK                             0x300
#define D18F5x164_NbVid_6_0__OFFSET                             10
#define D18F5x164_NbVid_6_0__WIDTH                              7
#define D18F5x164_NbVid_6_0__MASK                               0x1fc00
#define D18F5x164_Reserved_17_17_OFFSET                         17
#define D18F5x164_Reserved_17_17_WIDTH                          1
#define D18F5x164_Reserved_17_17_MASK                           0x20000
#define D18F5x164_MemPstate_OFFSET                              18
#define D18F5x164_MemPstate_WIDTH                               1
#define D18F5x164_MemPstate_MASK                                0x40000
#define D18F5x164_Reserved_20_19_OFFSET                         19
#define D18F5x164_Reserved_20_19_WIDTH                          2
#define D18F5x164_Reserved_20_19_MASK                           0x180000
#define D18F5x164_NbVid_7__OFFSET                               21
#define D18F5x164_NbVid_7__WIDTH                                1
#define D18F5x164_NbVid_7__MASK                                 0x200000
#define D18F5x164_NbIddDiv_OFFSET                               22
#define D18F5x164_NbIddDiv_WIDTH                                2
#define D18F5x164_NbIddDiv_MASK                                 0xc00000
#define D18F5x164_NbIddValue_OFFSET                             24
#define D18F5x164_NbIddValue_WIDTH                              8
#define D18F5x164_NbIddValue_MASK                               0xff000000

/// D18F5x164
typedef union {
  struct {                                                              ///<
    UINT32                                               NbPstateEn:1 ; ///<
    UINT32                                                    NbFid:6 ; ///<
    UINT32                                                    NbDid:1 ; ///<
    UINT32                                             Reserved_9_8:2 ; ///<
    UINT32                                               NbVid_6_0_:7 ; ///<
    UINT32                                           Reserved_17_17:1 ; ///<
    UINT32                                                MemPstate:1 ; ///<
    UINT32                                           Reserved_20_19:2 ; ///<
    UINT32                                                 NbVid_7_:1 ; ///<
    UINT32                                                 NbIddDiv:2 ; ///<
    UINT32                                               NbIddValue:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x164_STRUCT;

// **** D18F5x168 Register Definition ****
// Address
#define D18F5x168_ADDRESS                                       0x168

// Type
#define D18F5x168_TYPE                                          TYPE_D18F5
// Field Data
#define D18F5x168_NbPstateEn_OFFSET                             0
#define D18F5x168_NbPstateEn_WIDTH                              1
#define D18F5x168_NbPstateEn_MASK                               0x1
#define D18F5x168_NbFid_OFFSET                                  1
#define D18F5x168_NbFid_WIDTH                                   6
#define D18F5x168_NbFid_MASK                                    0x7e
#define D18F5x168_NbDid_OFFSET                                  7
#define D18F5x168_NbDid_WIDTH                                   1
#define D18F5x168_NbDid_MASK                                    0x80
#define D18F5x168_Reserved_9_8_OFFSET                           8
#define D18F5x168_Reserved_9_8_WIDTH                            2
#define D18F5x168_Reserved_9_8_MASK                             0x300
#define D18F5x168_NbVid_6_0__OFFSET                             10
#define D18F5x168_NbVid_6_0__WIDTH                              7
#define D18F5x168_NbVid_6_0__MASK                               0x1fc00
#define D18F5x168_Reserved_17_17_OFFSET                         17
#define D18F5x168_Reserved_17_17_WIDTH                          1
#define D18F5x168_Reserved_17_17_MASK                           0x20000
#define D18F5x168_MemPstate_OFFSET                              18
#define D18F5x168_MemPstate_WIDTH                               1
#define D18F5x168_MemPstate_MASK                                0x40000
#define D18F5x168_Reserved_20_19_OFFSET                         19
#define D18F5x168_Reserved_20_19_WIDTH                          2
#define D18F5x168_Reserved_20_19_MASK                           0x180000
#define D18F5x168_NbVid_7__OFFSET                               21
#define D18F5x168_NbVid_7__WIDTH                                1
#define D18F5x168_NbVid_7__MASK                                 0x200000
#define D18F5x168_NbIddDiv_OFFSET                               22
#define D18F5x168_NbIddDiv_WIDTH                                2
#define D18F5x168_NbIddDiv_MASK                                 0xc00000
#define D18F5x168_NbIddValue_OFFSET                             24
#define D18F5x168_NbIddValue_WIDTH                              8
#define D18F5x168_NbIddValue_MASK                               0xff000000

/// D18F5x168
typedef union {
  struct {                                                              ///<
    UINT32                                               NbPstateEn:1 ; ///<
    UINT32                                                    NbFid:6 ; ///<
    UINT32                                                    NbDid:1 ; ///<
    UINT32                                             Reserved_9_8:2 ; ///<
    UINT32                                               NbVid_6_0_:7 ; ///<
    UINT32                                           Reserved_17_17:1 ; ///<
    UINT32                                                MemPstate:1 ; ///<
    UINT32                                           Reserved_20_19:2 ; ///<
    UINT32                                                 NbVid_7_:1 ; ///<
    UINT32                                                 NbIddDiv:2 ; ///<
    UINT32                                               NbIddValue:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x168_STRUCT;

// **** D18F5x16C Register Definition ****
// Address
#define D18F5x16C_ADDRESS                                       0x16c

// Type
#define D18F5x16C_TYPE                                          TYPE_D18F5
// Field Data
#define D18F5x16C_NbPstateEn_OFFSET                             0
#define D18F5x16C_NbPstateEn_WIDTH                              1
#define D18F5x16C_NbPstateEn_MASK                               0x1
#define D18F5x16C_NbFid_OFFSET                                  1
#define D18F5x16C_NbFid_WIDTH                                   6
#define D18F5x16C_NbFid_MASK                                    0x7e
#define D18F5x16C_NbDid_OFFSET                                  7
#define D18F5x16C_NbDid_WIDTH                                   1
#define D18F5x16C_NbDid_MASK                                    0x80
#define D18F5x16C_Reserved_9_8_OFFSET                           8
#define D18F5x16C_Reserved_9_8_WIDTH                            2
#define D18F5x16C_Reserved_9_8_MASK                             0x300
#define D18F5x16C_NbVid_6_0__OFFSET                             10
#define D18F5x16C_NbVid_6_0__WIDTH                              7
#define D18F5x16C_NbVid_6_0__MASK                               0x1fc00
#define D18F5x16C_Reserved_17_17_OFFSET                         17
#define D18F5x16C_Reserved_17_17_WIDTH                          1
#define D18F5x16C_Reserved_17_17_MASK                           0x20000
#define D18F5x16C_MemPstate_OFFSET                              18
#define D18F5x16C_MemPstate_WIDTH                               1
#define D18F5x16C_MemPstate_MASK                                0x40000
#define D18F5x16C_Reserved_20_19_OFFSET                         19
#define D18F5x16C_Reserved_20_19_WIDTH                          2
#define D18F5x16C_Reserved_20_19_MASK                           0x180000
#define D18F5x16C_NbVid_7__OFFSET                               21
#define D18F5x16C_NbVid_7__WIDTH                                1
#define D18F5x16C_NbVid_7__MASK                                 0x200000
#define D18F5x16C_NbIddDiv_OFFSET                               22
#define D18F5x16C_NbIddDiv_WIDTH                                2
#define D18F5x16C_NbIddDiv_MASK                                 0xc00000
#define D18F5x16C_NbIddValue_OFFSET                             24
#define D18F5x16C_NbIddValue_WIDTH                              8
#define D18F5x16C_NbIddValue_MASK                               0xff000000

/// D18F5x16C
typedef union {
  struct {                                                              ///<
    UINT32                                               NbPstateEn:1 ; ///<
    UINT32                                                    NbFid:6 ; ///<
    UINT32                                                    NbDid:1 ; ///<
    UINT32                                             Reserved_9_8:2 ; ///<
    UINT32                                               NbVid_6_0_:7 ; ///<
    UINT32                                           Reserved_17_17:1 ; ///<
    UINT32                                                MemPstate:1 ; ///<
    UINT32                                           Reserved_20_19:2 ; ///<
    UINT32                                                 NbVid_7_:1 ; ///<
    UINT32                                                 NbIddDiv:2 ; ///<
    UINT32                                               NbIddValue:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x16C_STRUCT;

// **** D18F5x170 Register Definition ****
// Address
#define D18F5x170_ADDRESS                                       0x170

// Type
#define D18F5x170_TYPE                                          TYPE_D18F5
// Field Data
#define D18F5x170_NbPstateMaxVal_OFFSET                         0
#define D18F5x170_NbPstateMaxVal_WIDTH                          2
#define D18F5x170_NbPstateMaxVal_MASK                           0x3
#define D18F5x170_Reserved_2_2_OFFSET                           2
#define D18F5x170_Reserved_2_2_WIDTH                            1
#define D18F5x170_Reserved_2_2_MASK                             0x4
#define D18F5x170_NbPstateLo_OFFSET                             3
#define D18F5x170_NbPstateLo_WIDTH                              2
#define D18F5x170_NbPstateLo_MASK                               0x18
#define D18F5x170_Reserved_5_5_OFFSET                           5
#define D18F5x170_Reserved_5_5_WIDTH                            1
#define D18F5x170_Reserved_5_5_MASK                             0x20
#define D18F5x170_NbPstateHi_OFFSET                             6
#define D18F5x170_NbPstateHi_WIDTH                              2
#define D18F5x170_NbPstateHi_MASK                               0xc0
#define D18F5x170_Reserved_8_8_OFFSET                           8
#define D18F5x170_Reserved_8_8_WIDTH                            1
#define D18F5x170_Reserved_8_8_MASK                             0x100
#define D18F5x170_NbPstateThreshold_OFFSET                      9
#define D18F5x170_NbPstateThreshold_WIDTH                       3
#define D18F5x170_NbPstateThreshold_MASK                        0xe00
#define D18F5x170_Reserved_12_12_OFFSET                         12
#define D18F5x170_Reserved_12_12_WIDTH                          1
#define D18F5x170_Reserved_12_12_MASK                           0x1000
#define D18F5x170_NbPstateDisOnP0_OFFSET                        13
#define D18F5x170_NbPstateDisOnP0_WIDTH                         1
#define D18F5x170_NbPstateDisOnP0_MASK                          0x2000
#define D18F5x170_SwNbPstateLoDis_OFFSET                        14
#define D18F5x170_SwNbPstateLoDis_WIDTH                         1
#define D18F5x170_SwNbPstateLoDis_MASK                          0x4000
#define D18F5x170_Reserved_22_15_OFFSET                         15
#define D18F5x170_Reserved_22_15_WIDTH                          8
#define D18F5x170_Reserved_22_15_MASK                           0x7f8000
#define D18F5x170_NbPstateGnbSlowDis_OFFSET                     23
#define D18F5x170_NbPstateGnbSlowDis_WIDTH                      1
#define D18F5x170_NbPstateGnbSlowDis_MASK                       0x800000
#define D18F5x170_NbPstateLoRes_OFFSET                          24
#define D18F5x170_NbPstateLoRes_WIDTH                           3
#define D18F5x170_NbPstateLoRes_MASK                            0x7000000
#define D18F5x170_NbPstateHiRes_OFFSET                          27
#define D18F5x170_NbPstateHiRes_WIDTH                           3
#define D18F5x170_NbPstateHiRes_MASK                            0x38000000
#define D18F5x170_Reserved_30_30_OFFSET                         30
#define D18F5x170_Reserved_30_30_WIDTH                          1
#define D18F5x170_Reserved_30_30_MASK                           0x40000000
#define D18F5x170_MemPstateDis_OFFSET                           31
#define D18F5x170_MemPstateDis_WIDTH                            1
#define D18F5x170_MemPstateDis_MASK                             0x80000000

/// D18F5x170
typedef union {
  struct {                                                              ///<
    UINT32                                           NbPstateMaxVal:2 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                               NbPstateLo:2 ; ///<
    UINT32                                             Reserved_5_5:1 ; ///<
    UINT32                                               NbPstateHi:2 ; ///<
    UINT32                                             Reserved_8_8:1 ; ///<
    UINT32                                        NbPstateThreshold:3 ; ///<
    UINT32                                           Reserved_12_12:1 ; ///<
    UINT32                                          NbPstateDisOnP0:1 ; ///<
    UINT32                                          SwNbPstateLoDis:1 ; ///<
    UINT32                                           Reserved_22_15:8 ; ///<
    UINT32                                       NbPstateGnbSlowDis:1 ; ///<
    UINT32                                            NbPstateLoRes:3 ; ///<
    UINT32                                            NbPstateHiRes:3 ; ///<
    UINT32                                           Reserved_30_30:1 ; ///<
    UINT32                                             MemPstateDis:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x170_STRUCT;

// **** D18F5x174 Register Definition ****
// Address
#define D18F5x174_ADDRESS                                       0x174

// Type
#define D18F5x174_TYPE                                          TYPE_D18F5
// Field Data
#define D18F5x174_NbPstateDis_OFFSET                            0
#define D18F5x174_NbPstateDis_WIDTH                             1
#define D18F5x174_NbPstateDis_MASK                              0x1
#define D18F5x174_StartupNbPstate_OFFSET                        1
#define D18F5x174_StartupNbPstate_WIDTH                         2
#define D18F5x174_StartupNbPstate_MASK                          0x6
#define D18F5x174_CurNbFid_OFFSET                               3
#define D18F5x174_CurNbFid_WIDTH                                6
#define D18F5x174_CurNbFid_MASK                                 0x1f8
#define D18F5x174_CurNbDid_OFFSET                               9
#define D18F5x174_CurNbDid_WIDTH                                1
#define D18F5x174_CurNbDid_MASK                                 0x200
#define D18F5x174_Reserved_11_10_OFFSET                         10
#define D18F5x174_Reserved_11_10_WIDTH                          2
#define D18F5x174_Reserved_11_10_MASK                           0xc00
#define D18F5x174_CurNbVid_6_0__OFFSET                          12
#define D18F5x174_CurNbVid_6_0__WIDTH                           7
#define D18F5x174_CurNbVid_6_0__MASK                            0x7f000
#define D18F5x174_CurNbPstate_OFFSET                            19
#define D18F5x174_CurNbPstate_WIDTH                             2
#define D18F5x174_CurNbPstate_MASK                              0x180000
#define D18F5x174_Reserved_22_21_OFFSET                         21
#define D18F5x174_Reserved_22_21_WIDTH                          2
#define D18F5x174_Reserved_22_21_MASK                           0x600000
#define D18F5x174_CurNbVid_7__OFFSET                            23
#define D18F5x174_CurNbVid_7__WIDTH                             1
#define D18F5x174_CurNbVid_7__MASK                              0x800000
#define D18F5x174_CurMemPstate_OFFSET                           24
#define D18F5x174_CurMemPstate_WIDTH                            1
#define D18F5x174_CurMemPstate_MASK                             0x1000000
#define D18F5x174_Reserved_31_25_OFFSET                         25
#define D18F5x174_Reserved_31_25_WIDTH                          7
#define D18F5x174_Reserved_31_25_MASK                           0xfe000000

/// D18F5x174
typedef union {
  struct {                                                              ///<
    UINT32                                              NbPstateDis:1 ; ///<
    UINT32                                          StartupNbPstate:2 ; ///<
    UINT32                                                 CurNbFid:6 ; ///<
    UINT32                                                 CurNbDid:1 ; ///<
    UINT32                                           Reserved_11_10:2 ; ///<
    UINT32                                            CurNbVid_6_0_:7 ; ///<
    UINT32                                              CurNbPstate:2 ; ///<
    UINT32                                           Reserved_22_21:2 ; ///<
    UINT32                                              CurNbVid_7_:1 ; ///<
    UINT32                                             CurMemPstate:1 ; ///<
    UINT32                                           Reserved_31_25:7 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x174_STRUCT;

// **** D18F5x178 Register Definition ****
// Address
#define D18F5x178_ADDRESS                                       0x178

// Type
#define D18F5x178_TYPE                                          TYPE_D18F5
// Field Data
#define D18F5x178_Reserved_1_0_OFFSET                           0
#define D18F5x178_Reserved_1_0_WIDTH                            2
#define D18F5x178_Reserved_1_0_MASK                             0x3
#define D18F5x178_CstateFusionDis_OFFSET                        2
#define D18F5x178_CstateFusionDis_WIDTH                         1
#define D18F5x178_CstateFusionDis_MASK                          0x4
#define D18F5x178_CstateThreeWayHsEn_OFFSET                     3
#define D18F5x178_CstateThreeWayHsEn_WIDTH                      1
#define D18F5x178_CstateThreeWayHsEn_MASK                       0x8
#define D18F5x178_Reserved_9_4_OFFSET                           4
#define D18F5x178_Reserved_9_4_WIDTH                            6
#define D18F5x178_Reserved_9_4_MASK                             0x3f0
#define D18F5x178_InbWakeS3Dis_OFFSET                           10
#define D18F5x178_InbWakeS3Dis_WIDTH                            1
#define D18F5x178_InbWakeS3Dis_MASK                             0x400
#define D18F5x178_AllowSelfRefrS3Dis_OFFSET                     11
#define D18F5x178_AllowSelfRefrS3Dis_WIDTH                      1
#define D18F5x178_AllowSelfRefrS3Dis_MASK                       0x800
#define D18F5x178_CstateFusionHsDis_OFFSET                      18
#define D18F5x178_CstateFusionHsDis_WIDTH                       1
#define D18F5x178_CstateFusionHsDis_MASK                        0x40000
#define D18F5x178_SwGfxDis_OFFSET                               19
#define D18F5x178_SwGfxDis_WIDTH                                1
#define D18F5x178_SwGfxDis_MASK                                 0x80000
#define D18F5x178_Reserved_31_20_OFFSET                         20
#define D18F5x178_Reserved_31_20_WIDTH                          12
#define D18F5x178_Reserved_31_20_MASK                           0xfff00000

/// D18F5x178
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_1_0:2 ; ///<
    UINT32                                          CstateFusionDis:1 ; ///<
    UINT32                                       CstateThreeWayHsEn:1 ; ///<
    UINT32                                             Reserved_9_4:6 ; ///<
    UINT32                                             InbWakeS3Dis:1 ; ///<
    UINT32                                       AllowSelfRefrS3Dis:1 ; ///<
    UINT32                                           :6 ; ///<
    UINT32                                        CstateFusionHsDis:1 ; ///<
    UINT32                                                 SwGfxDis:1 ; ///<
    UINT32                                           Reserved_31_20:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x178_STRUCT;

// **** D18F5x17C Register Definition ****
// Address
#define D18F5x17C_ADDRESS                                       0x17c

// Type
#define D18F5x17C_TYPE                                          TYPE_D18F5
// Field Data
#define D18F5x17C_MaxVid_OFFSET                                 0
#define D18F5x17C_MaxVid_WIDTH                                  8
#define D18F5x17C_MaxVid_MASK                                   0xff
#define D18F5x17C_Reserved_9_8_OFFSET                           8
#define D18F5x17C_Reserved_9_8_WIDTH                            2
#define D18F5x17C_Reserved_9_8_MASK                             0x300
#define D18F5x17C_MinVid_OFFSET                                 10
#define D18F5x17C_MinVid_WIDTH                                  8
#define D18F5x17C_MinVid_MASK                                   0x3fc00
#define D18F5x17C_Reserved_22_18_OFFSET                         18
#define D18F5x17C_Reserved_22_18_WIDTH                          5
#define D18F5x17C_Reserved_22_18_MASK                           0x7c0000
#define D18F5x17C_NbPsi0Vid_7_0__OFFSET                         23
#define D18F5x17C_NbPsi0Vid_7_0__WIDTH                          8
#define D18F5x17C_NbPsi0Vid_7_0__MASK                           0x7f800000
#define D18F5x17C_NbPsi0VidEn_OFFSET                            31
#define D18F5x17C_NbPsi0VidEn_WIDTH                             1
#define D18F5x17C_NbPsi0VidEn_MASK                              0x80000000

/// D18F5x17C
typedef union {
  struct {                                                              ///<
    UINT32                                                   MaxVid:8 ; ///<
    UINT32                                             Reserved_9_8:2 ; ///<
    UINT32                                                   MinVid:8 ; ///<
    UINT32                                           Reserved_22_18:5 ; ///<
    UINT32                                           NbPsi0Vid_7_0_:8 ; ///<
    UINT32                                              NbPsi0VidEn:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x17C_STRUCT;

// **** D18F5x188 Register Definition ****
// Address
#define D18F5x188_ADDRESS                                       0x188

// Type
#define D18F5x188_TYPE                                          TYPE_D18F5
// Field Data
#define D18F5x188_NbOffsetTrim_OFFSET                           0
#define D18F5x188_NbOffsetTrim_WIDTH                            2
#define D18F5x188_NbOffsetTrim_MASK                             0x3
#define D18F5x188_NbLoadLineTrim_OFFSET                         2
#define D18F5x188_NbLoadLineTrim_WIDTH                          3
#define D18F5x188_NbLoadLineTrim_MASK                           0x1c
#define D18F5x188_NbPsi1_OFFSET                                 5
#define D18F5x188_NbPsi1_WIDTH                                  1
#define D18F5x188_NbPsi1_MASK                                   0x20
#define D18F5x188_Reserved_31_7_OFFSET                          7
#define D18F5x188_Reserved_31_7_WIDTH                           25
#define D18F5x188_Reserved_31_7_MASK                            0xffffff80

/// D18F5x188
typedef union {
  struct {                                                              ///<
    UINT32                                             NbOffsetTrim:2 ; ///<
    UINT32                                           NbLoadLineTrim:3 ; ///<
    UINT32                                                   NbPsi1:1 ; ///<
    UINT32                                                    NbTfn:1 ; ///<
    UINT32                                            Reserved_31_7:25; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x188_STRUCT;

// **** D18F5x194 Register Definition ****
// Address
#define D18F5x194_ADDRESS                                       0x194

// Type
#define D18F5x194_TYPE                                          TYPE_D18F5
// Field Data
#define D18F5x194_Index_OFFSET                                  0
#define D18F5x194_Index_WIDTH                                   4
#define D18F5x194_Index_MASK                                    0xf
#define D18F5x194_Reserved_31_4_OFFSET                          4
#define D18F5x194_Reserved_31_4_WIDTH                           28
#define D18F5x194_Reserved_31_4_MASK                            0xfffffff0

/// D18F5x194
typedef union {
  struct {                                                              ///<
    UINT32                                                    Index:4 ; ///<
    UINT32                                            Reserved_31_4:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x194_STRUCT;

// **** D18F5x198 Register Definition ****
// Address
#define D18F5x198_ADDRESS                                       0x198

// Type
#define D18F5x198_TYPE                                          TYPE_D18F5
// Field Data
#define D18F5x198_Data_OFFSET                                   0
#define D18F5x198_Data_WIDTH                                    32
#define D18F5x198_Data_MASK                                     0xffffffff

/// D18F5x198
typedef union {
  struct {                                                              ///<
    UINT32                                                     Data:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F5x198_STRUCT;

// **** DxF0x00 Register Definition ****
// Address
#define DxF0x00_ADDRESS                                         0x0

// Type
#define DxF0x00_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x00_VendorID_OFFSET                                 0
#define DxF0x00_VendorID_WIDTH                                  16
#define DxF0x00_VendorID_MASK                                   0xffff
#define DxF0x00_DeviceID_OFFSET                                 16
#define DxF0x00_DeviceID_WIDTH                                  16
#define DxF0x00_DeviceID_MASK                                   0xffff0000

/// DxF0x00
typedef union {
  struct {                                                              ///<
    UINT32                                                 VendorID:16; ///<
    UINT32                                                 DeviceID:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x00_STRUCT;

// **** DxF0x04 Register Definition ****
// Address
#define DxF0x04_ADDRESS                                         0x4

// Type
#define DxF0x04_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x04_IoAccessEn_OFFSET                               0
#define DxF0x04_IoAccessEn_WIDTH                                1
#define DxF0x04_IoAccessEn_MASK                                 0x1
#define DxF0x04_MemAccessEn_OFFSET                              1
#define DxF0x04_MemAccessEn_WIDTH                               1
#define DxF0x04_MemAccessEn_MASK                                0x2
#define DxF0x04_BusMasterEn_OFFSET                              2
#define DxF0x04_BusMasterEn_WIDTH                               1
#define DxF0x04_BusMasterEn_MASK                                0x4
#define DxF0x04_SpecialCycleEn_OFFSET                           3
#define DxF0x04_SpecialCycleEn_WIDTH                            1
#define DxF0x04_SpecialCycleEn_MASK                             0x8
#define DxF0x04_MemWriteInvalidateEn_OFFSET                     4
#define DxF0x04_MemWriteInvalidateEn_WIDTH                      1
#define DxF0x04_MemWriteInvalidateEn_MASK                       0x10
#define DxF0x04_PalSnoopEn_OFFSET                               5
#define DxF0x04_PalSnoopEn_WIDTH                                1
#define DxF0x04_PalSnoopEn_MASK                                 0x20
#define DxF0x04_ParityErrorEn_OFFSET                            6
#define DxF0x04_ParityErrorEn_WIDTH                             1
#define DxF0x04_ParityErrorEn_MASK                              0x40
#define DxF0x04_Stepping_OFFSET                                 7
#define DxF0x04_Stepping_WIDTH                                  1
#define DxF0x04_Stepping_MASK                                   0x80
#define DxF0x04_SerrEn_OFFSET                                   8
#define DxF0x04_SerrEn_WIDTH                                    1
#define DxF0x04_SerrEn_MASK                                     0x100
#define DxF0x04_FastB2BEn_OFFSET                                9
#define DxF0x04_FastB2BEn_WIDTH                                 1
#define DxF0x04_FastB2BEn_MASK                                  0x200
#define DxF0x04_IntDis_OFFSET                                   10
#define DxF0x04_IntDis_WIDTH                                    1
#define DxF0x04_IntDis_MASK                                     0x400
#define DxF0x04_Reserved_18_11_OFFSET                           11
#define DxF0x04_Reserved_18_11_WIDTH                            8
#define DxF0x04_Reserved_18_11_MASK                             0x7f800
#define DxF0x04_IntStatus_OFFSET                                19
#define DxF0x04_IntStatus_WIDTH                                 1
#define DxF0x04_IntStatus_MASK                                  0x80000
#define DxF0x04_CapList_OFFSET                                  20
#define DxF0x04_CapList_WIDTH                                   1
#define DxF0x04_CapList_MASK                                    0x100000
#define DxF0x04_PCI66En_OFFSET                                  21
#define DxF0x04_PCI66En_WIDTH                                   1
#define DxF0x04_PCI66En_MASK                                    0x200000
#define DxF0x04_UDFEn_OFFSET                                    22
#define DxF0x04_UDFEn_WIDTH                                     1
#define DxF0x04_UDFEn_MASK                                      0x400000
#define DxF0x04_FastBackCapable_OFFSET                          23
#define DxF0x04_FastBackCapable_WIDTH                           1
#define DxF0x04_FastBackCapable_MASK                            0x800000
#define DxF0x04_DataPerr_OFFSET                                 24
#define DxF0x04_DataPerr_WIDTH                                  1
#define DxF0x04_DataPerr_MASK                                   0x1000000
#define DxF0x04_DevselTiming_OFFSET                             25
#define DxF0x04_DevselTiming_WIDTH                              2
#define DxF0x04_DevselTiming_MASK                               0x6000000
#define DxF0x04_SignalTargetAbort_OFFSET                        27
#define DxF0x04_SignalTargetAbort_WIDTH                         1
#define DxF0x04_SignalTargetAbort_MASK                          0x8000000
#define DxF0x04_ReceivedTargetAbort_OFFSET                      28
#define DxF0x04_ReceivedTargetAbort_WIDTH                       1
#define DxF0x04_ReceivedTargetAbort_MASK                        0x10000000
#define DxF0x04_ReceivedMasterAbort_OFFSET                      29
#define DxF0x04_ReceivedMasterAbort_WIDTH                       1
#define DxF0x04_ReceivedMasterAbort_MASK                        0x20000000
#define DxF0x04_SignaledSystemError_OFFSET                      30
#define DxF0x04_SignaledSystemError_WIDTH                       1
#define DxF0x04_SignaledSystemError_MASK                        0x40000000
#define DxF0x04_ParityErrorDetected_OFFSET                      31
#define DxF0x04_ParityErrorDetected_WIDTH                       1
#define DxF0x04_ParityErrorDetected_MASK                        0x80000000

/// DxF0x04
typedef union {
  struct {                                                              ///<
    UINT32                                               IoAccessEn:1 ; ///<
    UINT32                                              MemAccessEn:1 ; ///<
    UINT32                                              BusMasterEn:1 ; ///<
    UINT32                                           SpecialCycleEn:1 ; ///<
    UINT32                                     MemWriteInvalidateEn:1 ; ///<
    UINT32                                               PalSnoopEn:1 ; ///<
    UINT32                                            ParityErrorEn:1 ; ///<
    UINT32                                                 Stepping:1 ; ///<
    UINT32                                                   SerrEn:1 ; ///<
    UINT32                                                FastB2BEn:1 ; ///<
    UINT32                                                   IntDis:1 ; ///<
    UINT32                                           Reserved_18_11:8 ; ///<
    UINT32                                                IntStatus:1 ; ///<
    UINT32                                                  CapList:1 ; ///<
    UINT32                                                  PCI66En:1 ; ///<
    UINT32                                                    UDFEn:1 ; ///<
    UINT32                                          FastBackCapable:1 ; ///<
    UINT32                                                 DataPerr:1 ; ///<
    UINT32                                             DevselTiming:2 ; ///<
    UINT32                                        SignalTargetAbort:1 ; ///<
    UINT32                                      ReceivedTargetAbort:1 ; ///<
    UINT32                                      ReceivedMasterAbort:1 ; ///<
    UINT32                                      SignaledSystemError:1 ; ///<
    UINT32                                      ParityErrorDetected:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x04_STRUCT;

// **** DxF0x08 Register Definition ****
// Address
#define DxF0x08_ADDRESS                                         0x8

// Type
#define DxF0x08_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x08_RevID_OFFSET                                    0
#define DxF0x08_RevID_WIDTH                                     8
#define DxF0x08_RevID_MASK                                      0xff
#define DxF0x08_ClassCode_OFFSET                                8
#define DxF0x08_ClassCode_WIDTH                                 24
#define DxF0x08_ClassCode_MASK                                  0xffffff00

/// DxF0x08
typedef union {
  struct {                                                              ///<
    UINT32                                                    RevID:8 ; ///<
    UINT32                                                ClassCode:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x08_STRUCT;

// **** DxF0x0C Register Definition ****
// Address
#define DxF0x0C_ADDRESS                                         0xc

// Type
#define DxF0x0C_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x0C_CacheLineSize_OFFSET                            0
#define DxF0x0C_CacheLineSize_WIDTH                             8
#define DxF0x0C_CacheLineSize_MASK                              0xff
#define DxF0x0C_LatencyTimer_OFFSET                             8
#define DxF0x0C_LatencyTimer_WIDTH                              8
#define DxF0x0C_LatencyTimer_MASK                               0xff00
#define DxF0x0C_HeaderTypeReg_OFFSET                            16
#define DxF0x0C_HeaderTypeReg_WIDTH                             8
#define DxF0x0C_HeaderTypeReg_MASK                              0xff0000
#define DxF0x0C_BIST_OFFSET                                     24
#define DxF0x0C_BIST_WIDTH                                      8
#define DxF0x0C_BIST_MASK                                       0xff000000

/// DxF0x0C
typedef union {
  struct {                                                              ///<
    UINT32                                            CacheLineSize:8 ; ///<
    UINT32                                             LatencyTimer:8 ; ///<
    UINT32                                            HeaderTypeReg:8 ; ///<
    UINT32                                                     BIST:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x0C_STRUCT;

// **** DxF0x18 Register Definition ****
// Address
#define DxF0x18_ADDRESS                                         0x18

// Type
#define DxF0x18_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x18_PrimaryBus_OFFSET                               0
#define DxF0x18_PrimaryBus_WIDTH                                8
#define DxF0x18_PrimaryBus_MASK                                 0xff
#define DxF0x18_SecondaryBus_OFFSET                             8
#define DxF0x18_SecondaryBus_WIDTH                              8
#define DxF0x18_SecondaryBus_MASK                               0xff00
#define DxF0x18_SubBusNumber_OFFSET                             16
#define DxF0x18_SubBusNumber_WIDTH                              8
#define DxF0x18_SubBusNumber_MASK                               0xff0000
#define DxF0x18_SecondaryLatencyTimer_OFFSET                    24
#define DxF0x18_SecondaryLatencyTimer_WIDTH                     8
#define DxF0x18_SecondaryLatencyTimer_MASK                      0xff000000

/// DxF0x18
typedef union {
  struct {                                                              ///<
    UINT32                                               PrimaryBus:8 ; ///<
    UINT32                                             SecondaryBus:8 ; ///<
    UINT32                                             SubBusNumber:8 ; ///<
    UINT32                                    SecondaryLatencyTimer:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x18_STRUCT;

// **** DxF0x1C Register Definition ****
// Address
#define DxF0x1C_ADDRESS                                         0x1c

// Type
#define DxF0x1C_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x1C_Reserved_3_0_OFFSET                             0
#define DxF0x1C_Reserved_3_0_WIDTH                              4
#define DxF0x1C_Reserved_3_0_MASK                               0xf
#define DxF0x1C_IOBase_15_12__OFFSET                            4
#define DxF0x1C_IOBase_15_12__WIDTH                             4
#define DxF0x1C_IOBase_15_12__MASK                              0xf0
#define DxF0x1C_Reserved_11_8_OFFSET                            8
#define DxF0x1C_Reserved_11_8_WIDTH                             4
#define DxF0x1C_Reserved_11_8_MASK                              0xf00
#define DxF0x1C_IOLimit_15_12__OFFSET                           12
#define DxF0x1C_IOLimit_15_12__WIDTH                            4
#define DxF0x1C_IOLimit_15_12__MASK                             0xf000
#define DxF0x1C_Reserved_19_16_OFFSET                           16
#define DxF0x1C_Reserved_19_16_WIDTH                            4
#define DxF0x1C_Reserved_19_16_MASK                             0xf0000
#define DxF0x1C_CapList_OFFSET                                  20
#define DxF0x1C_CapList_WIDTH                                   1
#define DxF0x1C_CapList_MASK                                    0x100000
#define DxF0x1C_PCI66En_OFFSET                                  21
#define DxF0x1C_PCI66En_WIDTH                                   1
#define DxF0x1C_PCI66En_MASK                                    0x200000
#define DxF0x1C_UDFEn_OFFSET                                    22
#define DxF0x1C_UDFEn_WIDTH                                     1
#define DxF0x1C_UDFEn_MASK                                      0x400000
#define DxF0x1C_FastBackCapable_OFFSET                          23
#define DxF0x1C_FastBackCapable_WIDTH                           1
#define DxF0x1C_FastBackCapable_MASK                            0x800000
#define DxF0x1C_MasterDataPerr_OFFSET                           24
#define DxF0x1C_MasterDataPerr_WIDTH                            1
#define DxF0x1C_MasterDataPerr_MASK                             0x1000000
#define DxF0x1C_DevselTiming_OFFSET                             25
#define DxF0x1C_DevselTiming_WIDTH                              2
#define DxF0x1C_DevselTiming_MASK                               0x6000000
#define DxF0x1C_SignalTargetAbort_OFFSET                        27
#define DxF0x1C_SignalTargetAbort_WIDTH                         1
#define DxF0x1C_SignalTargetAbort_MASK                          0x8000000
#define DxF0x1C_ReceivedTargetAbort_OFFSET                      28
#define DxF0x1C_ReceivedTargetAbort_WIDTH                       1
#define DxF0x1C_ReceivedTargetAbort_MASK                        0x10000000
#define DxF0x1C_ReceivedMasterAbort_OFFSET                      29
#define DxF0x1C_ReceivedMasterAbort_WIDTH                       1
#define DxF0x1C_ReceivedMasterAbort_MASK                        0x20000000
#define DxF0x1C_ReceivedSystemError_OFFSET                      30
#define DxF0x1C_ReceivedSystemError_WIDTH                       1
#define DxF0x1C_ReceivedSystemError_MASK                        0x40000000
#define DxF0x1C_ParityErrorDetected_OFFSET                      31
#define DxF0x1C_ParityErrorDetected_WIDTH                       1
#define DxF0x1C_ParityErrorDetected_MASK                        0x80000000

/// DxF0x1C
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_3_0:4 ; ///<
    UINT32                                            IOBase_15_12_:4 ; ///<
    UINT32                                            Reserved_11_8:4 ; ///<
    UINT32                                           IOLimit_15_12_:4 ; ///<
    UINT32                                           Reserved_19_16:4 ; ///<
    UINT32                                                  CapList:1 ; ///<
    UINT32                                                  PCI66En:1 ; ///<
    UINT32                                                    UDFEn:1 ; ///<
    UINT32                                          FastBackCapable:1 ; ///<
    UINT32                                           MasterDataPerr:1 ; ///<
    UINT32                                             DevselTiming:2 ; ///<
    UINT32                                        SignalTargetAbort:1 ; ///<
    UINT32                                      ReceivedTargetAbort:1 ; ///<
    UINT32                                      ReceivedMasterAbort:1 ; ///<
    UINT32                                      ReceivedSystemError:1 ; ///<
    UINT32                                      ParityErrorDetected:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x1C_STRUCT;

// **** DxF0x20 Register Definition ****
// Address
#define DxF0x20_ADDRESS                                         0x20

// Type
#define DxF0x20_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x20_Reserved_3_0_OFFSET                             0
#define DxF0x20_Reserved_3_0_WIDTH                              4
#define DxF0x20_Reserved_3_0_MASK                               0xf
#define DxF0x20_MemBase_OFFSET                                  4
#define DxF0x20_MemBase_WIDTH                                   12
#define DxF0x20_MemBase_MASK                                    0xfff0
#define DxF0x20_Reserved_19_16_OFFSET                           16
#define DxF0x20_Reserved_19_16_WIDTH                            4
#define DxF0x20_Reserved_19_16_MASK                             0xf0000
#define DxF0x20_MemLimit_OFFSET                                 20
#define DxF0x20_MemLimit_WIDTH                                  12
#define DxF0x20_MemLimit_MASK                                   0xfff00000

/// DxF0x20
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_3_0:4 ; ///<
    UINT32                                                  MemBase:12; ///<
    UINT32                                           Reserved_19_16:4 ; ///<
    UINT32                                                 MemLimit:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x20_STRUCT;

// **** DxF0x24 Register Definition ****
// Address
#define DxF0x24_ADDRESS                                         0x24

// Type
#define DxF0x24_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x24_PrefMemBaseR_OFFSET                             0
#define DxF0x24_PrefMemBaseR_WIDTH                              4
#define DxF0x24_PrefMemBaseR_MASK                               0xf
#define DxF0x24_PrefMemBase_31_20__OFFSET                       4
#define DxF0x24_PrefMemBase_31_20__WIDTH                        12
#define DxF0x24_PrefMemBase_31_20__MASK                         0xfff0
#define DxF0x24_PrefMemLimitR_OFFSET                            16
#define DxF0x24_PrefMemLimitR_WIDTH                             4
#define DxF0x24_PrefMemLimitR_MASK                              0xf0000
#define DxF0x24_PrefMemLimit_OFFSET                             20
#define DxF0x24_PrefMemLimit_WIDTH                              12
#define DxF0x24_PrefMemLimit_MASK                               0xfff00000

/// DxF0x24
typedef union {
  struct {                                                              ///<
    UINT32                                             PrefMemBaseR:4 ; ///<
    UINT32                                       PrefMemBase_31_20_:12; ///<
    UINT32                                            PrefMemLimitR:4 ; ///<
    UINT32                                             PrefMemLimit:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x24_STRUCT;

// **** DxF0x28 Register Definition ****
// Address
#define DxF0x28_ADDRESS                                         0x28

// Type
#define DxF0x28_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x28_PrefMemBase_63_32__OFFSET                       0
#define DxF0x28_PrefMemBase_63_32__WIDTH                        32
#define DxF0x28_PrefMemBase_63_32__MASK                         0xffffffff

/// DxF0x28
typedef union {
  struct {                                                              ///<
    UINT32                                       PrefMemBase_63_32_:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x28_STRUCT;

// **** DxF0x2C Register Definition ****
// Address
#define DxF0x2C_ADDRESS                                         0x2c

// Type
#define DxF0x2C_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x2C_PrefMemLimit_63_32__OFFSET                      0
#define DxF0x2C_PrefMemLimit_63_32__WIDTH                       32
#define DxF0x2C_PrefMemLimit_63_32__MASK                        0xffffffff

/// DxF0x2C
typedef union {
  struct {                                                              ///<
    UINT32                                      PrefMemLimit_63_32_:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x2C_STRUCT;

// **** DxF0x30 Register Definition ****
// Address
#define DxF0x30_ADDRESS                                         0x30

// Type
#define DxF0x30_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x30_IOBase_31_16__OFFSET                            0
#define DxF0x30_IOBase_31_16__WIDTH                             16
#define DxF0x30_IOBase_31_16__MASK                              0xffff
#define DxF0x30_IOLimit_31_16__OFFSET                           16
#define DxF0x30_IOLimit_31_16__WIDTH                            16
#define DxF0x30_IOLimit_31_16__MASK                             0xffff0000

/// DxF0x30
typedef union {
  struct {                                                              ///<
    UINT32                                            IOBase_31_16_:16; ///<
    UINT32                                           IOLimit_31_16_:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x30_STRUCT;

// **** DxF0x34 Register Definition ****
// Address
#define DxF0x34_ADDRESS                                         0x34

// Type
#define DxF0x34_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x34_CapPtr_OFFSET                                   0
#define DxF0x34_CapPtr_WIDTH                                    8
#define DxF0x34_CapPtr_MASK                                     0xff
#define DxF0x34_Reserved_31_8_OFFSET                            8
#define DxF0x34_Reserved_31_8_WIDTH                             24
#define DxF0x34_Reserved_31_8_MASK                              0xffffff00

/// DxF0x34
typedef union {
  struct {                                                              ///<
    UINT32                                                   CapPtr:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x34_STRUCT;

// **** DxF0x3C Register Definition ****
// Address
#define DxF0x3C_ADDRESS                                         0x3c

// Type
#define DxF0x3C_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x3C_IntLine_OFFSET                                  0
#define DxF0x3C_IntLine_WIDTH                                   8
#define DxF0x3C_IntLine_MASK                                    0xff
#define DxF0x3C_IntPin_OFFSET                                   8
#define DxF0x3C_IntPin_WIDTH                                    3
#define DxF0x3C_IntPin_MASK                                     0x700
#define DxF0x3C_IntPinR_OFFSET                                  11
#define DxF0x3C_IntPinR_WIDTH                                   5
#define DxF0x3C_IntPinR_MASK                                    0xf800
#define DxF0x3C_ParityResponseEn_OFFSET                         16
#define DxF0x3C_ParityResponseEn_WIDTH                          1
#define DxF0x3C_ParityResponseEn_MASK                           0x10000
#define DxF0x3C_SerrEn_OFFSET                                   17
#define DxF0x3C_SerrEn_WIDTH                                    1
#define DxF0x3C_SerrEn_MASK                                     0x20000
#define DxF0x3C_IsaEn_OFFSET                                    18
#define DxF0x3C_IsaEn_WIDTH                                     1
#define DxF0x3C_IsaEn_MASK                                      0x40000
#define DxF0x3C_VgaEn_OFFSET                                    19
#define DxF0x3C_VgaEn_WIDTH                                     1
#define DxF0x3C_VgaEn_MASK                                      0x80000
#define DxF0x3C_Vga16En_OFFSET                                  20
#define DxF0x3C_Vga16En_WIDTH                                   1
#define DxF0x3C_Vga16En_MASK                                    0x100000
#define DxF0x3C_MasterAbortMode_OFFSET                          21
#define DxF0x3C_MasterAbortMode_WIDTH                           1
#define DxF0x3C_MasterAbortMode_MASK                            0x200000
#define DxF0x3C_SecondaryBusReset_OFFSET                        22
#define DxF0x3C_SecondaryBusReset_WIDTH                         1
#define DxF0x3C_SecondaryBusReset_MASK                          0x400000
#define DxF0x3C_FastB2BCap_OFFSET                               23
#define DxF0x3C_FastB2BCap_WIDTH                                1
#define DxF0x3C_FastB2BCap_MASK                                 0x800000
#define DxF0x3C_Reserved_31_24_OFFSET                           24
#define DxF0x3C_Reserved_31_24_WIDTH                            8
#define DxF0x3C_Reserved_31_24_MASK                             0xff000000

/// DxF0x3C
typedef union {
  struct {                                                              ///<
    UINT32                                                  IntLine:8 ; ///<
    UINT32                                                   IntPin:3 ; ///<
    UINT32                                                  IntPinR:5 ; ///<
    UINT32                                         ParityResponseEn:1 ; ///<
    UINT32                                                   SerrEn:1 ; ///<
    UINT32                                                    IsaEn:1 ; ///<
    UINT32                                                    VgaEn:1 ; ///<
    UINT32                                                  Vga16En:1 ; ///<
    UINT32                                          MasterAbortMode:1 ; ///<
    UINT32                                        SecondaryBusReset:1 ; ///<
    UINT32                                               FastB2BCap:1 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x3C_STRUCT;

// **** DxF0x50 Register Definition ****
// Address
#define DxF0x50_ADDRESS                                         0x50

// Type
#define DxF0x50_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x50_CapID_OFFSET                                    0
#define DxF0x50_CapID_WIDTH                                     8
#define DxF0x50_CapID_MASK                                      0xff
#define DxF0x50_NextPtr_OFFSET                                  8
#define DxF0x50_NextPtr_WIDTH                                   8
#define DxF0x50_NextPtr_MASK                                    0xff00
#define DxF0x50_Version_OFFSET                                  16
#define DxF0x50_Version_WIDTH                                   3
#define DxF0x50_Version_MASK                                    0x70000
#define DxF0x50_PmeClock_OFFSET                                 19
#define DxF0x50_PmeClock_WIDTH                                  1
#define DxF0x50_PmeClock_MASK                                   0x80000
#define DxF0x50_Reserved_20_20_OFFSET                           20
#define DxF0x50_Reserved_20_20_WIDTH                            1
#define DxF0x50_Reserved_20_20_MASK                             0x100000
#define DxF0x50_DevSpecificInit_OFFSET                          21
#define DxF0x50_DevSpecificInit_WIDTH                           1
#define DxF0x50_DevSpecificInit_MASK                            0x200000
#define DxF0x50_AuxCurrent_OFFSET                               22
#define DxF0x50_AuxCurrent_WIDTH                                3
#define DxF0x50_AuxCurrent_MASK                                 0x1c00000
#define DxF0x50_D1Support_OFFSET                                25
#define DxF0x50_D1Support_WIDTH                                 1
#define DxF0x50_D1Support_MASK                                  0x2000000
#define DxF0x50_D2Support_OFFSET                                26
#define DxF0x50_D2Support_WIDTH                                 1
#define DxF0x50_D2Support_MASK                                  0x4000000
#define DxF0x50_PmeSupport_OFFSET                               27
#define DxF0x50_PmeSupport_WIDTH                                5
#define DxF0x50_PmeSupport_MASK                                 0xf8000000

/// DxF0x50
typedef union {
  struct {                                                              ///<
    UINT32                                                    CapID:8 ; ///<
    UINT32                                                  NextPtr:8 ; ///<
    UINT32                                                  Version:3 ; ///<
    UINT32                                                 PmeClock:1 ; ///<
    UINT32                                           Reserved_20_20:1 ; ///<
    UINT32                                          DevSpecificInit:1 ; ///<
    UINT32                                               AuxCurrent:3 ; ///<
    UINT32                                                D1Support:1 ; ///<
    UINT32                                                D2Support:1 ; ///<
    UINT32                                               PmeSupport:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x50_STRUCT;

// **** DxF0x54 Register Definition ****
// Address
#define DxF0x54_ADDRESS                                         0x54

// Type
#define DxF0x54_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x54_PowerState_OFFSET                               0
#define DxF0x54_PowerState_WIDTH                                2
#define DxF0x54_PowerState_MASK                                 0x3
#define DxF0x54_Reserved_2_2_OFFSET                             2
#define DxF0x54_Reserved_2_2_WIDTH                              1
#define DxF0x54_Reserved_2_2_MASK                               0x4
#define DxF0x54_NoSoftReset_OFFSET                              3
#define DxF0x54_NoSoftReset_WIDTH                               1
#define DxF0x54_NoSoftReset_MASK                                0x8
#define DxF0x54_Reserved_7_4_OFFSET                             4
#define DxF0x54_Reserved_7_4_WIDTH                              4
#define DxF0x54_Reserved_7_4_MASK                               0xf0
#define DxF0x54_PmeEn_OFFSET                                    8
#define DxF0x54_PmeEn_WIDTH                                     1
#define DxF0x54_PmeEn_MASK                                      0x100
#define DxF0x54_DataSelect_OFFSET                               9
#define DxF0x54_DataSelect_WIDTH                                4
#define DxF0x54_DataSelect_MASK                                 0x1e00
#define DxF0x54_DataScale_OFFSET                                13
#define DxF0x54_DataScale_WIDTH                                 2
#define DxF0x54_DataScale_MASK                                  0x6000
#define DxF0x54_PmeStatus_OFFSET                                15
#define DxF0x54_PmeStatus_WIDTH                                 1
#define DxF0x54_PmeStatus_MASK                                  0x8000
#define DxF0x54_Reserved_21_16_OFFSET                           16
#define DxF0x54_Reserved_21_16_WIDTH                            6
#define DxF0x54_Reserved_21_16_MASK                             0x3f0000
#define DxF0x54_B2B3Support_OFFSET                              22
#define DxF0x54_B2B3Support_WIDTH                               1
#define DxF0x54_B2B3Support_MASK                                0x400000
#define DxF0x54_BusPwrEn_OFFSET                                 23
#define DxF0x54_BusPwrEn_WIDTH                                  1
#define DxF0x54_BusPwrEn_MASK                                   0x800000
#define DxF0x54_PmeData_OFFSET                                  24
#define DxF0x54_PmeData_WIDTH                                   8
#define DxF0x54_PmeData_MASK                                    0xff000000

/// DxF0x54
typedef union {
  struct {                                                              ///<
    UINT32                                               PowerState:2 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                              NoSoftReset:1 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                    PmeEn:1 ; ///<
    UINT32                                               DataSelect:4 ; ///<
    UINT32                                                DataScale:2 ; ///<
    UINT32                                                PmeStatus:1 ; ///<
    UINT32                                           Reserved_21_16:6 ; ///<
    UINT32                                              B2B3Support:1 ; ///<
    UINT32                                                 BusPwrEn:1 ; ///<
    UINT32                                                  PmeData:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x54_STRUCT;

// **** DxF0x58 Register Definition ****
// Address
#define DxF0x58_ADDRESS                                         0x58

// Type
#define DxF0x58_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x58_CapID_OFFSET                                    0
#define DxF0x58_CapID_WIDTH                                     8
#define DxF0x58_CapID_MASK                                      0xff
#define DxF0x58_NextPtr_OFFSET                                  8
#define DxF0x58_NextPtr_WIDTH                                   8
#define DxF0x58_NextPtr_MASK                                    0xff00
#define DxF0x58_Version_OFFSET                                  16
#define DxF0x58_Version_WIDTH                                   4
#define DxF0x58_Version_MASK                                    0xf0000
#define DxF0x58_DeviceType_OFFSET                               20
#define DxF0x58_DeviceType_WIDTH                                4
#define DxF0x58_DeviceType_MASK                                 0xf00000
#define DxF0x58_SlotImplemented_OFFSET                          24
#define DxF0x58_SlotImplemented_WIDTH                           1
#define DxF0x58_SlotImplemented_MASK                            0x1000000
#define DxF0x58_IntMessageNum_OFFSET                            25
#define DxF0x58_IntMessageNum_WIDTH                             5
#define DxF0x58_IntMessageNum_MASK                              0x3e000000
#define DxF0x58_Reserved_31_30_OFFSET                           30
#define DxF0x58_Reserved_31_30_WIDTH                            2
#define DxF0x58_Reserved_31_30_MASK                             0xc0000000

/// DxF0x58
typedef union {
  struct {                                                              ///<
    UINT32                                                    CapID:8 ; ///<
    UINT32                                                  NextPtr:8 ; ///<
    UINT32                                                  Version:4 ; ///<
    UINT32                                               DeviceType:4 ; ///<
    UINT32                                          SlotImplemented:1 ; ///<
    UINT32                                            IntMessageNum:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x58_STRUCT;

// **** DxF0x5C Register Definition ****
// Address
#define DxF0x5C_ADDRESS                                         0x5c

// Type
#define DxF0x5C_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x5C_MaxPayloadSupport_OFFSET                        0
#define DxF0x5C_MaxPayloadSupport_WIDTH                         3
#define DxF0x5C_MaxPayloadSupport_MASK                          0x7
#define DxF0x5C_PhantomFunc_OFFSET                              3
#define DxF0x5C_PhantomFunc_WIDTH                               2
#define DxF0x5C_PhantomFunc_MASK                                0x18
#define DxF0x5C_ExtendedTag_OFFSET                              5
#define DxF0x5C_ExtendedTag_WIDTH                               1
#define DxF0x5C_ExtendedTag_MASK                                0x20
#define DxF0x5C_L0SAcceptableLatency_OFFSET                     6
#define DxF0x5C_L0SAcceptableLatency_WIDTH                      3
#define DxF0x5C_L0SAcceptableLatency_MASK                       0x1c0
#define DxF0x5C_L1AcceptableLatency_OFFSET                      9
#define DxF0x5C_L1AcceptableLatency_WIDTH                       3
#define DxF0x5C_L1AcceptableLatency_MASK                        0xe00
#define DxF0x5C_Reserved_14_12_OFFSET                           12
#define DxF0x5C_Reserved_14_12_WIDTH                            3
#define DxF0x5C_Reserved_14_12_MASK                             0x7000
#define DxF0x5C_RoleBasedErrReporting_OFFSET                    15
#define DxF0x5C_RoleBasedErrReporting_WIDTH                     1
#define DxF0x5C_RoleBasedErrReporting_MASK                      0x8000
#define DxF0x5C_Reserved_17_16_OFFSET                           16
#define DxF0x5C_Reserved_17_16_WIDTH                            2
#define DxF0x5C_Reserved_17_16_MASK                             0x30000
#define DxF0x5C_CapturedSlotPowerLimit_OFFSET                   18
#define DxF0x5C_CapturedSlotPowerLimit_WIDTH                    8
#define DxF0x5C_CapturedSlotPowerLimit_MASK                     0x3fc0000
#define DxF0x5C_CapturedSlotPowerScale_OFFSET                   26
#define DxF0x5C_CapturedSlotPowerScale_WIDTH                    2
#define DxF0x5C_CapturedSlotPowerScale_MASK                     0xc000000
#define DxF0x5C_FlrCapable_OFFSET                               28
#define DxF0x5C_FlrCapable_WIDTH                                1
#define DxF0x5C_FlrCapable_MASK                                 0x10000000
#define DxF0x5C_Reserved_31_29_OFFSET                           29
#define DxF0x5C_Reserved_31_29_WIDTH                            3
#define DxF0x5C_Reserved_31_29_MASK                             0xe0000000

/// DxF0x5C
typedef union {
  struct {                                                              ///<
    UINT32                                        MaxPayloadSupport:3 ; ///<
    UINT32                                              PhantomFunc:2 ; ///<
    UINT32                                              ExtendedTag:1 ; ///<
    UINT32                                     L0SAcceptableLatency:3 ; ///<
    UINT32                                      L1AcceptableLatency:3 ; ///<
    UINT32                                           Reserved_14_12:3 ; ///<
    UINT32                                    RoleBasedErrReporting:1 ; ///<
    UINT32                                           Reserved_17_16:2 ; ///<
    UINT32                                   CapturedSlotPowerLimit:8 ; ///<
    UINT32                                   CapturedSlotPowerScale:2 ; ///<
    UINT32                                               FlrCapable:1 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x5C_STRUCT;

// **** DxF0x60 Register Definition ****
// Address
#define DxF0x60_ADDRESS                                         0x60

// Type
#define DxF0x60_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x60_CorrErrEn_OFFSET                                0
#define DxF0x60_CorrErrEn_WIDTH                                 1
#define DxF0x60_CorrErrEn_MASK                                  0x1
#define DxF0x60_NonFatalErrEn_OFFSET                            1
#define DxF0x60_NonFatalErrEn_WIDTH                             1
#define DxF0x60_NonFatalErrEn_MASK                              0x2
#define DxF0x60_FatalErrEn_OFFSET                               2
#define DxF0x60_FatalErrEn_WIDTH                                1
#define DxF0x60_FatalErrEn_MASK                                 0x4
#define DxF0x60_UsrReportEn_OFFSET                              3
#define DxF0x60_UsrReportEn_WIDTH                               1
#define DxF0x60_UsrReportEn_MASK                                0x8
#define DxF0x60_RelaxedOrdEn_OFFSET                             4
#define DxF0x60_RelaxedOrdEn_WIDTH                              1
#define DxF0x60_RelaxedOrdEn_MASK                               0x10
#define DxF0x60_MaxPayloadSize_OFFSET                           5
#define DxF0x60_MaxPayloadSize_WIDTH                            3
#define DxF0x60_MaxPayloadSize_MASK                             0xe0
#define DxF0x60_ExtendedTagEn_OFFSET                            8
#define DxF0x60_ExtendedTagEn_WIDTH                             1
#define DxF0x60_ExtendedTagEn_MASK                              0x100
#define DxF0x60_PhantomFuncEn_OFFSET                            9
#define DxF0x60_PhantomFuncEn_WIDTH                             1
#define DxF0x60_PhantomFuncEn_MASK                              0x200
#define DxF0x60_AuxPowerPmEn_OFFSET                             10
#define DxF0x60_AuxPowerPmEn_WIDTH                              1
#define DxF0x60_AuxPowerPmEn_MASK                               0x400
#define DxF0x60_NoSnoopEnable_OFFSET                            11
#define DxF0x60_NoSnoopEnable_WIDTH                             1
#define DxF0x60_NoSnoopEnable_MASK                              0x800
#define DxF0x60_MaxRequestSize_OFFSET                           12
#define DxF0x60_MaxRequestSize_WIDTH                            3
#define DxF0x60_MaxRequestSize_MASK                             0x7000
#define DxF0x60_BridgeCfgRetryEn_OFFSET                         15
#define DxF0x60_BridgeCfgRetryEn_WIDTH                          1
#define DxF0x60_BridgeCfgRetryEn_MASK                           0x8000
#define DxF0x60_CorrErr_OFFSET                                  16
#define DxF0x60_CorrErr_WIDTH                                   1
#define DxF0x60_CorrErr_MASK                                    0x10000
#define DxF0x60_NonFatalErr_OFFSET                              17
#define DxF0x60_NonFatalErr_WIDTH                               1
#define DxF0x60_NonFatalErr_MASK                                0x20000
#define DxF0x60_FatalErr_OFFSET                                 18
#define DxF0x60_FatalErr_WIDTH                                  1
#define DxF0x60_FatalErr_MASK                                   0x40000
#define DxF0x60_UsrDetected_OFFSET                              19
#define DxF0x60_UsrDetected_WIDTH                               1
#define DxF0x60_UsrDetected_MASK                                0x80000
#define DxF0x60_AuxPwr_OFFSET                                   20
#define DxF0x60_AuxPwr_WIDTH                                    1
#define DxF0x60_AuxPwr_MASK                                     0x100000
#define DxF0x60_TransactionsPending_OFFSET                      21
#define DxF0x60_TransactionsPending_WIDTH                       1
#define DxF0x60_TransactionsPending_MASK                        0x200000
#define DxF0x60_Reserved_31_22_OFFSET                           22
#define DxF0x60_Reserved_31_22_WIDTH                            10
#define DxF0x60_Reserved_31_22_MASK                             0xffc00000

/// DxF0x60
typedef union {
  struct {                                                              ///<
    UINT32                                                CorrErrEn:1 ; ///<
    UINT32                                            NonFatalErrEn:1 ; ///<
    UINT32                                               FatalErrEn:1 ; ///<
    UINT32                                              UsrReportEn:1 ; ///<
    UINT32                                             RelaxedOrdEn:1 ; ///<
    UINT32                                           MaxPayloadSize:3 ; ///<
    UINT32                                            ExtendedTagEn:1 ; ///<
    UINT32                                            PhantomFuncEn:1 ; ///<
    UINT32                                             AuxPowerPmEn:1 ; ///<
    UINT32                                            NoSnoopEnable:1 ; ///<
    UINT32                                           MaxRequestSize:3 ; ///<
    UINT32                                         BridgeCfgRetryEn:1 ; ///<
    UINT32                                                  CorrErr:1 ; ///<
    UINT32                                              NonFatalErr:1 ; ///<
    UINT32                                                 FatalErr:1 ; ///<
    UINT32                                              UsrDetected:1 ; ///<
    UINT32                                                   AuxPwr:1 ; ///<
    UINT32                                      TransactionsPending:1 ; ///<
    UINT32                                           Reserved_31_22:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x60_STRUCT;

// **** DxF0x64 Register Definition ****
// Address
#define DxF0x64_ADDRESS                                         0x64

// Type
#define DxF0x64_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x64_LinkSpeed_OFFSET                                0
#define DxF0x64_LinkSpeed_WIDTH                                 4
#define DxF0x64_LinkSpeed_MASK                                  0xf
#define DxF0x64_LinkWidth_OFFSET                                4
#define DxF0x64_LinkWidth_WIDTH                                 6
#define DxF0x64_LinkWidth_MASK                                  0x3f0
#define DxF0x64_PMSupport_OFFSET                                10
#define DxF0x64_PMSupport_WIDTH                                 2
#define DxF0x64_PMSupport_MASK                                  0xc00
#define DxF0x64_L0sExitLatency_OFFSET                           12
#define DxF0x64_L0sExitLatency_WIDTH                            3
#define DxF0x64_L0sExitLatency_MASK                             0x7000
#define DxF0x64_L1ExitLatency_OFFSET                            15
#define DxF0x64_L1ExitLatency_WIDTH                             3
#define DxF0x64_L1ExitLatency_MASK                              0x38000
#define DxF0x64_ClockPowerManagement_OFFSET                     18
#define DxF0x64_ClockPowerManagement_WIDTH                      1
#define DxF0x64_ClockPowerManagement_MASK                       0x40000
#define DxF0x64_SurpriseDownErrReporting_OFFSET                 19
#define DxF0x64_SurpriseDownErrReporting_WIDTH                  1
#define DxF0x64_SurpriseDownErrReporting_MASK                   0x80000
#define DxF0x64_DlActiveReportingCapable_OFFSET                 20
#define DxF0x64_DlActiveReportingCapable_WIDTH                  1
#define DxF0x64_DlActiveReportingCapable_MASK                   0x100000
#define DxF0x64_LinkBWNotificationCap_OFFSET                    21
#define DxF0x64_LinkBWNotificationCap_WIDTH                     1
#define DxF0x64_LinkBWNotificationCap_MASK                      0x200000
#define DxF0x64_AspmOptionalityCompliance_OFFSET                22
#define DxF0x64_AspmOptionalityCompliance_WIDTH                 1
#define DxF0x64_AspmOptionalityCompliance_MASK                  0x400000
#define DxF0x64_Reserved_23_23_OFFSET                           23
#define DxF0x64_Reserved_23_23_WIDTH                            1
#define DxF0x64_Reserved_23_23_MASK                             0x800000
#define DxF0x64_PortNumber_OFFSET                               24
#define DxF0x64_PortNumber_WIDTH                                8
#define DxF0x64_PortNumber_MASK                                 0xff000000

/// DxF0x64
typedef union {
  struct {                                                              ///<
    UINT32                                                LinkSpeed:4 ; ///<
    UINT32                                                LinkWidth:6 ; ///<
    UINT32                                                PMSupport:2 ; ///<
    UINT32                                           L0sExitLatency:3 ; ///<
    UINT32                                            L1ExitLatency:3 ; ///<
    UINT32                                     ClockPowerManagement:1 ; ///<
    UINT32                                 SurpriseDownErrReporting:1 ; ///<
    UINT32                                 DlActiveReportingCapable:1 ; ///<
    UINT32                                    LinkBWNotificationCap:1 ; ///<
    UINT32                                AspmOptionalityCompliance:1 ; ///<
    UINT32                                           Reserved_23_23:1 ; ///<
    UINT32                                               PortNumber:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x64_STRUCT;

// **** DxF0x68 Register Definition ****
// Address
#define DxF0x68_ADDRESS                                         0x68

// Type
#define DxF0x68_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x68_PmControl_OFFSET                                0
#define DxF0x68_PmControl_WIDTH                                 2
#define DxF0x68_PmControl_MASK                                  0x3
#define DxF0x68_Reserved_2_2_OFFSET                             2
#define DxF0x68_Reserved_2_2_WIDTH                              1
#define DxF0x68_Reserved_2_2_MASK                               0x4
#define DxF0x68_ReadCplBoundary_OFFSET                          3
#define DxF0x68_ReadCplBoundary_WIDTH                           1
#define DxF0x68_ReadCplBoundary_MASK                            0x8
#define DxF0x68_LinkDis_OFFSET                                  4
#define DxF0x68_LinkDis_WIDTH                                   1
#define DxF0x68_LinkDis_MASK                                    0x10
#define DxF0x68_RetrainLink_OFFSET                              5
#define DxF0x68_RetrainLink_WIDTH                               1
#define DxF0x68_RetrainLink_MASK                                0x20
#define DxF0x68_CommonClockCfg_OFFSET                           6
#define DxF0x68_CommonClockCfg_WIDTH                            1
#define DxF0x68_CommonClockCfg_MASK                             0x40
#define DxF0x68_ExtendedSync_OFFSET                             7
#define DxF0x68_ExtendedSync_WIDTH                              1
#define DxF0x68_ExtendedSync_MASK                               0x80
#define DxF0x68_ClockPowerManagementEn_OFFSET                   8
#define DxF0x68_ClockPowerManagementEn_WIDTH                    1
#define DxF0x68_ClockPowerManagementEn_MASK                     0x100
#define DxF0x68_HWAutonomousWidthDisable_OFFSET                 9
#define DxF0x68_HWAutonomousWidthDisable_WIDTH                  1
#define DxF0x68_HWAutonomousWidthDisable_MASK                   0x200
#define DxF0x68_LinkBWManagementEn_OFFSET                       10
#define DxF0x68_LinkBWManagementEn_WIDTH                        1
#define DxF0x68_LinkBWManagementEn_MASK                         0x400
#define DxF0x68_LinkAutonomousBWIntEn_OFFSET                    11
#define DxF0x68_LinkAutonomousBWIntEn_WIDTH                     1
#define DxF0x68_LinkAutonomousBWIntEn_MASK                      0x800
#define DxF0x68_Reserved_15_12_OFFSET                           12
#define DxF0x68_Reserved_15_12_WIDTH                            4
#define DxF0x68_Reserved_15_12_MASK                             0xf000
#define DxF0x68_LinkSpeed_OFFSET                                16
#define DxF0x68_LinkSpeed_WIDTH                                 4
#define DxF0x68_LinkSpeed_MASK                                  0xf0000
#define DxF0x68_NegotiatedLinkWidth_OFFSET                      20
#define DxF0x68_NegotiatedLinkWidth_WIDTH                       6
#define DxF0x68_NegotiatedLinkWidth_MASK                        0x3f00000
#define DxF0x68_Reserved_26_26_OFFSET                           26
#define DxF0x68_Reserved_26_26_WIDTH                            1
#define DxF0x68_Reserved_26_26_MASK                             0x4000000
#define DxF0x68_LinkTraining_OFFSET                             27
#define DxF0x68_LinkTraining_WIDTH                              1
#define DxF0x68_LinkTraining_MASK                               0x8000000
#define DxF0x68_SlotClockCfg_OFFSET                             28
#define DxF0x68_SlotClockCfg_WIDTH                              1
#define DxF0x68_SlotClockCfg_MASK                               0x10000000
#define DxF0x68_DlActive_OFFSET                                 29
#define DxF0x68_DlActive_WIDTH                                  1
#define DxF0x68_DlActive_MASK                                   0x20000000
#define DxF0x68_LinkBWManagementStatus_OFFSET                   30
#define DxF0x68_LinkBWManagementStatus_WIDTH                    1
#define DxF0x68_LinkBWManagementStatus_MASK                     0x40000000
#define DxF0x68_LinkAutonomousBWStatus_OFFSET                   31
#define DxF0x68_LinkAutonomousBWStatus_WIDTH                    1
#define DxF0x68_LinkAutonomousBWStatus_MASK                     0x80000000

/// DxF0x68
typedef union {
  struct {                                                              ///<
    UINT32                                                PmControl:2 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                          ReadCplBoundary:1 ; ///<
    UINT32                                                  LinkDis:1 ; ///<
    UINT32                                              RetrainLink:1 ; ///<
    UINT32                                           CommonClockCfg:1 ; ///<
    UINT32                                             ExtendedSync:1 ; ///<
    UINT32                                   ClockPowerManagementEn:1 ; ///<
    UINT32                                 HWAutonomousWidthDisable:1 ; ///<
    UINT32                                       LinkBWManagementEn:1 ; ///<
    UINT32                                    LinkAutonomousBWIntEn:1 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                                LinkSpeed:4 ; ///<
    UINT32                                      NegotiatedLinkWidth:6 ; ///<
    UINT32                                           Reserved_26_26:1 ; ///<
    UINT32                                             LinkTraining:1 ; ///<
    UINT32                                             SlotClockCfg:1 ; ///<
    UINT32                                                 DlActive:1 ; ///<
    UINT32                                   LinkBWManagementStatus:1 ; ///<
    UINT32                                   LinkAutonomousBWStatus:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x68_STRUCT;

// **** DxF0x6C Register Definition ****
// Address
#define DxF0x6C_ADDRESS                                         0x6c

// Type
#define DxF0x6C_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x6C_AttnButtonPresent_OFFSET                        0
#define DxF0x6C_AttnButtonPresent_WIDTH                         1
#define DxF0x6C_AttnButtonPresent_MASK                          0x1
#define DxF0x6C_PwrControllerPresent_OFFSET                     1
#define DxF0x6C_PwrControllerPresent_WIDTH                      1
#define DxF0x6C_PwrControllerPresent_MASK                       0x2
#define DxF0x6C_MrlSensorPresent_OFFSET                         2
#define DxF0x6C_MrlSensorPresent_WIDTH                          1
#define DxF0x6C_MrlSensorPresent_MASK                           0x4
#define DxF0x6C_AttnIndicatorPresent_OFFSET                     3
#define DxF0x6C_AttnIndicatorPresent_WIDTH                      1
#define DxF0x6C_AttnIndicatorPresent_MASK                       0x8
#define DxF0x6C_PwrIndicatorPresent_OFFSET                      4
#define DxF0x6C_PwrIndicatorPresent_WIDTH                       1
#define DxF0x6C_PwrIndicatorPresent_MASK                        0x10
#define DxF0x6C_HotplugSurprise_OFFSET                          5
#define DxF0x6C_HotplugSurprise_WIDTH                           1
#define DxF0x6C_HotplugSurprise_MASK                            0x20
#define DxF0x6C_HotplugCapable_OFFSET                           6
#define DxF0x6C_HotplugCapable_WIDTH                            1
#define DxF0x6C_HotplugCapable_MASK                             0x40
#define DxF0x6C_SlotPwrLimitValue_OFFSET                        7
#define DxF0x6C_SlotPwrLimitValue_WIDTH                         8
#define DxF0x6C_SlotPwrLimitValue_MASK                          0x7f80
#define DxF0x6C_SlotPwrLimitScale_OFFSET                        15
#define DxF0x6C_SlotPwrLimitScale_WIDTH                         2
#define DxF0x6C_SlotPwrLimitScale_MASK                          0x18000
#define DxF0x6C_ElecMechIlPresent_OFFSET                        17
#define DxF0x6C_ElecMechIlPresent_WIDTH                         1
#define DxF0x6C_ElecMechIlPresent_MASK                          0x20000
#define DxF0x6C_NoCmdCplSupport_OFFSET                          18
#define DxF0x6C_NoCmdCplSupport_WIDTH                           1
#define DxF0x6C_NoCmdCplSupport_MASK                            0x40000
#define DxF0x6C_PhysicalSlotNumber_OFFSET                       19
#define DxF0x6C_PhysicalSlotNumber_WIDTH                        13
#define DxF0x6C_PhysicalSlotNumber_MASK                         0xfff80000

/// DxF0x6C
typedef union {
  struct {                                                              ///<
    UINT32                                        AttnButtonPresent:1 ; ///<
    UINT32                                     PwrControllerPresent:1 ; ///<
    UINT32                                         MrlSensorPresent:1 ; ///<
    UINT32                                     AttnIndicatorPresent:1 ; ///<
    UINT32                                      PwrIndicatorPresent:1 ; ///<
    UINT32                                          HotplugSurprise:1 ; ///<
    UINT32                                           HotplugCapable:1 ; ///<
    UINT32                                        SlotPwrLimitValue:8 ; ///<
    UINT32                                        SlotPwrLimitScale:2 ; ///<
    UINT32                                        ElecMechIlPresent:1 ; ///<
    UINT32                                          NoCmdCplSupport:1 ; ///<
    UINT32                                       PhysicalSlotNumber:13; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x6C_STRUCT;

// **** DxF0x70 Register Definition ****
// Address
#define DxF0x70_ADDRESS                                         0x70

// Type
#define DxF0x70_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x70_AttnButtonPressedEn_OFFSET                      0
#define DxF0x70_AttnButtonPressedEn_WIDTH                       1
#define DxF0x70_AttnButtonPressedEn_MASK                        0x1
#define DxF0x70_PwrFaultDetectedEn_OFFSET                       1
#define DxF0x70_PwrFaultDetectedEn_WIDTH                        1
#define DxF0x70_PwrFaultDetectedEn_MASK                         0x2
#define DxF0x70_MrlSensorChangedEn_OFFSET                       2
#define DxF0x70_MrlSensorChangedEn_WIDTH                        1
#define DxF0x70_MrlSensorChangedEn_MASK                         0x4
#define DxF0x70_PresenceDetectChangedEn_OFFSET                  3
#define DxF0x70_PresenceDetectChangedEn_WIDTH                   1
#define DxF0x70_PresenceDetectChangedEn_MASK                    0x8
#define DxF0x70_CmdCplIntrEn_OFFSET                             4
#define DxF0x70_CmdCplIntrEn_WIDTH                              1
#define DxF0x70_CmdCplIntrEn_MASK                               0x10
#define DxF0x70_HotplugIntrEn_OFFSET                            5
#define DxF0x70_HotplugIntrEn_WIDTH                             1
#define DxF0x70_HotplugIntrEn_MASK                              0x20
#define DxF0x70_AttnIndicatorControl_OFFSET                     6
#define DxF0x70_AttnIndicatorControl_WIDTH                      2
#define DxF0x70_AttnIndicatorControl_MASK                       0xc0
#define DxF0x70_PwrIndicatorCntl_OFFSET                         8
#define DxF0x70_PwrIndicatorCntl_WIDTH                          2
#define DxF0x70_PwrIndicatorCntl_MASK                           0x300
#define DxF0x70_PwrControllerCntl_OFFSET                        10
#define DxF0x70_PwrControllerCntl_WIDTH                         1
#define DxF0x70_PwrControllerCntl_MASK                          0x400
#define DxF0x70_ElecMechIlCntl_OFFSET                           11
#define DxF0x70_ElecMechIlCntl_WIDTH                            1
#define DxF0x70_ElecMechIlCntl_MASK                             0x800
#define DxF0x70_DlStateChangedEn_OFFSET                         12
#define DxF0x70_DlStateChangedEn_WIDTH                          1
#define DxF0x70_DlStateChangedEn_MASK                           0x1000
#define DxF0x70_Reserved_15_13_OFFSET                           13
#define DxF0x70_Reserved_15_13_WIDTH                            3
#define DxF0x70_Reserved_15_13_MASK                             0xe000
#define DxF0x70_AttnButtonPressed_OFFSET                        16
#define DxF0x70_AttnButtonPressed_WIDTH                         1
#define DxF0x70_AttnButtonPressed_MASK                          0x10000
#define DxF0x70_PwrFaultDetected_OFFSET                         17
#define DxF0x70_PwrFaultDetected_WIDTH                          1
#define DxF0x70_PwrFaultDetected_MASK                           0x20000
#define DxF0x70_MrlSensorChanged_OFFSET                         18
#define DxF0x70_MrlSensorChanged_WIDTH                          1
#define DxF0x70_MrlSensorChanged_MASK                           0x40000
#define DxF0x70_PresenceDetectChanged_OFFSET                    19
#define DxF0x70_PresenceDetectChanged_WIDTH                     1
#define DxF0x70_PresenceDetectChanged_MASK                      0x80000
#define DxF0x70_CmdCpl_OFFSET                                   20
#define DxF0x70_CmdCpl_WIDTH                                    1
#define DxF0x70_CmdCpl_MASK                                     0x100000
#define DxF0x70_MrlSensorState_OFFSET                           21
#define DxF0x70_MrlSensorState_WIDTH                            1
#define DxF0x70_MrlSensorState_MASK                             0x200000
#define DxF0x70_PresenceDetectState_OFFSET                      22
#define DxF0x70_PresenceDetectState_WIDTH                       1
#define DxF0x70_PresenceDetectState_MASK                        0x400000
#define DxF0x70_ElecMechIlSts_OFFSET                            23
#define DxF0x70_ElecMechIlSts_WIDTH                             1
#define DxF0x70_ElecMechIlSts_MASK                              0x800000
#define DxF0x70_DlStateChanged_OFFSET                           24
#define DxF0x70_DlStateChanged_WIDTH                            1
#define DxF0x70_DlStateChanged_MASK                             0x1000000
#define DxF0x70_Reserved_31_25_OFFSET                           25
#define DxF0x70_Reserved_31_25_WIDTH                            7
#define DxF0x70_Reserved_31_25_MASK                             0xfe000000

/// DxF0x70
typedef union {
  struct {                                                              ///<
    UINT32                                      AttnButtonPressedEn:1 ; ///<
    UINT32                                       PwrFaultDetectedEn:1 ; ///<
    UINT32                                       MrlSensorChangedEn:1 ; ///<
    UINT32                                  PresenceDetectChangedEn:1 ; ///<
    UINT32                                             CmdCplIntrEn:1 ; ///<
    UINT32                                            HotplugIntrEn:1 ; ///<
    UINT32                                     AttnIndicatorControl:2 ; ///<
    UINT32                                         PwrIndicatorCntl:2 ; ///<
    UINT32                                        PwrControllerCntl:1 ; ///<
    UINT32                                           ElecMechIlCntl:1 ; ///<
    UINT32                                         DlStateChangedEn:1 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                        AttnButtonPressed:1 ; ///<
    UINT32                                         PwrFaultDetected:1 ; ///<
    UINT32                                         MrlSensorChanged:1 ; ///<
    UINT32                                    PresenceDetectChanged:1 ; ///<
    UINT32                                                   CmdCpl:1 ; ///<
    UINT32                                           MrlSensorState:1 ; ///<
    UINT32                                      PresenceDetectState:1 ; ///<
    UINT32                                            ElecMechIlSts:1 ; ///<
    UINT32                                           DlStateChanged:1 ; ///<
    UINT32                                           Reserved_31_25:7 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x70_STRUCT;

// **** DxF0x74 Register Definition ****
// Address
#define DxF0x74_ADDRESS                                         0x74

// Type
#define DxF0x74_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x74_SerrOnCorrErrEn_OFFSET                          0
#define DxF0x74_SerrOnCorrErrEn_WIDTH                           1
#define DxF0x74_SerrOnCorrErrEn_MASK                            0x1
#define DxF0x74_SerrOnNonFatalErrEn_OFFSET                      1
#define DxF0x74_SerrOnNonFatalErrEn_WIDTH                       1
#define DxF0x74_SerrOnNonFatalErrEn_MASK                        0x2
#define DxF0x74_SerrOnFatalErrEn_OFFSET                         2
#define DxF0x74_SerrOnFatalErrEn_WIDTH                          1
#define DxF0x74_SerrOnFatalErrEn_MASK                           0x4
#define DxF0x74_PmIntEn_OFFSET                                  3
#define DxF0x74_PmIntEn_WIDTH                                   1
#define DxF0x74_PmIntEn_MASK                                    0x8
#define DxF0x74_CrsSoftVisibilityEn_OFFSET                      4
#define DxF0x74_CrsSoftVisibilityEn_WIDTH                       1
#define DxF0x74_CrsSoftVisibilityEn_MASK                        0x10
#define DxF0x74_Reserved_15_5_OFFSET                            5
#define DxF0x74_Reserved_15_5_WIDTH                             11
#define DxF0x74_Reserved_15_5_MASK                              0xffe0
#define DxF0x74_CrsSoftVisibility_OFFSET                        16
#define DxF0x74_CrsSoftVisibility_WIDTH                         1
#define DxF0x74_CrsSoftVisibility_MASK                          0x10000
#define DxF0x74_Reserved_31_17_OFFSET                           17
#define DxF0x74_Reserved_31_17_WIDTH                            15
#define DxF0x74_Reserved_31_17_MASK                             0xfffe0000

/// DxF0x74
typedef union {
  struct {                                                              ///<
    UINT32                                          SerrOnCorrErrEn:1 ; ///<
    UINT32                                      SerrOnNonFatalErrEn:1 ; ///<
    UINT32                                         SerrOnFatalErrEn:1 ; ///<
    UINT32                                                  PmIntEn:1 ; ///<
    UINT32                                      CrsSoftVisibilityEn:1 ; ///<
    UINT32                                            Reserved_15_5:11; ///<
    UINT32                                        CrsSoftVisibility:1 ; ///<
    UINT32                                           Reserved_31_17:15; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x74_STRUCT;

// **** DxF0x78 Register Definition ****
// Address
#define DxF0x78_ADDRESS                                         0x78

// Type
#define DxF0x78_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x78_PmeRequestorId_OFFSET                           0
#define DxF0x78_PmeRequestorId_WIDTH                            16
#define DxF0x78_PmeRequestorId_MASK                             0xffff
#define DxF0x78_PmeStatus_OFFSET                                16
#define DxF0x78_PmeStatus_WIDTH                                 1
#define DxF0x78_PmeStatus_MASK                                  0x10000
#define DxF0x78_PmePending_OFFSET                               17
#define DxF0x78_PmePending_WIDTH                                1
#define DxF0x78_PmePending_MASK                                 0x20000
#define DxF0x78_Reserved_31_18_OFFSET                           18
#define DxF0x78_Reserved_31_18_WIDTH                            14
#define DxF0x78_Reserved_31_18_MASK                             0xfffc0000

/// DxF0x78
typedef union {
  struct {                                                              ///<
    UINT32                                           PmeRequestorId:16; ///<
    UINT32                                                PmeStatus:1 ; ///<
    UINT32                                               PmePending:1 ; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x78_STRUCT;

// **** DxF0x7C Register Definition ****
// Address
#define DxF0x7C_ADDRESS                                         0x7c

// Type
#define DxF0x7C_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x7C_CplTimeoutRangeSup_OFFSET                       0
#define DxF0x7C_CplTimeoutRangeSup_WIDTH                        4
#define DxF0x7C_CplTimeoutRangeSup_MASK                         0xf
#define DxF0x7C_CplTimeoutDisSup_OFFSET                         4
#define DxF0x7C_CplTimeoutDisSup_WIDTH                          1
#define DxF0x7C_CplTimeoutDisSup_MASK                           0x10
#define DxF0x7C_AriForwardingSupported_OFFSET                   5
#define DxF0x7C_AriForwardingSupported_WIDTH                    1
#define DxF0x7C_AriForwardingSupported_MASK                     0x20
#define DxF0x7C_Reserved_31_6_OFFSET                            6
#define DxF0x7C_Reserved_31_6_WIDTH                             26
#define DxF0x7C_Reserved_31_6_MASK                              0xffffffc0

/// DxF0x7C
typedef union {
  struct {                                                              ///<
    UINT32                                       CplTimeoutRangeSup:4 ; ///<
    UINT32                                         CplTimeoutDisSup:1 ; ///<
    UINT32                                   AriForwardingSupported:1 ; ///<
    UINT32                                            Reserved_31_6:26; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x7C_STRUCT;

// **** DxF0x80 Register Definition ****
// Address
#define DxF0x80_ADDRESS                                         0x80

// Type
#define DxF0x80_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x80_CplTimeoutValue_OFFSET                          0
#define DxF0x80_CplTimeoutValue_WIDTH                           4
#define DxF0x80_CplTimeoutValue_MASK                            0xf
#define DxF0x80_CplTimeoutDis_OFFSET                            4
#define DxF0x80_CplTimeoutDis_WIDTH                             1
#define DxF0x80_CplTimeoutDis_MASK                              0x10
#define DxF0x80_AriForwardingEn_OFFSET                          5
#define DxF0x80_AriForwardingEn_WIDTH                           1
#define DxF0x80_AriForwardingEn_MASK                            0x20
#define DxF0x80_Reserved_31_6_OFFSET                            6
#define DxF0x80_Reserved_31_6_WIDTH                             26
#define DxF0x80_Reserved_31_6_MASK                              0xffffffc0

/// DxF0x80
typedef union {
  struct {                                                              ///<
    UINT32                                          CplTimeoutValue:4 ; ///<
    UINT32                                            CplTimeoutDis:1 ; ///<
    UINT32                                          AriForwardingEn:1 ; ///<
    UINT32                                            Reserved_31_6:26; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x80_STRUCT;

// **** DxF0x84 Register Definition ****
// Address
#define DxF0x84_ADDRESS                                         0x84

// Type
#define DxF0x84_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x84_Reserved_31_0_OFFSET                            0
#define DxF0x84_Reserved_31_0_WIDTH                             32
#define DxF0x84_Reserved_31_0_MASK                              0xffffffff

/// DxF0x84
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_31_0:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x84_STRUCT;

// **** DxF0x88 Register Definition ****
// Address
#define DxF0x88_ADDRESS                                         0x88

// Type
#define DxF0x88_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x88_TargetLinkSpeed_OFFSET                          0
#define DxF0x88_TargetLinkSpeed_WIDTH                           4
#define DxF0x88_TargetLinkSpeed_MASK                            0xf
#define DxF0x88_EnterCompliance_OFFSET                          4
#define DxF0x88_EnterCompliance_WIDTH                           1
#define DxF0x88_EnterCompliance_MASK                            0x10
#define DxF0x88_HwAutonomousSpeedDisable_OFFSET                 5
#define DxF0x88_HwAutonomousSpeedDisable_WIDTH                  1
#define DxF0x88_HwAutonomousSpeedDisable_MASK                   0x20
#define DxF0x88_SelectableDeemphasis_OFFSET                     6
#define DxF0x88_SelectableDeemphasis_WIDTH                      1
#define DxF0x88_SelectableDeemphasis_MASK                       0x40
#define DxF0x88_XmitMargin_OFFSET                               7
#define DxF0x88_XmitMargin_WIDTH                                3
#define DxF0x88_XmitMargin_MASK                                 0x380
#define DxF0x88_EnterModCompliance_OFFSET                       10
#define DxF0x88_EnterModCompliance_WIDTH                        1
#define DxF0x88_EnterModCompliance_MASK                         0x400
#define DxF0x88_ComplianceSOS_OFFSET                            11
#define DxF0x88_ComplianceSOS_WIDTH                             1
#define DxF0x88_ComplianceSOS_MASK                              0x800
#define DxF0x88_ComplianceDeemphasis_OFFSET                     12
#define DxF0x88_ComplianceDeemphasis_WIDTH                      1
#define DxF0x88_ComplianceDeemphasis_MASK                       0x1000
#define DxF0x88_Reserved_15_13_OFFSET                           13
#define DxF0x88_Reserved_15_13_WIDTH                            3
#define DxF0x88_Reserved_15_13_MASK                             0xe000
#define DxF0x88_CurDeemphasisLevel_OFFSET                       16
#define DxF0x88_CurDeemphasisLevel_WIDTH                        1
#define DxF0x88_CurDeemphasisLevel_MASK                         0x10000
#define DxF0x88_Reserved_31_17_OFFSET                           17
#define DxF0x88_Reserved_31_17_WIDTH                            15
#define DxF0x88_Reserved_31_17_MASK                             0xfffe0000

/// DxF0x88
typedef union {
  struct {                                                              ///<
    UINT32                                          TargetLinkSpeed:4 ; ///<
    UINT32                                          EnterCompliance:1 ; ///<
    UINT32                                 HwAutonomousSpeedDisable:1 ; ///<
    UINT32                                     SelectableDeemphasis:1 ; ///<
    UINT32                                               XmitMargin:3 ; ///<
    UINT32                                       EnterModCompliance:1 ; ///<
    UINT32                                            ComplianceSOS:1 ; ///<
    UINT32                                     ComplianceDeemphasis:1 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                       CurDeemphasisLevel:1 ; ///<
    UINT32                                           Reserved_31_17:15; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x88_STRUCT;

// **** DxF0x8C Register Definition ****
// Address
#define DxF0x8C_ADDRESS                                         0x8c

// Type
#define DxF0x8C_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x8C_Reserved_31_0_OFFSET                            0
#define DxF0x8C_Reserved_31_0_WIDTH                             32
#define DxF0x8C_Reserved_31_0_MASK                              0xffffffff

/// DxF0x8C
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_31_0:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x8C_STRUCT;

// **** DxF0x90 Register Definition ****
// Address
#define DxF0x90_ADDRESS                                         0x90

// Type
#define DxF0x90_TYPE                                            TYPE_D4F0
// Field Data
#define DxF0x90_Reserved_31_0_OFFSET                            0
#define DxF0x90_Reserved_31_0_WIDTH                             32
#define DxF0x90_Reserved_31_0_MASK                              0xffffffff

/// DxF0x90
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_31_0:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x90_STRUCT;

// **** DxF0x128 Register Definition ****
// Address
#define DxF0x128_ADDRESS                                        0x128

// Type
#define DxF0x128_TYPE                                           TYPE_D4F0
// Field Data
#define DxF0x128_Reserved_15_0_OFFSET                           0
#define DxF0x128_Reserved_15_0_WIDTH                            16
#define DxF0x128_Reserved_15_0_MASK                             0xffff
#define DxF0x128_PortArbTableStatus_OFFSET                      16
#define DxF0x128_PortArbTableStatus_WIDTH                       1
#define DxF0x128_PortArbTableStatus_MASK                        0x10000
#define DxF0x128_VcNegotiationPending_OFFSET                    17
#define DxF0x128_VcNegotiationPending_WIDTH                     1
#define DxF0x128_VcNegotiationPending_MASK                      0x20000
#define DxF0x128_Reserved_31_18_OFFSET                          18
#define DxF0x128_Reserved_31_18_WIDTH                           14
#define DxF0x128_Reserved_31_18_MASK                            0xfffc0000

/// DxF0x128
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_15_0:16; ///<
    UINT32                                       PortArbTableStatus:1 ; ///<
    UINT32                                     VcNegotiationPending:1 ; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0x128_STRUCT;

// **** D0F0x64_x00 Register Definition ****
// Address
#define D0F0x64_x00_ADDRESS                                     0x0

// Type
#define D0F0x64_x00_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x00_Reserved_5_0_OFFSET                         0
#define D0F0x64_x00_Reserved_5_0_WIDTH                          6
#define D0F0x64_x00_Reserved_5_0_MASK                           0x3f
#define D0F0x64_x00_NbFchCfgEn_OFFSET                           6
#define D0F0x64_x00_NbFchCfgEn_WIDTH                            1
#define D0F0x64_x00_NbFchCfgEn_MASK                             0x40
#define D0F0x64_x00_HwInitWrLock_OFFSET                         7
#define D0F0x64_x00_HwInitWrLock_WIDTH                          1
#define D0F0x64_x00_HwInitWrLock_MASK                           0x80
#define D0F0x64_x00_Reserved_31_8_OFFSET                        8
#define D0F0x64_x00_Reserved_31_8_WIDTH                         24
#define D0F0x64_x00_Reserved_31_8_MASK                          0xffffff00

/// D0F0x64_x00
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_5_0:6 ; ///<
    UINT32                                               NbFchCfgEn:1 ; ///<
    UINT32                                             HwInitWrLock:1 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x00_STRUCT;

// **** D0F0x64_x0B Register Definition ****
// Address
#define D0F0x64_x0B_ADDRESS                                     0xb

// Type
#define D0F0x64_x0B_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x0B_Reserved_19_0_OFFSET                        0
#define D0F0x64_x0B_Reserved_19_0_WIDTH                         20
#define D0F0x64_x0B_Reserved_19_0_MASK                          0xfffff
#define D0F0x64_x0B_SetPowEn_OFFSET                             20
#define D0F0x64_x0B_SetPowEn_WIDTH                              1
#define D0F0x64_x0B_SetPowEn_MASK                               0x100000
#define D0F0x64_x0B_IocFchSetPowEn_OFFSET                       21
#define D0F0x64_x0B_IocFchSetPowEn_WIDTH                        1
#define D0F0x64_x0B_IocFchSetPowEn_MASK                         0x200000
#define D0F0x64_x0B_Reserved_22_22_OFFSET                       22
#define D0F0x64_x0B_Reserved_22_22_WIDTH                        1
#define D0F0x64_x0B_Reserved_22_22_MASK                         0x400000
#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_OFFSET                23
#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_WIDTH                 1
#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_MASK                  0x800000
#define D0F0x64_x0B_Reserved_31_24_OFFSET                       24
#define D0F0x64_x0B_Reserved_31_24_WIDTH                        8
#define D0F0x64_x0B_Reserved_31_24_MASK                         0xff000000

/// D0F0x64_x0B
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_19_0:20; ///<
    UINT32                                                 SetPowEn:1 ; ///<
    UINT32                                           IocFchSetPowEn:1 ; ///<
    UINT32                                           Reserved_22_22:1 ; ///<
    UINT32                                    IocFchSetPmeTurnOffEn:1 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x0B_STRUCT;

// **** D0F0x64_x0C Register Definition ****
// Address
#define D0F0x64_x0C_ADDRESS                                     0xc

// Type
#define D0F0x64_x0C_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x0C_Reserved_1_0_OFFSET                         0
#define D0F0x64_x0C_Reserved_1_0_WIDTH                          2
#define D0F0x64_x0C_Reserved_1_0_MASK                           0x3
#define D0F0x64_x0C_Dev2BridgeDis_OFFSET                        2
#define D0F0x64_x0C_Dev2BridgeDis_WIDTH                         1
#define D0F0x64_x0C_Dev2BridgeDis_MASK                          0x4
#define D0F0x64_x0C_Dev3BridgeDis_OFFSET                        3
#define D0F0x64_x0C_Dev3BridgeDis_WIDTH                         1
#define D0F0x64_x0C_Dev3BridgeDis_MASK                          0x8
#define D0F0x64_x0C_Dev4BridgeDis_OFFSET                        4
#define D0F0x64_x0C_Dev4BridgeDis_WIDTH                         1
#define D0F0x64_x0C_Dev4BridgeDis_MASK                          0x10
#define D0F0x64_x0C_Dev5BridgeDis_OFFSET                        5
#define D0F0x64_x0C_Dev5BridgeDis_WIDTH                         1
#define D0F0x64_x0C_Dev5BridgeDis_MASK                          0x20
#define D0F0x64_x0C_Dev6BridgeDis_OFFSET                        6
#define D0F0x64_x0C_Dev6BridgeDis_WIDTH                         1
#define D0F0x64_x0C_Dev6BridgeDis_MASK                          0x40
#define D0F0x64_x0C_Dev7BridgeDis_OFFSET                        7
#define D0F0x64_x0C_Dev7BridgeDis_WIDTH                         1
#define D0F0x64_x0C_Dev7BridgeDis_MASK                          0x80
#define D0F0x64_x0C_Reserved_31_8_OFFSET                        8
#define D0F0x64_x0C_Reserved_31_8_WIDTH                         24
#define D0F0x64_x0C_Reserved_31_8_MASK                          0xffffff00

/// D0F0x64_x0C
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_1_0:2 ; ///<
    UINT32                                            Dev2BridgeDis:1 ; ///<
    UINT32                                            Dev3BridgeDis:1 ; ///<
    UINT32                                            Dev4BridgeDis:1 ; ///<
    UINT32                                            Dev5BridgeDis:1 ; ///<
    UINT32                                            Dev6BridgeDis:1 ; ///<
    UINT32                                            Dev7BridgeDis:1 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x0C_STRUCT;

// **** D0F0x64_x0D Register Definition ****
// Address
#define D0F0x64_x0D_ADDRESS                                     0xd

// Type
#define D0F0x64_x0D_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x0D_PciDev0Fn2RegEn_OFFSET                      0
#define D0F0x64_x0D_PciDev0Fn2RegEn_WIDTH                       1
#define D0F0x64_x0D_PciDev0Fn2RegEn_MASK                        0x1
#define D0F0x64_x0D_Reserved_31_1_OFFSET                        1
#define D0F0x64_x0D_Reserved_31_1_WIDTH                         31
#define D0F0x64_x0D_Reserved_31_1_MASK                          0xfffffffe

/// D0F0x64_x0D
typedef union {
  struct {                                                              ///<
    UINT32                                          PciDev0Fn2RegEn:1 ; ///<
    UINT32                                            Reserved_31_1:31; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x0D_STRUCT;

// **** D0F0x64_x16 Register Definition ****
// Address
#define D0F0x64_x16_ADDRESS                                     0x16

// Type
#define D0F0x64_x16_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x16_AerUrMsgEn_OFFSET                           0
#define D0F0x64_x16_AerUrMsgEn_WIDTH                            1
#define D0F0x64_x16_AerUrMsgEn_MASK                             0x1
#define D0F0x64_x16_Reserved_31_1_OFFSET                        1
#define D0F0x64_x16_Reserved_31_1_WIDTH                         31
#define D0F0x64_x16_Reserved_31_1_MASK                          0xfffffffe

/// D0F0x64_x16
typedef union {
  struct {                                                              ///<
    UINT32                                               AerUrMsgEn:1 ; ///<
    UINT32                                            Reserved_31_1:31; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x16_STRUCT;

// **** D0F0x64_x19 Register Definition ****
// Address
#define D0F0x64_x19_ADDRESS                                     0x19

// Type
#define D0F0x64_x19_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x19_TomEn_OFFSET                                0
#define D0F0x64_x19_TomEn_WIDTH                                 1
#define D0F0x64_x19_TomEn_MASK                                  0x1
#define D0F0x64_x19_Reserved_22_1_OFFSET                        1
#define D0F0x64_x19_Reserved_22_1_WIDTH                         22
#define D0F0x64_x19_Reserved_22_1_MASK                          0x7ffffe
#define D0F0x64_x19_Tom2_31_23__OFFSET                          23
#define D0F0x64_x19_Tom2_31_23__WIDTH                           9
#define D0F0x64_x19_Tom2_31_23__MASK                            0xff800000

/// D0F0x64_x19
typedef union {
  struct {                                                              ///<
    UINT32                                                    TomEn:1 ; ///<
    UINT32                                            Reserved_22_1:22; ///<
    UINT32                                              Tom2_31_23_:9 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x19_STRUCT;

// **** D0F0x64_x1A Register Definition ****
// Address
#define D0F0x64_x1A_ADDRESS                                     0x1a

// Type
#define D0F0x64_x1A_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x1A_Tom2_39_32__OFFSET                          0
#define D0F0x64_x1A_Tom2_39_32__WIDTH                           8
#define D0F0x64_x1A_Tom2_39_32__MASK                            0xff
#define D0F0x64_x1A_Reserved_31_8_OFFSET                        8
#define D0F0x64_x1A_Reserved_31_8_WIDTH                         24
#define D0F0x64_x1A_Reserved_31_8_MASK                          0xffffff00

/// D0F0x64_x1A
typedef union {
  struct {                                                              ///<
    UINT32                                              Tom2_39_32_:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x1A_STRUCT;

// **** D0F0x64_x1C Register Definition ****
// Address
#define D0F0x64_x1C_ADDRESS                                     0x1c

// Type
#define D0F0x64_x1C_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x1C_WriteDis_OFFSET                             0
#define D0F0x64_x1C_WriteDis_WIDTH                              1
#define D0F0x64_x1C_WriteDis_MASK                               0x1
#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET              1
#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH               1
#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK                0x2
#define D0F0x64_x1C_F064BarEn_OFFSET                            2
#define D0F0x64_x1C_F064BarEn_WIDTH                             1
#define D0F0x64_x1C_F064BarEn_MASK                              0x4
#define D0F0x64_x1C_MemApSize_OFFSET                            3
#define D0F0x64_x1C_MemApSize_WIDTH                             3
#define D0F0x64_x1C_MemApSize_MASK                              0x38
#define D0F0x64_x1C_RegApSize_OFFSET                            6
#define D0F0x64_x1C_RegApSize_WIDTH                             1
#define D0F0x64_x1C_RegApSize_MASK                              0x40
#define D0F0x64_x1C_Reserved_7_7_OFFSET                         7
#define D0F0x64_x1C_Reserved_7_7_WIDTH                          1
#define D0F0x64_x1C_Reserved_7_7_MASK                           0x80
#define D0F0x64_x1C_AudioEn_OFFSET                              8
#define D0F0x64_x1C_AudioEn_WIDTH                               1
#define D0F0x64_x1C_AudioEn_MASK                                0x100
#define D0F0x64_x1C_MsiDis_OFFSET                               9
#define D0F0x64_x1C_MsiDis_WIDTH                                1
#define D0F0x64_x1C_MsiDis_MASK                                 0x200
#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_OFFSET           10
#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_WIDTH            1
#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_MASK             0x400
#define D0F0x64_x1C_Audio64BarEn_OFFSET                         11
#define D0F0x64_x1C_Audio64BarEn_WIDTH                          1
#define D0F0x64_x1C_Audio64BarEn_MASK                           0x800
#define D0F0x64_x1C_Reserved_15_12_OFFSET                       12
#define D0F0x64_x1C_Reserved_15_12_WIDTH                        4
#define D0F0x64_x1C_Reserved_15_12_MASK                         0xf000
#define D0F0x64_x1C_IoBarDis_OFFSET                             16
#define D0F0x64_x1C_IoBarDis_WIDTH                              1
#define D0F0x64_x1C_IoBarDis_MASK                               0x10000
#define D0F0x64_x1C_F0En_OFFSET                                 17
#define D0F0x64_x1C_F0En_WIDTH                                  1
#define D0F0x64_x1C_F0En_MASK                                   0x20000
#define D0F0x64_x1C_Reserved_22_18_OFFSET                       18
#define D0F0x64_x1C_Reserved_22_18_WIDTH                        5
#define D0F0x64_x1C_Reserved_22_18_MASK                         0x7c0000
#define D0F0x64_x1C_RcieEn_OFFSET                               23
#define D0F0x64_x1C_RcieEn_WIDTH                                1
#define D0F0x64_x1C_RcieEn_MASK                                 0x800000
#define D0F0x64_x1C_Reserved_31_24_OFFSET                       24
#define D0F0x64_x1C_Reserved_31_24_WIDTH                        8
#define D0F0x64_x1C_Reserved_31_24_MASK                         0xff000000

/// D0F0x64_x1C
typedef union {
  struct {                                                              ///<
    UINT32                                                 WriteDis:1 ; ///<
    UINT32                                  F0NonlegacyDeviceTypeEn:1 ; ///<
    UINT32                                                F064BarEn:1 ; ///<
    UINT32                                                MemApSize:3 ; ///<
    UINT32                                                RegApSize:1 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                                  AudioEn:1 ; ///<
    UINT32                                                   MsiDis:1 ; ///<
    UINT32                               AudioNonlegacyDeviceTypeEn:1 ; ///<
    UINT32                                             Audio64BarEn:1 ; ///<
    UINT32                                           Reserved_15_12:4 ; ///<
    UINT32                                                 IoBarDis:1 ; ///<
    UINT32                                                     F0En:1 ; ///<
    UINT32                                           Reserved_22_18:5 ; ///<
    UINT32                                                   RcieEn:1 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x1C_STRUCT;

// **** D0F0x64_x1D Register Definition ****
// Address
#define D0F0x64_x1D_ADDRESS                                     0x1d

// Type
#define D0F0x64_x1D_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x1D_IntGfxAsPcieEn_OFFSET                       0
#define D0F0x64_x1D_IntGfxAsPcieEn_WIDTH                        1
#define D0F0x64_x1D_IntGfxAsPcieEn_MASK                         0x1
#define D0F0x64_x1D_VgaEn_OFFSET                                1
#define D0F0x64_x1D_VgaEn_WIDTH                                 1
#define D0F0x64_x1D_VgaEn_MASK                                  0x2
#define D0F0x64_x1D_Reserved_2_2_OFFSET                         2
#define D0F0x64_x1D_Reserved_2_2_WIDTH                          1
#define D0F0x64_x1D_Reserved_2_2_MASK                           0x4
#define D0F0x64_x1D_Vga16En_OFFSET                              3
#define D0F0x64_x1D_Vga16En_WIDTH                               1
#define D0F0x64_x1D_Vga16En_MASK                                0x8
#define D0F0x64_x1D_Reserved_31_4_OFFSET                        4
#define D0F0x64_x1D_Reserved_31_4_WIDTH                         28
#define D0F0x64_x1D_Reserved_31_4_MASK                          0xfffffff0

/// D0F0x64_x1D
typedef union {
  struct {                                                              ///<
    UINT32                                           IntGfxAsPcieEn:1 ; ///<
    UINT32                                                    VgaEn:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                                  Vga16En:1 ; ///<
    UINT32                                            Reserved_31_4:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x1D_STRUCT;

// **** D0F0x64_x20 Register Definition ****
// Address
#define D0F0x64_x20_ADDRESS                                     0x20

// Type
#define D0F0x64_x20_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x20_ProgDevMapEn_OFFSET                         0
#define D0F0x64_x20_ProgDevMapEn_WIDTH                          1
#define D0F0x64_x20_ProgDevMapEn_MASK                           0x1
#define D0F0x64_x20_IocPcieDevRemapDis_OFFSET                   1
#define D0F0x64_x20_IocPcieDevRemapDis_WIDTH                    1
#define D0F0x64_x20_IocPcieDevRemapDis_MASK                     0x2
#define D0F0x64_x20_Reserved_3_2_OFFSET                         2
#define D0F0x64_x20_Reserved_3_2_WIDTH                          2
#define D0F0x64_x20_Reserved_3_2_MASK                           0xc
#define D0F0x64_x20_GppPortBDevmap_OFFSET                       4
#define D0F0x64_x20_GppPortBDevmap_WIDTH                        4
#define D0F0x64_x20_GppPortBDevmap_MASK                         0xf0
#define D0F0x64_x20_GppPortCDevmap_OFFSET                       8
#define D0F0x64_x20_GppPortCDevmap_WIDTH                        4
#define D0F0x64_x20_GppPortCDevmap_MASK                         0xf00
#define D0F0x64_x20_GppPortDDevmap_OFFSET                       12
#define D0F0x64_x20_GppPortDDevmap_WIDTH                        4
#define D0F0x64_x20_GppPortDDevmap_MASK                         0xf000
#define D0F0x64_x20_GppPortEDevmap_OFFSET                       16
#define D0F0x64_x20_GppPortEDevmap_WIDTH                        4
#define D0F0x64_x20_GppPortEDevmap_MASK                         0xf0000
#define D0F0x64_x20_Reserved_31_20_OFFSET                       20
#define D0F0x64_x20_Reserved_31_20_WIDTH                        12
#define D0F0x64_x20_Reserved_31_20_MASK                         0xfff00000

/// D0F0x64_x20
typedef union {
  struct {                                                              ///<
    UINT32                                             ProgDevMapEn:1 ; ///<
    UINT32                                       IocPcieDevRemapDis:1 ; ///<
    UINT32                                             Reserved_3_2:2 ; ///<
    UINT32                                           GppPortBDevmap:4 ; ///<
    UINT32                                           GppPortCDevmap:4 ; ///<
    UINT32                                           GppPortDDevmap:4 ; ///<
    UINT32                                           GppPortEDevmap:4 ; ///<
    UINT32                                           Reserved_31_20:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x20_STRUCT;

// **** D0F0x64_x21 Register Definition ****
// Address
#define D0F0x64_x21_ADDRESS                                     0x21

// Type
#define D0F0x64_x21_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x21_Reserved_11_0_OFFSET                        0
#define D0F0x64_x21_Reserved_11_0_WIDTH                         12
#define D0F0x64_x21_Reserved_11_0_MASK                          0xfff
#define D0F0x64_x21_GfxPortADevmap_OFFSET                       12
#define D0F0x64_x21_GfxPortADevmap_WIDTH                        4
#define D0F0x64_x21_GfxPortADevmap_MASK                         0xf000
#define D0F0x64_x21_GfxPortBDevmap_OFFSET                       16
#define D0F0x64_x21_GfxPortBDevmap_WIDTH                        4
#define D0F0x64_x21_GfxPortBDevmap_MASK                         0xf0000
#define D0F0x64_x21_Reserved_31_20_OFFSET                       20
#define D0F0x64_x21_Reserved_31_20_WIDTH                        12
#define D0F0x64_x21_Reserved_31_20_MASK                         0xfff00000

/// D0F0x64_x21
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_11_0:12; ///<
    UINT32                                           GfxPortADevmap:4 ; ///<
    UINT32                                           GfxPortBDevmap:4 ; ///<
    UINT32                                           Reserved_31_20:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x21_STRUCT;

// **** D0F0x64_x22 Register Definition ****
// Address
#define D0F0x64_x22_ADDRESS                                     0x22

// Type
#define D0F0x64_x22_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x22_Reserved_25_0_OFFSET                        0
#define D0F0x64_x22_Reserved_25_0_WIDTH                         26
#define D0F0x64_x22_Reserved_25_0_MASK                          0x3ffffff
#define D0F0x64_x22_SoftOverrideClk4_OFFSET                     26
#define D0F0x64_x22_SoftOverrideClk4_WIDTH                      1
#define D0F0x64_x22_SoftOverrideClk4_MASK                       0x4000000
#define D0F0x64_x22_SoftOverrideClk3_OFFSET                     27
#define D0F0x64_x22_SoftOverrideClk3_WIDTH                      1
#define D0F0x64_x22_SoftOverrideClk3_MASK                       0x8000000
#define D0F0x64_x22_SoftOverrideClk2_OFFSET                     28
#define D0F0x64_x22_SoftOverrideClk2_WIDTH                      1
#define D0F0x64_x22_SoftOverrideClk2_MASK                       0x10000000
#define D0F0x64_x22_SoftOverrideClk1_OFFSET                     29
#define D0F0x64_x22_SoftOverrideClk1_WIDTH                      1
#define D0F0x64_x22_SoftOverrideClk1_MASK                       0x20000000
#define D0F0x64_x22_SoftOverrideClk0_OFFSET                     30
#define D0F0x64_x22_SoftOverrideClk0_WIDTH                      1
#define D0F0x64_x22_SoftOverrideClk0_MASK                       0x40000000
#define D0F0x64_x22_Reserved_31_31_OFFSET                       31
#define D0F0x64_x22_Reserved_31_31_WIDTH                        1
#define D0F0x64_x22_Reserved_31_31_MASK                         0x80000000

/// D0F0x64_x22
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_25_0:26; ///<
    UINT32                                         SoftOverrideClk4:1 ; ///<
    UINT32                                         SoftOverrideClk3:1 ; ///<
    UINT32                                         SoftOverrideClk2:1 ; ///<
    UINT32                                         SoftOverrideClk1:1 ; ///<
    UINT32                                         SoftOverrideClk0:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x22_STRUCT;

// **** D0F0x64_x23 Register Definition ****
// Address
#define D0F0x64_x23_ADDRESS                                     0x23

// Type
#define D0F0x64_x23_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x23_Reserved_25_0_OFFSET                        0
#define D0F0x64_x23_Reserved_25_0_WIDTH                         26
#define D0F0x64_x23_Reserved_25_0_MASK                          0x3ffffff
#define D0F0x64_x23_SoftOverrideClk4_OFFSET                     26
#define D0F0x64_x23_SoftOverrideClk4_WIDTH                      1
#define D0F0x64_x23_SoftOverrideClk4_MASK                       0x4000000
#define D0F0x64_x23_SoftOverrideClk3_OFFSET                     27
#define D0F0x64_x23_SoftOverrideClk3_WIDTH                      1
#define D0F0x64_x23_SoftOverrideClk3_MASK                       0x8000000
#define D0F0x64_x23_SoftOverrideClk2_OFFSET                     28
#define D0F0x64_x23_SoftOverrideClk2_WIDTH                      1
#define D0F0x64_x23_SoftOverrideClk2_MASK                       0x10000000
#define D0F0x64_x23_SoftOverrideClk1_OFFSET                     29
#define D0F0x64_x23_SoftOverrideClk1_WIDTH                      1
#define D0F0x64_x23_SoftOverrideClk1_MASK                       0x20000000
#define D0F0x64_x23_SoftOverrideClk0_OFFSET                     30
#define D0F0x64_x23_SoftOverrideClk0_WIDTH                      1
#define D0F0x64_x23_SoftOverrideClk0_MASK                       0x40000000
#define D0F0x64_x23_Reserved_31_31_OFFSET                       31
#define D0F0x64_x23_Reserved_31_31_WIDTH                        1
#define D0F0x64_x23_Reserved_31_31_MASK                         0x80000000

/// D0F0x64_x23
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_25_0:26; ///<
    UINT32                                         SoftOverrideClk4:1 ; ///<
    UINT32                                         SoftOverrideClk3:1 ; ///<
    UINT32                                         SoftOverrideClk2:1 ; ///<
    UINT32                                         SoftOverrideClk1:1 ; ///<
    UINT32                                         SoftOverrideClk0:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x23_STRUCT;


// **** D0F0x64_x46 Register Definition ****
// Address
#define D0F0x64_x46_ADDRESS                                     0x46

// Type
#define D0F0x64_x46_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x46_Reserved_0_0_OFFSET                         0
#define D0F0x64_x46_Reserved_0_0_WIDTH                          1
#define D0F0x64_x46_Reserved_0_0_MASK                           0x1
#define D0F0x64_x46_Reserved_15_3_OFFSET                        3
#define D0F0x64_x46_Reserved_15_3_WIDTH                         13
#define D0F0x64_x46_Reserved_15_3_MASK                          0xfff8
#define D0F0x64_x46_Msi64bitEn_OFFSET                           16
#define D0F0x64_x46_Msi64bitEn_WIDTH                            1
#define D0F0x64_x46_Msi64bitEn_MASK                             0x10000
#define D0F0x64_x46_Reserved_31_17_OFFSET                       17
#define D0F0x64_x46_Reserved_31_17_WIDTH                        15
#define D0F0x64_x46_Reserved_31_17_MASK                         0xfffe0000

/// D0F0x64_x46
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                  :2 ; ///<
    UINT32                                            Reserved_15_3:13; ///<
    UINT32                                               Msi64bitEn:1 ; ///<
    UINT32                                           Reserved_31_17:15; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x46_STRUCT;


// **** D0F0x64_x53 Register Definition ****
// Address
#define D0F0x64_x53_ADDRESS                                     0x53

// Type
#define D0F0x64_x53_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x53_Reserved_19_0_OFFSET                        0
#define D0F0x64_x53_Reserved_19_0_WIDTH                         20
#define D0F0x64_x53_Reserved_19_0_MASK                          0xfffff
#define D0F0x64_x53_SetPowEn_OFFSET                             20
#define D0F0x64_x53_SetPowEn_WIDTH                              1
#define D0F0x64_x53_SetPowEn_MASK                               0x100000
#define D0F0x64_x53_Reserved_31_21_OFFSET                       21
#define D0F0x64_x53_Reserved_31_21_WIDTH                        11
#define D0F0x64_x53_Reserved_31_21_MASK                         0xffe00000

/// D0F0x64_x53
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_19_0:20; ///<
    UINT32                                                 SetPowEn:1 ; ///<
    UINT32                                           Reserved_31_21:11; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x53_STRUCT;

// **** D0F0x64_x55 Register Definition ****
// Address
#define D0F0x64_x55_ADDRESS                                     0x55

// Type
#define D0F0x64_x55_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x55_Reserved_19_0_OFFSET                        0
#define D0F0x64_x55_Reserved_19_0_WIDTH                         20
#define D0F0x64_x55_Reserved_19_0_MASK                          0xfffff
#define D0F0x64_x55_SetPowEn_OFFSET                             20
#define D0F0x64_x55_SetPowEn_WIDTH                              1
#define D0F0x64_x55_SetPowEn_MASK                               0x100000
#define D0F0x64_x55_Reserved_31_21_OFFSET                       21
#define D0F0x64_x55_Reserved_31_21_WIDTH                        11
#define D0F0x64_x55_Reserved_31_21_MASK                         0xffe00000

/// D0F0x64_x55
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_19_0:20; ///<
    UINT32                                                 SetPowEn:1 ; ///<
    UINT32                                           Reserved_31_21:11; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x55_STRUCT;

// **** D0F0x64_x57 Register Definition ****
// Address
#define D0F0x64_x57_ADDRESS                                     0x57

// Type
#define D0F0x64_x57_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x57_Reserved_19_0_OFFSET                        0
#define D0F0x64_x57_Reserved_19_0_WIDTH                         20
#define D0F0x64_x57_Reserved_19_0_MASK                          0xfffff
#define D0F0x64_x57_SetPowEn_OFFSET                             20
#define D0F0x64_x57_SetPowEn_WIDTH                              1
#define D0F0x64_x57_SetPowEn_MASK                               0x100000
#define D0F0x64_x57_Reserved_31_21_OFFSET                       21
#define D0F0x64_x57_Reserved_31_21_WIDTH                        11
#define D0F0x64_x57_Reserved_31_21_MASK                         0xffe00000

/// D0F0x64_x57
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_19_0:20; ///<
    UINT32                                                 SetPowEn:1 ; ///<
    UINT32                                           Reserved_31_21:11; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x57_STRUCT;

// **** D0F0x64_x59 Register Definition ****
// Address
#define D0F0x64_x59_ADDRESS                                     0x59

// Type
#define D0F0x64_x59_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x59_Reserved_19_0_OFFSET                        0
#define D0F0x64_x59_Reserved_19_0_WIDTH                         20
#define D0F0x64_x59_Reserved_19_0_MASK                          0xfffff
#define D0F0x64_x59_SetPowEn_OFFSET                             20
#define D0F0x64_x59_SetPowEn_WIDTH                              1
#define D0F0x64_x59_SetPowEn_MASK                               0x100000
#define D0F0x64_x59_Reserved_31_21_OFFSET                       21
#define D0F0x64_x59_Reserved_31_21_WIDTH                        11
#define D0F0x64_x59_Reserved_31_21_MASK                         0xffe00000

/// D0F0x64_x59
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_19_0:20; ///<
    UINT32                                                 SetPowEn:1 ; ///<
    UINT32                                           Reserved_31_21:11; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x59_STRUCT;

// **** D0F0x64_x5B Register Definition ****
// Address
#define D0F0x64_x5B_ADDRESS                                     0x5b

// Type
#define D0F0x64_x5B_TYPE                                        TYPE_D0F0x64
// Field Data
#define D0F0x64_x5B_Reserved_19_0_OFFSET                        0
#define D0F0x64_x5B_Reserved_19_0_WIDTH                         20
#define D0F0x64_x5B_Reserved_19_0_MASK                          0xfffff
#define D0F0x64_x5B_SetPowEn_OFFSET                             20
#define D0F0x64_x5B_SetPowEn_WIDTH                              1
#define D0F0x64_x5B_SetPowEn_MASK                               0x100000
#define D0F0x64_x5B_Reserved_31_21_OFFSET                       21
#define D0F0x64_x5B_Reserved_31_21_WIDTH                        11
#define D0F0x64_x5B_Reserved_31_21_MASK                         0xffe00000

/// D0F0x64_x5B
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_19_0:20; ///<
    UINT32                                                 SetPowEn:1 ; ///<
    UINT32                                           Reserved_31_21:11; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x64_x5B_STRUCT;

// **** D0F0x98_x06 Register Definition ****
// Address
#define D0F0x98_x06_ADDRESS                                     0x6

// Type
#define D0F0x98_x06_TYPE                                        TYPE_D0F0x98
// Field Data
#define D0F0x98_x06_Reserved_25_0_OFFSET                        0
#define D0F0x98_x06_Reserved_25_0_WIDTH                         26
#define D0F0x98_x06_Reserved_25_0_MASK                          0x3ffffff
#define D0F0x98_x06_UmiNpMemWrEn_OFFSET                         26
#define D0F0x98_x06_UmiNpMemWrEn_WIDTH                          1
#define D0F0x98_x06_UmiNpMemWrEn_MASK                           0x4000000
#define D0F0x98_x06_Reserved_31_27_OFFSET                       27
#define D0F0x98_x06_Reserved_31_27_WIDTH                        5
#define D0F0x98_x06_Reserved_31_27_MASK                         0xf8000000

/// D0F0x98_x06
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_25_0:26; ///<
    UINT32                                             UmiNpMemWrEn:1 ; ///<
    UINT32                                           Reserved_31_27:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x98_x06_STRUCT;

// **** D0F0x98_x07 Register Definition ****
// Address
#define D0F0x98_x07_ADDRESS                                     0x7

// Type
#define D0F0x98_x07_TYPE                                        TYPE_D0F0x98
// Field Data
#define D0F0x98_x07_IocBwOptEn_OFFSET                           0
#define D0F0x98_x07_IocBwOptEn_WIDTH                            1
#define D0F0x98_x07_IocBwOptEn_MASK                             0x1
#define D0F0x98_x07_Reserved_3_1_OFFSET                         1
#define D0F0x98_x07_Reserved_3_1_WIDTH                          3
#define D0F0x98_x07_Reserved_3_1_MASK                           0xe
#define D0F0x98_x07_IommuBwOptEn_OFFSET                         4
#define D0F0x98_x07_IommuBwOptEn_WIDTH                          1
#define D0F0x98_x07_IommuBwOptEn_MASK                           0x10
#define D0F0x98_x07_Reserved_5_5_OFFSET                         5
#define D0F0x98_x07_Reserved_5_5_WIDTH                          1
#define D0F0x98_x07_Reserved_5_5_MASK                           0x20
#define D0F0x98_x07_DmaReqRespPassPWMode_OFFSET                 6
#define D0F0x98_x07_DmaReqRespPassPWMode_WIDTH                  1
#define D0F0x98_x07_DmaReqRespPassPWMode_MASK                   0x40
#define D0F0x98_x07_IommuIsocPassPWMode_OFFSET                  7
#define D0F0x98_x07_IommuIsocPassPWMode_WIDTH                   1
#define D0F0x98_x07_IommuIsocPassPWMode_MASK                    0x80
#define D0F0x98_x07_Reserved_13_8_OFFSET                        8
#define D0F0x98_x07_Reserved_13_8_WIDTH                         6
#define D0F0x98_x07_Reserved_13_8_MASK                          0x3f00
#define D0F0x98_x07_MSIHTIntConversionEn_OFFSET                 14
#define D0F0x98_x07_MSIHTIntConversionEn_WIDTH                  1
#define D0F0x98_x07_MSIHTIntConversionEn_MASK                   0x4000
#define D0F0x98_x07_DropZeroMaskWrEn_OFFSET                     15
#define D0F0x98_x07_DropZeroMaskWrEn_WIDTH                      1
#define D0F0x98_x07_DropZeroMaskWrEn_MASK                       0x8000
#define D0F0x98_x07_Reserved_29_16_OFFSET                       16
#define D0F0x98_x07_Reserved_29_16_WIDTH                        14
#define D0F0x98_x07_Reserved_29_16_MASK                         0x3fff0000
#define D0F0x98_x07_UnadjustThrottlingStpclk_OFFSET             30
#define D0F0x98_x07_UnadjustThrottlingStpclk_WIDTH              1
#define D0F0x98_x07_UnadjustThrottlingStpclk_MASK               0x40000000
#define D0F0x98_x07_SMUCsrIsocEn_OFFSET                         31
#define D0F0x98_x07_SMUCsrIsocEn_WIDTH                          1
#define D0F0x98_x07_SMUCsrIsocEn_MASK                           0x80000000

/// D0F0x98_x07
typedef union {
  struct {                                                              ///<
    UINT32                                               IocBwOptEn:1 ; ///<
    UINT32                                             Reserved_3_1:3 ; ///<
    UINT32                                             IommuBwOptEn:1 ; ///<
    UINT32                                             Reserved_5_5:1 ; ///<
    UINT32                                     DmaReqRespPassPWMode:1 ; ///<
    UINT32                                      IommuIsocPassPWMode:1 ; ///<
    UINT32                                            Reserved_13_8:6 ; ///<
    UINT32                                     MSIHTIntConversionEn:1 ; ///<
    UINT32                                         DropZeroMaskWrEn:1 ; ///<
    UINT32                                           Reserved_29_16:14; ///<
    UINT32                                 UnadjustThrottlingStpclk:1 ; ///<
    UINT32                                             SMUCsrIsocEn:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x98_x07_STRUCT;

// **** D0F0x98_x08 Register Definition ****
// Address
#define D0F0x98_x08_ADDRESS                                     0x8

// Type
#define D0F0x98_x08_TYPE                                        TYPE_D0F0x98
// Field Data
#define D0F0x98_x08_NpWrrLenA_OFFSET                            0
#define D0F0x98_x08_NpWrrLenA_WIDTH                             8
#define D0F0x98_x08_NpWrrLenA_MASK                              0xff
#define D0F0x98_x08_NpWrrLenB_OFFSET                            8
#define D0F0x98_x08_NpWrrLenB_WIDTH                             8
#define D0F0x98_x08_NpWrrLenB_MASK                              0xff00
#define D0F0x98_x08_NpWrrLenC_OFFSET                            16
#define D0F0x98_x08_NpWrrLenC_WIDTH                             8
#define D0F0x98_x08_NpWrrLenC_MASK                              0xff0000
#define D0F0x98_x08_Reserved_31_24_OFFSET                       24
#define D0F0x98_x08_Reserved_31_24_WIDTH                        8
#define D0F0x98_x08_Reserved_31_24_MASK                         0xff000000

/// D0F0x98_x08
typedef union {
  struct {                                                              ///<
    UINT32                                                NpWrrLenA:8 ; ///<
    UINT32                                                NpWrrLenB:8 ; ///<
    UINT32                                                NpWrrLenC:8 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x98_x08_STRUCT;

// **** D0F0x98_x09 Register Definition ****
// Address
#define D0F0x98_x09_ADDRESS                                     0x9

// Type
#define D0F0x98_x09_TYPE                                        TYPE_D0F0x98
// Field Data
#define D0F0x98_x09_PWrrLenA_OFFSET                             0
#define D0F0x98_x09_PWrrLenA_WIDTH                              8
#define D0F0x98_x09_PWrrLenA_MASK                               0xff
#define D0F0x98_x09_PWrrLenB_OFFSET                             8
#define D0F0x98_x09_PWrrLenB_WIDTH                              8
#define D0F0x98_x09_PWrrLenB_MASK                               0xff00
#define D0F0x98_x09_Reserved_31_16_OFFSET                       16
#define D0F0x98_x09_Reserved_31_16_WIDTH                        16
#define D0F0x98_x09_Reserved_31_16_MASK                         0xffff0000

/// D0F0x98_x09
typedef union {
  struct {                                                              ///<
    UINT32                                                 PWrrLenA:8 ; ///<
    UINT32                                                 PWrrLenB:8 ; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x98_x09_STRUCT;

// **** D0F0x98_x0C Register Definition ****
// Address
#define D0F0x98_x0C_ADDRESS                                     0xc

// Type
#define D0F0x98_x0C_TYPE                                        TYPE_D0F0x98
// Field Data
#define D0F0x98_x0C_GcmWrrLenA_OFFSET                           0
#define D0F0x98_x0C_GcmWrrLenA_WIDTH                            8
#define D0F0x98_x0C_GcmWrrLenA_MASK                             0xff
#define D0F0x98_x0C_GcmWrrLenB_OFFSET                           8
#define D0F0x98_x0C_GcmWrrLenB_WIDTH                            8
#define D0F0x98_x0C_GcmWrrLenB_MASK                             0xff00
#define D0F0x98_x0C_Reserved_29_16_OFFSET                       16
#define D0F0x98_x0C_Reserved_29_16_WIDTH                        14
#define D0F0x98_x0C_Reserved_29_16_MASK                         0x3fff0000
#define D0F0x98_x0C_StrictSelWinnerEn_OFFSET                    30
#define D0F0x98_x0C_StrictSelWinnerEn_WIDTH                     1
#define D0F0x98_x0C_StrictSelWinnerEn_MASK                      0x40000000
#define D0F0x98_x0C_Reserved_31_31_OFFSET                       31
#define D0F0x98_x0C_Reserved_31_31_WIDTH                        1
#define D0F0x98_x0C_Reserved_31_31_MASK                         0x80000000

/// D0F0x98_x0C
typedef union {
  struct {                                                              ///<
    UINT32                                               GcmWrrLenA:8 ; ///<
    UINT32                                               GcmWrrLenB:8 ; ///<
    UINT32                                           Reserved_29_16:14; ///<
    UINT32                                        StrictSelWinnerEn:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x98_x0C_STRUCT;

// **** D0F0x98_x1E Register Definition ****
// Address
#define D0F0x98_x1E_ADDRESS                                     0x1e

// Type
#define D0F0x98_x1E_TYPE                                        TYPE_D0F0x98
// Field Data
#define D0F0x98_x1E_Reserved_0_0_OFFSET                         0
#define D0F0x98_x1E_Reserved_0_0_WIDTH                          1
#define D0F0x98_x1E_Reserved_0_0_MASK                           0x1
#define D0F0x98_x1E_HiPriEn_OFFSET                              1
#define D0F0x98_x1E_HiPriEn_WIDTH                               1
#define D0F0x98_x1E_HiPriEn_MASK                                0x2
#define D0F0x98_x1E_Reserved_31_2_OFFSET                        2
#define D0F0x98_x1E_Reserved_31_2_WIDTH                         30
#define D0F0x98_x1E_Reserved_31_2_MASK                          0xfffffffc

/// D0F0x98_x1E
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                  HiPriEn:1 ; ///<
    UINT32                                            Reserved_31_2:30; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x98_x1E_STRUCT;

// **** D0F0x98_x26 Register Definition ****
// Address
#define D0F0x98_x26_ADDRESS                                     0x26

// Type
#define D0F0x98_x26_TYPE                                        TYPE_D0F0x98
// Field Data
#define D0F0x98_x26_IOMMUUrAddr_39_32__OFFSET                   0
#define D0F0x98_x26_IOMMUUrAddr_39_32__WIDTH                    8
#define D0F0x98_x26_IOMMUUrAddr_39_32__MASK                     0xff
#define D0F0x98_x26_Reserved_31_8_OFFSET                        8
#define D0F0x98_x26_Reserved_31_8_WIDTH                         24
#define D0F0x98_x26_Reserved_31_8_MASK                          0xffffff00

/// D0F0x98_x26
typedef union {
  struct {                                                              ///<
    UINT32                                       IOMMUUrAddr_39_32_:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x98_x26_STRUCT;

// **** D0F0x98_x27 Register Definition ****
// Address
#define D0F0x98_x27_ADDRESS                                     0x27

// Type
#define D0F0x98_x27_TYPE                                        TYPE_D0F0x98
// Field Data
#define D0F0x98_x27_Reserved_5_0_OFFSET                         0
#define D0F0x98_x27_Reserved_5_0_WIDTH                          6
#define D0F0x98_x27_Reserved_5_0_MASK                           0x3f
#define D0F0x98_x27_IOMMUUrAddr_31_6__OFFSET                    6
#define D0F0x98_x27_IOMMUUrAddr_31_6__WIDTH                     26
#define D0F0x98_x27_IOMMUUrAddr_31_6__MASK                      0xffffffc0

/// D0F0x98_x27
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_5_0:6 ; ///<
    UINT32                                        IOMMUUrAddr_31_6_:26; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x98_x27_STRUCT;

// **** D0F0x98_x28 Register Definition ****
// Address
#define D0F0x98_x28_ADDRESS                                     0x28

// Type
#define D0F0x98_x28_TYPE                                        TYPE_D0F0x98
// Field Data
#define D0F0x98_x28_Reserved_0_0_OFFSET                         0
#define D0F0x98_x28_Reserved_0_0_WIDTH                          1
#define D0F0x98_x28_Reserved_0_0_MASK                           0x1
#define D0F0x98_x28_ForceCoherentIntr_OFFSET                    1
#define D0F0x98_x28_ForceCoherentIntr_WIDTH                     1
#define D0F0x98_x28_ForceCoherentIntr_MASK                      0x2
#define D0F0x98_x28_Reserved_31_2_OFFSET                        2
#define D0F0x98_x28_Reserved_31_2_WIDTH                         30
#define D0F0x98_x28_Reserved_31_2_MASK                          0xfffffffc

/// D0F0x98_x28
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                        ForceCoherentIntr:1 ; ///<
    UINT32                                            Reserved_31_2:30; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x98_x28_STRUCT;


// **** D0F0x98_x2C Register Definition ****
// Address
#define D0F0x98_x2C_ADDRESS                                     0x2c

// Type
#define D0F0x98_x2C_TYPE                                        TYPE_D0F0x98
// Field Data
#define D0F0x98_x2C_Reserved_0_0_OFFSET                         0
#define D0F0x98_x2C_Reserved_0_0_WIDTH                          1
#define D0F0x98_x2C_Reserved_0_0_MASK                           0x1
#define D0F0x98_x2C_DynWakeEn_OFFSET                            1
#define D0F0x98_x2C_DynWakeEn_WIDTH                             1
#define D0F0x98_x2C_DynWakeEn_MASK                              0x2
#define D0F0x98_x2C_Reserved_7_2_OFFSET                         2
#define D0F0x98_x2C_Reserved_7_2_WIDTH                          6
#define D0F0x98_x2C_Reserved_7_2_MASK                           0xfc
#define D0F0x98_x2C_OrbRxIdlesMask_OFFSET                       8
#define D0F0x98_x2C_OrbRxIdlesMask_WIDTH                        1
#define D0F0x98_x2C_OrbRxIdlesMask_MASK                         0x100
#define D0F0x98_x2C_SBDmaActiveMask_OFFSET                      9
#define D0F0x98_x2C_SBDmaActiveMask_WIDTH                       1
#define D0F0x98_x2C_SBDmaActiveMask_MASK                        0x200
#define D0F0x98_x2C_NBOutbWakeMask_OFFSET                       10
#define D0F0x98_x2C_NBOutbWakeMask_WIDTH                        1
#define D0F0x98_x2C_NBOutbWakeMask_MASK                         0x400
#define D0F0x98_x2C_Reserved_15_11_OFFSET                       11
#define D0F0x98_x2C_Reserved_15_11_WIDTH                        5
#define D0F0x98_x2C_Reserved_15_11_MASK                         0xf800
#define D0F0x98_x2C_WakeHysteresis_OFFSET                       16
#define D0F0x98_x2C_WakeHysteresis_WIDTH                        16
#define D0F0x98_x2C_WakeHysteresis_MASK                         0xffff0000

/// D0F0x98_x2C
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                DynWakeEn:1 ; ///<
    UINT32                                             Reserved_7_2:6 ; ///<
    UINT32                                           OrbRxIdlesMask:1 ; ///<
    UINT32                                          SBDmaActiveMask:1 ; ///<
    UINT32                                           NBOutbWakeMask:1 ; ///<
    UINT32                                           Reserved_15_11:5 ; ///<
    UINT32                                           WakeHysteresis:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x98_x2C_STRUCT;

// **** D0F0x98_x3A Register Definition ****
// Address
#define D0F0x98_x3A_ADDRESS                                     0x3a

// Type
#define D0F0x98_x3A_TYPE                                        TYPE_D0F0x98
// Field Data
#define D0F0x98_x3A_ClumpingEn_OFFSET                           0
#define D0F0x98_x3A_ClumpingEn_WIDTH                            32
#define D0F0x98_x3A_ClumpingEn_MASK                             0xffffffff

/// D0F0x98_x3A
typedef union {
  struct {                                                              ///<
    UINT32                                               ClumpingEn:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x98_x3A_STRUCT;

// **** D0F0x98_x49 Register Definition ****
// Address
#define D0F0x98_x49_ADDRESS                                     0x49

// Type
#define D0F0x98_x49_TYPE                                        TYPE_D0F0x98
// Field Data
#define D0F0x98_x49_Reserved_23_0_OFFSET                        0
#define D0F0x98_x49_Reserved_23_0_WIDTH                         24
#define D0F0x98_x49_Reserved_23_0_MASK                          0xffffff
#define D0F0x98_x49_SoftOverrideClk6_OFFSET                     24
#define D0F0x98_x49_SoftOverrideClk6_WIDTH                      1
#define D0F0x98_x49_SoftOverrideClk6_MASK                       0x1000000
#define D0F0x98_x49_SoftOverrideClk5_OFFSET                     25
#define D0F0x98_x49_SoftOverrideClk5_WIDTH                      1
#define D0F0x98_x49_SoftOverrideClk5_MASK                       0x2000000
#define D0F0x98_x49_SoftOverrideClk4_OFFSET                     26
#define D0F0x98_x49_SoftOverrideClk4_WIDTH                      1
#define D0F0x98_x49_SoftOverrideClk4_MASK                       0x4000000
#define D0F0x98_x49_SoftOverrideClk3_OFFSET                     27
#define D0F0x98_x49_SoftOverrideClk3_WIDTH                      1
#define D0F0x98_x49_SoftOverrideClk3_MASK                       0x8000000
#define D0F0x98_x49_SoftOverrideClk2_OFFSET                     28
#define D0F0x98_x49_SoftOverrideClk2_WIDTH                      1
#define D0F0x98_x49_SoftOverrideClk2_MASK                       0x10000000
#define D0F0x98_x49_SoftOverrideClk1_OFFSET                     29
#define D0F0x98_x49_SoftOverrideClk1_WIDTH                      1
#define D0F0x98_x49_SoftOverrideClk1_MASK                       0x20000000
#define D0F0x98_x49_SoftOverrideClk0_OFFSET                     30
#define D0F0x98_x49_SoftOverrideClk0_WIDTH                      1
#define D0F0x98_x49_SoftOverrideClk0_MASK                       0x40000000
#define D0F0x98_x49_Reserved_31_31_OFFSET                       31
#define D0F0x98_x49_Reserved_31_31_WIDTH                        1
#define D0F0x98_x49_Reserved_31_31_MASK                         0x80000000

/// D0F0x98_x49
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_23_0:24; ///<
    UINT32                                         SoftOverrideClk6:1 ; ///<
    UINT32                                         SoftOverrideClk5:1 ; ///<
    UINT32                                         SoftOverrideClk4:1 ; ///<
    UINT32                                         SoftOverrideClk3:1 ; ///<
    UINT32                                         SoftOverrideClk2:1 ; ///<
    UINT32                                         SoftOverrideClk1:1 ; ///<
    UINT32                                         SoftOverrideClk0:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x98_x49_STRUCT;

// **** D0F0x98_x4A Register Definition ****
// Address
#define D0F0x98_x4A_ADDRESS                                     0x4a

// Type
#define D0F0x98_x4A_TYPE                                        TYPE_D0F0x98
// Field Data
#define D0F0x98_x4A_Reserved_23_0_OFFSET                        0
#define D0F0x98_x4A_Reserved_23_0_WIDTH                         24
#define D0F0x98_x4A_Reserved_23_0_MASK                          0xffffff
#define D0F0x98_x4A_SoftOverrideClk6_OFFSET                     24
#define D0F0x98_x4A_SoftOverrideClk6_WIDTH                      1
#define D0F0x98_x4A_SoftOverrideClk6_MASK                       0x1000000
#define D0F0x98_x4A_SoftOverrideClk5_OFFSET                     25
#define D0F0x98_x4A_SoftOverrideClk5_WIDTH                      1
#define D0F0x98_x4A_SoftOverrideClk5_MASK                       0x2000000
#define D0F0x98_x4A_SoftOverrideClk4_OFFSET                     26
#define D0F0x98_x4A_SoftOverrideClk4_WIDTH                      1
#define D0F0x98_x4A_SoftOverrideClk4_MASK                       0x4000000
#define D0F0x98_x4A_SoftOverrideClk3_OFFSET                     27
#define D0F0x98_x4A_SoftOverrideClk3_WIDTH                      1
#define D0F0x98_x4A_SoftOverrideClk3_MASK                       0x8000000
#define D0F0x98_x4A_SoftOverrideClk2_OFFSET                     28
#define D0F0x98_x4A_SoftOverrideClk2_WIDTH                      1
#define D0F0x98_x4A_SoftOverrideClk2_MASK                       0x10000000
#define D0F0x98_x4A_SoftOverrideClk1_OFFSET                     29
#define D0F0x98_x4A_SoftOverrideClk1_WIDTH                      1
#define D0F0x98_x4A_SoftOverrideClk1_MASK                       0x20000000
#define D0F0x98_x4A_SoftOverrideClk0_OFFSET                     30
#define D0F0x98_x4A_SoftOverrideClk0_WIDTH                      1
#define D0F0x98_x4A_SoftOverrideClk0_MASK                       0x40000000
#define D0F0x98_x4A_Reserved_31_31_OFFSET                       31
#define D0F0x98_x4A_Reserved_31_31_WIDTH                        1
#define D0F0x98_x4A_Reserved_31_31_MASK                         0x80000000

/// D0F0x98_x4A
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_23_0:24; ///<
    UINT32                                         SoftOverrideClk6:1 ; ///<
    UINT32                                         SoftOverrideClk5:1 ; ///<
    UINT32                                         SoftOverrideClk4:1 ; ///<
    UINT32                                         SoftOverrideClk3:1 ; ///<
    UINT32                                         SoftOverrideClk2:1 ; ///<
    UINT32                                         SoftOverrideClk1:1 ; ///<
    UINT32                                         SoftOverrideClk0:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0x98_x4A_STRUCT;

// **** D0F0xBC_x1F200 Register Definition ****
// Address
#define D0F0xBC_x1F200_ADDRESS                                  0x1f200

// Type
#define D0F0xBC_x1F200_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F200_StateValid_OFFSET                        0
#define D0F0xBC_x1F200_StateValid_WIDTH                         1
#define D0F0xBC_x1F200_StateValid_MASK                          0x1
#define D0F0xBC_x1F200_Reserved_7_1_OFFSET                      1
#define D0F0xBC_x1F200_Reserved_7_1_WIDTH                       7
#define D0F0xBC_x1F200_Reserved_7_1_MASK                        0xfe
#define D0F0xBC_x1F200_LclkDivider_OFFSET                       8
#define D0F0xBC_x1F200_LclkDivider_WIDTH                        8
#define D0F0xBC_x1F200_LclkDivider_MASK                         0xff00
#define D0F0xBC_x1F200_VID_OFFSET                               16
#define D0F0xBC_x1F200_VID_WIDTH                                8
#define D0F0xBC_x1F200_VID_MASK                                 0xff0000
#define D0F0xBC_x1F200_LowVoltageReqThreshold_OFFSET            24
#define D0F0xBC_x1F200_LowVoltageReqThreshold_WIDTH             8
#define D0F0xBC_x1F200_LowVoltageReqThreshold_MASK              0xff000000

/// D0F0xBC_x1F200
typedef union {
  struct {                                                              ///<
    UINT32                                               StateValid:1 ; ///<
    UINT32                                             Reserved_7_1:7 ; ///<
    UINT32                                              LclkDivider:8 ; ///<
    UINT32                                                      VID:8 ; ///<
    UINT32                                   LowVoltageReqThreshold:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F200_STRUCT;

// **** D0F0xBC_x1F208 Register Definition ****
// Address
#define D0F0xBC_x1F208_ADDRESS                                  0x1f208

// Type
#define D0F0xBC_x1F208_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F208_HysteresisUp_OFFSET                      0
#define D0F0xBC_x1F208_HysteresisUp_WIDTH                       8
#define D0F0xBC_x1F208_HysteresisUp_MASK                        0xff
#define D0F0xBC_x1F208_HysteresisDown_OFFSET                    8
#define D0F0xBC_x1F208_HysteresisDown_WIDTH                     8
#define D0F0xBC_x1F208_HysteresisDown_MASK                      0xff00
#define D0F0xBC_x1F208_ResidencyCounter_OFFSET                  16
#define D0F0xBC_x1F208_ResidencyCounter_WIDTH                   16
#define D0F0xBC_x1F208_ResidencyCounter_MASK                    0xffff0000

/// D0F0xBC_x1F208
typedef union {
  struct {                                                              ///<
    UINT32                                             HysteresisUp:8 ; ///<
    UINT32                                           HysteresisDown:8 ; ///<
    UINT32                                         ResidencyCounter:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F208_STRUCT;

// **** D0F0xBC_x1F210 Register Definition ****
// Address
#define D0F0xBC_x1F210_ADDRESS                                  0x1f210

// Type
#define D0F0xBC_x1F210_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F210_ActivityThreshold_OFFSET                 0
#define D0F0xBC_x1F210_ActivityThreshold_WIDTH                  8
#define D0F0xBC_x1F210_ActivityThreshold_MASK                   0xff
#define D0F0xBC_x1F210_Reserved_31_8_OFFSET                     8
#define D0F0xBC_x1F210_Reserved_31_8_WIDTH                      24
#define D0F0xBC_x1F210_Reserved_31_8_MASK                       0xffffff00

/// D0F0xBC_x1F210
typedef union {
  struct {                                                              ///<
    UINT32                                        ActivityThreshold:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F210_STRUCT;

// **** D0F0xBC_x1F220 Register Definition ****
// Address
#define D0F0xBC_x1F220_ADDRESS                                  0x1f220

// Type
#define D0F0xBC_x1F220_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F220_StateValid_OFFSET                        0
#define D0F0xBC_x1F220_StateValid_WIDTH                         1
#define D0F0xBC_x1F220_StateValid_MASK                          0x1
#define D0F0xBC_x1F220_Reserved_7_1_OFFSET                      1
#define D0F0xBC_x1F220_Reserved_7_1_WIDTH                       7
#define D0F0xBC_x1F220_Reserved_7_1_MASK                        0xfe
#define D0F0xBC_x1F220_LclkDivider_OFFSET                       8
#define D0F0xBC_x1F220_LclkDivider_WIDTH                        8
#define D0F0xBC_x1F220_LclkDivider_MASK                         0xff00
#define D0F0xBC_x1F220_VID_OFFSET                               16
#define D0F0xBC_x1F220_VID_WIDTH                                8
#define D0F0xBC_x1F220_VID_MASK                                 0xff0000
#define D0F0xBC_x1F220_LowVoltageReqThreshold_OFFSET            24
#define D0F0xBC_x1F220_LowVoltageReqThreshold_WIDTH             8
#define D0F0xBC_x1F220_LowVoltageReqThreshold_MASK              0xff000000

/// D0F0xBC_x1F220
typedef union {
  struct {                                                              ///<
    UINT32                                               StateValid:1 ; ///<
    UINT32                                             Reserved_7_1:7 ; ///<
    UINT32                                              LclkDivider:8 ; ///<
    UINT32                                                      VID:8 ; ///<
    UINT32                                   LowVoltageReqThreshold:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F220_STRUCT;

// **** D0F0xBC_x1F228 Register Definition ****
// Address
#define D0F0xBC_x1F228_ADDRESS                                  0x1f228

// Type
#define D0F0xBC_x1F228_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F228_HysteresisUp_OFFSET                      0
#define D0F0xBC_x1F228_HysteresisUp_WIDTH                       8
#define D0F0xBC_x1F228_HysteresisUp_MASK                        0xff
#define D0F0xBC_x1F228_HysteresisDown_OFFSET                    8
#define D0F0xBC_x1F228_HysteresisDown_WIDTH                     8
#define D0F0xBC_x1F228_HysteresisDown_MASK                      0xff00
#define D0F0xBC_x1F228_ResidencyCounter_OFFSET                  16
#define D0F0xBC_x1F228_ResidencyCounter_WIDTH                   16
#define D0F0xBC_x1F228_ResidencyCounter_MASK                    0xffff0000

/// D0F0xBC_x1F228
typedef union {
  struct {                                                              ///<
    UINT32                                             HysteresisUp:8 ; ///<
    UINT32                                           HysteresisDown:8 ; ///<
    UINT32                                         ResidencyCounter:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F228_STRUCT;

// **** D0F0xBC_x1F230 Register Definition ****
// Address
#define D0F0xBC_x1F230_ADDRESS                                  0x1f230

// Type
#define D0F0xBC_x1F230_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F230_ActivityThreshold_OFFSET                 0
#define D0F0xBC_x1F230_ActivityThreshold_WIDTH                  8
#define D0F0xBC_x1F230_ActivityThreshold_MASK                   0xff
#define D0F0xBC_x1F230_Reserved_31_8_OFFSET                     8
#define D0F0xBC_x1F230_Reserved_31_8_WIDTH                      24
#define D0F0xBC_x1F230_Reserved_31_8_MASK                       0xffffff00

/// D0F0xBC_x1F230
typedef union {
  struct {                                                              ///<
    UINT32                                        ActivityThreshold:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F230_STRUCT;

// **** D0F0xBC_x1F240 Register Definition ****
// Address
#define D0F0xBC_x1F240_ADDRESS                                  0x1f240

// Type
#define D0F0xBC_x1F240_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F240_StateValid_OFFSET                        0
#define D0F0xBC_x1F240_StateValid_WIDTH                         1
#define D0F0xBC_x1F240_StateValid_MASK                          0x1
#define D0F0xBC_x1F240_Reserved_7_1_OFFSET                      1
#define D0F0xBC_x1F240_Reserved_7_1_WIDTH                       7
#define D0F0xBC_x1F240_Reserved_7_1_MASK                        0xfe
#define D0F0xBC_x1F240_LclkDivider_OFFSET                       8
#define D0F0xBC_x1F240_LclkDivider_WIDTH                        8
#define D0F0xBC_x1F240_LclkDivider_MASK                         0xff00
#define D0F0xBC_x1F240_VID_OFFSET                               16
#define D0F0xBC_x1F240_VID_WIDTH                                8
#define D0F0xBC_x1F240_VID_MASK                                 0xff0000
#define D0F0xBC_x1F240_LowVoltageReqThreshold_OFFSET            24
#define D0F0xBC_x1F240_LowVoltageReqThreshold_WIDTH             8
#define D0F0xBC_x1F240_LowVoltageReqThreshold_MASK              0xff000000

/// D0F0xBC_x1F240
typedef union {
  struct {                                                              ///<
    UINT32                                               StateValid:1 ; ///<
    UINT32                                             Reserved_7_1:7 ; ///<
    UINT32                                              LclkDivider:8 ; ///<
    UINT32                                                      VID:8 ; ///<
    UINT32                                   LowVoltageReqThreshold:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F240_STRUCT;

// **** D0F0xBC_x1F248 Register Definition ****
// Address
#define D0F0xBC_x1F248_ADDRESS                                  0x1f248

// Type
#define D0F0xBC_x1F248_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F248_HysteresisUp_OFFSET                      0
#define D0F0xBC_x1F248_HysteresisUp_WIDTH                       8
#define D0F0xBC_x1F248_HysteresisUp_MASK                        0xff
#define D0F0xBC_x1F248_HysteresisDown_OFFSET                    8
#define D0F0xBC_x1F248_HysteresisDown_WIDTH                     8
#define D0F0xBC_x1F248_HysteresisDown_MASK                      0xff00
#define D0F0xBC_x1F248_ResidencyCounter_OFFSET                  16
#define D0F0xBC_x1F248_ResidencyCounter_WIDTH                   16
#define D0F0xBC_x1F248_ResidencyCounter_MASK                    0xffff0000

/// D0F0xBC_x1F248
typedef union {
  struct {                                                              ///<
    UINT32                                             HysteresisUp:8 ; ///<
    UINT32                                           HysteresisDown:8 ; ///<
    UINT32                                         ResidencyCounter:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F248_STRUCT;

// **** D0F0xBC_x1F250 Register Definition ****
// Address
#define D0F0xBC_x1F250_ADDRESS                                  0x1f250

// Type
#define D0F0xBC_x1F250_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F250_ActivityThreshold_OFFSET                 0
#define D0F0xBC_x1F250_ActivityThreshold_WIDTH                  8
#define D0F0xBC_x1F250_ActivityThreshold_MASK                   0xff
#define D0F0xBC_x1F250_Reserved_31_8_OFFSET                     8
#define D0F0xBC_x1F250_Reserved_31_8_WIDTH                      24
#define D0F0xBC_x1F250_Reserved_31_8_MASK                       0xffffff00

/// D0F0xBC_x1F250
typedef union {
  struct {                                                              ///<
    UINT32                                        ActivityThreshold:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F250_STRUCT;

// **** D0F0xBC_x1F260 Register Definition ****
// Address
#define D0F0xBC_x1F260_ADDRESS                                  0x1f260

// Type
#define D0F0xBC_x1F260_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F260_StateValid_OFFSET                        0
#define D0F0xBC_x1F260_StateValid_WIDTH                         1
#define D0F0xBC_x1F260_StateValid_MASK                          0x1
#define D0F0xBC_x1F260_Reserved_7_1_OFFSET                      1
#define D0F0xBC_x1F260_Reserved_7_1_WIDTH                       7
#define D0F0xBC_x1F260_Reserved_7_1_MASK                        0xfe
#define D0F0xBC_x1F260_LclkDivider_OFFSET                       8
#define D0F0xBC_x1F260_LclkDivider_WIDTH                        8
#define D0F0xBC_x1F260_LclkDivider_MASK                         0xff00
#define D0F0xBC_x1F260_VID_OFFSET                               16
#define D0F0xBC_x1F260_VID_WIDTH                                8
#define D0F0xBC_x1F260_VID_MASK                                 0xff0000
#define D0F0xBC_x1F260_LowVoltageReqThreshold_OFFSET            24
#define D0F0xBC_x1F260_LowVoltageReqThreshold_WIDTH             8
#define D0F0xBC_x1F260_LowVoltageReqThreshold_MASK              0xff000000

/// D0F0xBC_x1F260
typedef union {
  struct {                                                              ///<
    UINT32                                               StateValid:1 ; ///<
    UINT32                                             Reserved_7_1:7 ; ///<
    UINT32                                              LclkDivider:8 ; ///<
    UINT32                                                      VID:8 ; ///<
    UINT32                                   LowVoltageReqThreshold:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F260_STRUCT;

// **** D0F0xBC_x1F268 Register Definition ****
// Address
#define D0F0xBC_x1F268_ADDRESS                                  0x1f268

// Type
#define D0F0xBC_x1F268_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F268_HysteresisUp_OFFSET                      0
#define D0F0xBC_x1F268_HysteresisUp_WIDTH                       8
#define D0F0xBC_x1F268_HysteresisUp_MASK                        0xff
#define D0F0xBC_x1F268_HysteresisDown_OFFSET                    8
#define D0F0xBC_x1F268_HysteresisDown_WIDTH                     8
#define D0F0xBC_x1F268_HysteresisDown_MASK                      0xff00
#define D0F0xBC_x1F268_ResidencyCounter_OFFSET                  16
#define D0F0xBC_x1F268_ResidencyCounter_WIDTH                   16
#define D0F0xBC_x1F268_ResidencyCounter_MASK                    0xffff0000

/// D0F0xBC_x1F268
typedef union {
  struct {                                                              ///<
    UINT32                                             HysteresisUp:8 ; ///<
    UINT32                                           HysteresisDown:8 ; ///<
    UINT32                                         ResidencyCounter:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F268_STRUCT;

// **** D0F0xBC_x1F270 Register Definition ****
// Address
#define D0F0xBC_x1F270_ADDRESS                                  0x1f270

// Type
#define D0F0xBC_x1F270_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F270_ActivityThreshold_OFFSET                 0
#define D0F0xBC_x1F270_ActivityThreshold_WIDTH                  8
#define D0F0xBC_x1F270_ActivityThreshold_MASK                   0xff
#define D0F0xBC_x1F270_Reserved_31_8_OFFSET                     8
#define D0F0xBC_x1F270_Reserved_31_8_WIDTH                      24
#define D0F0xBC_x1F270_Reserved_31_8_MASK                       0xffffff00

/// D0F0xBC_x1F270
typedef union {
  struct {                                                              ///<
    UINT32                                        ActivityThreshold:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F270_STRUCT;

// **** D0F0xBC_x1F280 Register Definition ****
// Address
#define D0F0xBC_x1F280_ADDRESS                                  0x1f280

// Type
#define D0F0xBC_x1F280_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F280_StateValid_OFFSET                        0
#define D0F0xBC_x1F280_StateValid_WIDTH                         1
#define D0F0xBC_x1F280_StateValid_MASK                          0x1
#define D0F0xBC_x1F280_Reserved_7_1_OFFSET                      1
#define D0F0xBC_x1F280_Reserved_7_1_WIDTH                       7
#define D0F0xBC_x1F280_Reserved_7_1_MASK                        0xfe
#define D0F0xBC_x1F280_LclkDivider_OFFSET                       8
#define D0F0xBC_x1F280_LclkDivider_WIDTH                        8
#define D0F0xBC_x1F280_LclkDivider_MASK                         0xff00
#define D0F0xBC_x1F280_VID_OFFSET                               16
#define D0F0xBC_x1F280_VID_WIDTH                                8
#define D0F0xBC_x1F280_VID_MASK                                 0xff0000
#define D0F0xBC_x1F280_LowVoltageReqThreshold_OFFSET            24
#define D0F0xBC_x1F280_LowVoltageReqThreshold_WIDTH             8
#define D0F0xBC_x1F280_LowVoltageReqThreshold_MASK              0xff000000

/// D0F0xBC_x1F280
typedef union {
  struct {                                                              ///<
    UINT32                                               StateValid:1 ; ///<
    UINT32                                             Reserved_7_1:7 ; ///<
    UINT32                                              LclkDivider:8 ; ///<
    UINT32                                                      VID:8 ; ///<
    UINT32                                   LowVoltageReqThreshold:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F280_STRUCT;

// **** D0F0xBC_x1F288 Register Definition ****
// Address
#define D0F0xBC_x1F288_ADDRESS                                  0x1f288

// Type
#define D0F0xBC_x1F288_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F288_HysteresisUp_OFFSET                      0
#define D0F0xBC_x1F288_HysteresisUp_WIDTH                       8
#define D0F0xBC_x1F288_HysteresisUp_MASK                        0xff
#define D0F0xBC_x1F288_HysteresisDown_OFFSET                    8
#define D0F0xBC_x1F288_HysteresisDown_WIDTH                     8
#define D0F0xBC_x1F288_HysteresisDown_MASK                      0xff00
#define D0F0xBC_x1F288_ResidencyCounter_OFFSET                  16
#define D0F0xBC_x1F288_ResidencyCounter_WIDTH                   16
#define D0F0xBC_x1F288_ResidencyCounter_MASK                    0xffff0000

/// D0F0xBC_x1F288
typedef union {
  struct {                                                              ///<
    UINT32                                             HysteresisUp:8 ; ///<
    UINT32                                           HysteresisDown:8 ; ///<
    UINT32                                         ResidencyCounter:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F288_STRUCT;

// **** D0F0xBC_x1F290 Register Definition ****
// Address
#define D0F0xBC_x1F290_ADDRESS                                  0x1f290

// Type
#define D0F0xBC_x1F290_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F290_ActivityThreshold_OFFSET                 0
#define D0F0xBC_x1F290_ActivityThreshold_WIDTH                  8
#define D0F0xBC_x1F290_ActivityThreshold_MASK                   0xff
#define D0F0xBC_x1F290_Reserved_31_8_OFFSET                     8
#define D0F0xBC_x1F290_Reserved_31_8_WIDTH                      24
#define D0F0xBC_x1F290_Reserved_31_8_MASK                       0xffffff00

/// D0F0xBC_x1F290
typedef union {
  struct {                                                              ///<
    UINT32                                        ActivityThreshold:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F290_STRUCT;

// **** D0F0xBC_x1F2A0 Register Definition ****
// Address
#define D0F0xBC_x1F2A0_ADDRESS                                  0x1f2a0

// Type
#define D0F0xBC_x1F2A0_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F2A0_StateValid_OFFSET                        0
#define D0F0xBC_x1F2A0_StateValid_WIDTH                         1
#define D0F0xBC_x1F2A0_StateValid_MASK                          0x1
#define D0F0xBC_x1F2A0_Reserved_7_1_OFFSET                      1
#define D0F0xBC_x1F2A0_Reserved_7_1_WIDTH                       7
#define D0F0xBC_x1F2A0_Reserved_7_1_MASK                        0xfe
#define D0F0xBC_x1F2A0_LclkDivider_OFFSET                       8
#define D0F0xBC_x1F2A0_LclkDivider_WIDTH                        8
#define D0F0xBC_x1F2A0_LclkDivider_MASK                         0xff00
#define D0F0xBC_x1F2A0_VID_OFFSET                               16
#define D0F0xBC_x1F2A0_VID_WIDTH                                8
#define D0F0xBC_x1F2A0_VID_MASK                                 0xff0000
#define D0F0xBC_x1F2A0_LowVoltageReqThreshold_OFFSET            24
#define D0F0xBC_x1F2A0_LowVoltageReqThreshold_WIDTH             8
#define D0F0xBC_x1F2A0_LowVoltageReqThreshold_MASK              0xff000000

/// D0F0xBC_x1F2A0
typedef union {
  struct {                                                              ///<
    UINT32                                               StateValid:1 ; ///<
    UINT32                                             Reserved_7_1:7 ; ///<
    UINT32                                              LclkDivider:8 ; ///<
    UINT32                                                      VID:8 ; ///<
    UINT32                                   LowVoltageReqThreshold:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F2A0_STRUCT;

// **** D0F0xBC_x1F2A8 Register Definition ****
// Address
#define D0F0xBC_x1F2A8_ADDRESS                                  0x1f2a8

// Type
#define D0F0xBC_x1F2A8_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F2A8_HysteresisUp_OFFSET                      0
#define D0F0xBC_x1F2A8_HysteresisUp_WIDTH                       8
#define D0F0xBC_x1F2A8_HysteresisUp_MASK                        0xff
#define D0F0xBC_x1F2A8_HysteresisDown_OFFSET                    8
#define D0F0xBC_x1F2A8_HysteresisDown_WIDTH                     8
#define D0F0xBC_x1F2A8_HysteresisDown_MASK                      0xff00
#define D0F0xBC_x1F2A8_ResidencyCounter_OFFSET                  16
#define D0F0xBC_x1F2A8_ResidencyCounter_WIDTH                   16
#define D0F0xBC_x1F2A8_ResidencyCounter_MASK                    0xffff0000

/// D0F0xBC_x1F2A8
typedef union {
  struct {                                                              ///<
    UINT32                                             HysteresisUp:8 ; ///<
    UINT32                                           HysteresisDown:8 ; ///<
    UINT32                                         ResidencyCounter:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F2A8_STRUCT;

// **** D0F0xBC_x1F2B0 Register Definition ****
// Address
#define D0F0xBC_x1F2B0_ADDRESS                                  0x1f2b0

// Type
#define D0F0xBC_x1F2B0_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F2B0_ActivityThreshold_OFFSET                 0
#define D0F0xBC_x1F2B0_ActivityThreshold_WIDTH                  8
#define D0F0xBC_x1F2B0_ActivityThreshold_MASK                   0xff
#define D0F0xBC_x1F2B0_Reserved_31_8_OFFSET                     8
#define D0F0xBC_x1F2B0_Reserved_31_8_WIDTH                      24
#define D0F0xBC_x1F2B0_Reserved_31_8_MASK                       0xffffff00

/// D0F0xBC_x1F2B0
typedef union {
  struct {                                                              ///<
    UINT32                                        ActivityThreshold:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F2B0_STRUCT;

// **** D0F0xBC_x1F2C0 Register Definition ****
// Address
#define D0F0xBC_x1F2C0_ADDRESS                                  0x1f2c0

// Type
#define D0F0xBC_x1F2C0_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F2C0_StateValid_OFFSET                        0
#define D0F0xBC_x1F2C0_StateValid_WIDTH                         1
#define D0F0xBC_x1F2C0_StateValid_MASK                          0x1
#define D0F0xBC_x1F2C0_Reserved_7_1_OFFSET                      1
#define D0F0xBC_x1F2C0_Reserved_7_1_WIDTH                       7
#define D0F0xBC_x1F2C0_Reserved_7_1_MASK                        0xfe
#define D0F0xBC_x1F2C0_LclkDivider_OFFSET                       8
#define D0F0xBC_x1F2C0_LclkDivider_WIDTH                        8
#define D0F0xBC_x1F2C0_LclkDivider_MASK                         0xff00
#define D0F0xBC_x1F2C0_VID_OFFSET                               16
#define D0F0xBC_x1F2C0_VID_WIDTH                                8
#define D0F0xBC_x1F2C0_VID_MASK                                 0xff0000
#define D0F0xBC_x1F2C0_LowVoltageReqThreshold_OFFSET            24
#define D0F0xBC_x1F2C0_LowVoltageReqThreshold_WIDTH             8
#define D0F0xBC_x1F2C0_LowVoltageReqThreshold_MASK              0xff000000

/// D0F0xBC_x1F2C0
typedef union {
  struct {                                                              ///<
    UINT32                                               StateValid:1 ; ///<
    UINT32                                             Reserved_7_1:7 ; ///<
    UINT32                                              LclkDivider:8 ; ///<
    UINT32                                                      VID:8 ; ///<
    UINT32                                   LowVoltageReqThreshold:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F2C0_STRUCT;

// **** D0F0xBC_x1F2C8 Register Definition ****
// Address
#define D0F0xBC_x1F2C8_ADDRESS                                  0x1f2c8

// Type
#define D0F0xBC_x1F2C8_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F2C8_HysteresisUp_OFFSET                      0
#define D0F0xBC_x1F2C8_HysteresisUp_WIDTH                       8
#define D0F0xBC_x1F2C8_HysteresisUp_MASK                        0xff
#define D0F0xBC_x1F2C8_HysteresisDown_OFFSET                    8
#define D0F0xBC_x1F2C8_HysteresisDown_WIDTH                     8
#define D0F0xBC_x1F2C8_HysteresisDown_MASK                      0xff00
#define D0F0xBC_x1F2C8_ResidencyCounter_OFFSET                  16
#define D0F0xBC_x1F2C8_ResidencyCounter_WIDTH                   16
#define D0F0xBC_x1F2C8_ResidencyCounter_MASK                    0xffff0000

/// D0F0xBC_x1F2C8
typedef union {
  struct {                                                              ///<
    UINT32                                             HysteresisUp:8 ; ///<
    UINT32                                           HysteresisDown:8 ; ///<
    UINT32                                         ResidencyCounter:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F2C8_STRUCT;

// **** D0F0xBC_x1F2D0 Register Definition ****
// Address
#define D0F0xBC_x1F2D0_ADDRESS                                  0x1f2d0

// Type
#define D0F0xBC_x1F2D0_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F2D0_ActivityThreshold_OFFSET                 0
#define D0F0xBC_x1F2D0_ActivityThreshold_WIDTH                  8
#define D0F0xBC_x1F2D0_ActivityThreshold_MASK                   0xff
#define D0F0xBC_x1F2D0_Reserved_31_8_OFFSET                     8
#define D0F0xBC_x1F2D0_Reserved_31_8_WIDTH                      24
#define D0F0xBC_x1F2D0_Reserved_31_8_MASK                       0xffffff00

/// D0F0xBC_x1F2D0
typedef union {
  struct {                                                              ///<
    UINT32                                        ActivityThreshold:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F2D0_STRUCT;

// **** D0F0xBC_x1F2E0 Register Definition ****
// Address
#define D0F0xBC_x1F2E0_ADDRESS                                  0x1f2e0

// Type
#define D0F0xBC_x1F2E0_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F2E0_StateValid_OFFSET                        0
#define D0F0xBC_x1F2E0_StateValid_WIDTH                         1
#define D0F0xBC_x1F2E0_StateValid_MASK                          0x1
#define D0F0xBC_x1F2E0_Reserved_7_1_OFFSET                      1
#define D0F0xBC_x1F2E0_Reserved_7_1_WIDTH                       7
#define D0F0xBC_x1F2E0_Reserved_7_1_MASK                        0xfe
#define D0F0xBC_x1F2E0_LclkDivider_OFFSET                       8
#define D0F0xBC_x1F2E0_LclkDivider_WIDTH                        8
#define D0F0xBC_x1F2E0_LclkDivider_MASK                         0xff00
#define D0F0xBC_x1F2E0_VID_OFFSET                               16
#define D0F0xBC_x1F2E0_VID_WIDTH                                8
#define D0F0xBC_x1F2E0_VID_MASK                                 0xff0000
#define D0F0xBC_x1F2E0_LowVoltageReqThreshold_OFFSET            24
#define D0F0xBC_x1F2E0_LowVoltageReqThreshold_WIDTH             8
#define D0F0xBC_x1F2E0_LowVoltageReqThreshold_MASK              0xff000000

/// D0F0xBC_x1F2E0
typedef union {
  struct {                                                              ///<
    UINT32                                               StateValid:1 ; ///<
    UINT32                                             Reserved_7_1:7 ; ///<
    UINT32                                              LclkDivider:8 ; ///<
    UINT32                                                      VID:8 ; ///<
    UINT32                                   LowVoltageReqThreshold:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F2E0_STRUCT;

// **** D0F0xBC_x1F2E8 Register Definition ****
// Address
#define D0F0xBC_x1F2E8_ADDRESS                                  0x1f2e8

// Type
#define D0F0xBC_x1F2E8_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F2E8_HysteresisUp_OFFSET                      0
#define D0F0xBC_x1F2E8_HysteresisUp_WIDTH                       8
#define D0F0xBC_x1F2E8_HysteresisUp_MASK                        0xff
#define D0F0xBC_x1F2E8_HysteresisDown_OFFSET                    8
#define D0F0xBC_x1F2E8_HysteresisDown_WIDTH                     8
#define D0F0xBC_x1F2E8_HysteresisDown_MASK                      0xff00
#define D0F0xBC_x1F2E8_ResidencyCounter_OFFSET                  16
#define D0F0xBC_x1F2E8_ResidencyCounter_WIDTH                   16
#define D0F0xBC_x1F2E8_ResidencyCounter_MASK                    0xffff0000

/// D0F0xBC_x1F2E8
typedef union {
  struct {                                                              ///<
    UINT32                                             HysteresisUp:8 ; ///<
    UINT32                                           HysteresisDown:8 ; ///<
    UINT32                                         ResidencyCounter:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F2E8_STRUCT;

// **** D0F0xBC_x1F2F0 Register Definition ****
// Address
#define D0F0xBC_x1F2F0_ADDRESS                                  0x1f2f0

// Type
#define D0F0xBC_x1F2F0_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F2F0_ActivityThreshold_OFFSET                 0
#define D0F0xBC_x1F2F0_ActivityThreshold_WIDTH                  8
#define D0F0xBC_x1F2F0_ActivityThreshold_MASK                   0xff
#define D0F0xBC_x1F2F0_Reserved_31_8_OFFSET                     8
#define D0F0xBC_x1F2F0_Reserved_31_8_WIDTH                      24
#define D0F0xBC_x1F2F0_Reserved_31_8_MASK                       0xffffff00

/// D0F0xBC_x1F2F0
typedef union {
  struct {                                                              ///<
    UINT32                                        ActivityThreshold:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F2F0_STRUCT;

// **** D0F0xBC_x1F300 Register Definition ****
// Address
#define D0F0xBC_x1F300_ADDRESS                                  0x1f300

// Type
#define D0F0xBC_x1F300_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F300_LclkDpmEn_OFFSET                         0
#define D0F0xBC_x1F300_LclkDpmEn_WIDTH                          1
#define D0F0xBC_x1F300_LclkDpmEn_MASK                           0x1
#define D0F0xBC_x1F300_Reserved_7_1_OFFSET                      1
#define D0F0xBC_x1F300_Reserved_7_1_WIDTH                       7
#define D0F0xBC_x1F300_Reserved_7_1_MASK                        0xfe
#define D0F0xBC_x1F300_LclkDpmType_OFFSET                       8
#define D0F0xBC_x1F300_LclkDpmType_WIDTH                        1
#define D0F0xBC_x1F300_LclkDpmType_MASK                         0x100
#define D0F0xBC_x1F300_Reserved_15_9_OFFSET                     9
#define D0F0xBC_x1F300_Reserved_15_9_WIDTH                      7
#define D0F0xBC_x1F300_Reserved_15_9_MASK                       0xfe00
#define D0F0xBC_x1F300_LclkDpmBootState_OFFSET                  16
#define D0F0xBC_x1F300_LclkDpmBootState_WIDTH                   8
#define D0F0xBC_x1F300_LclkDpmBootState_MASK                    0xff0000
#define D0F0xBC_x1F300_VoltageChgEn_OFFSET                      24
#define D0F0xBC_x1F300_VoltageChgEn_WIDTH                       1
#define D0F0xBC_x1F300_VoltageChgEn_MASK                        0x1000000
#define D0F0xBC_x1F300_Reserved_31_25_OFFSET                    25
#define D0F0xBC_x1F300_Reserved_31_25_WIDTH                     7
#define D0F0xBC_x1F300_Reserved_31_25_MASK                      0xfe000000

/// D0F0xBC_x1F300
typedef union {
  struct {                                                              ///<
    UINT32                                                LclkDpmEn:1 ; ///<
    UINT32                                             Reserved_7_1:7 ; ///<
    UINT32                                              LclkDpmType:1 ; ///<
    UINT32                                            Reserved_15_9:7 ; ///<
    UINT32                                         LclkDpmBootState:8 ; ///<
    UINT32                                             VoltageChgEn:1 ; ///<
    UINT32                                           Reserved_31_25:7 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F300_STRUCT;

// **** D0F0xBC_x1F308 Register Definition ****
// Address
#define D0F0xBC_x1F308_ADDRESS                                  0x1f308

// Type
#define D0F0xBC_x1F308_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F308_LclkThermalThrottlingEn_OFFSET           0
#define D0F0xBC_x1F308_LclkThermalThrottlingEn_WIDTH            1
#define D0F0xBC_x1F308_LclkThermalThrottlingEn_MASK             0x1
#define D0F0xBC_x1F308_Reserved_7_1_OFFSET                      1
#define D0F0xBC_x1F308_Reserved_7_1_WIDTH                       7
#define D0F0xBC_x1F308_Reserved_7_1_MASK                        0xfe
#define D0F0xBC_x1F308_TemperatureSel_OFFSET                    8
#define D0F0xBC_x1F308_TemperatureSel_WIDTH                     1
#define D0F0xBC_x1F308_TemperatureSel_MASK                      0x100
#define D0F0xBC_x1F308_Reserved_15_9_OFFSET                     9
#define D0F0xBC_x1F308_Reserved_15_9_WIDTH                      7
#define D0F0xBC_x1F308_Reserved_15_9_MASK                       0xfe00
#define D0F0xBC_x1F308_LclkTtMode_OFFSET                        16
#define D0F0xBC_x1F308_LclkTtMode_WIDTH                         3
#define D0F0xBC_x1F308_LclkTtMode_MASK                          0x70000

/// D0F0xBC_x1F308
typedef union {
  struct {                                                              ///<
    UINT32                                  LclkThermalThrottlingEn:1 ; ///<
    UINT32                                             Reserved_7_1:7 ; ///<
    UINT32                                           TemperatureSel:1 ; ///<
    UINT32                                            Reserved_15_9:7 ; ///<
    UINT32                                               LclkTtMode:3 ; ///<
    UINT32                                           :13; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F308_STRUCT;

// **** D0F0xBC_x1F30C Register Definition ****
// Address
#define D0F0xBC_x1F30C_ADDRESS                                  0x1f30c

// Type
#define D0F0xBC_x1F30C_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F30C_LowThreshold_OFFSET                      0
#define D0F0xBC_x1F30C_LowThreshold_WIDTH                       16
#define D0F0xBC_x1F30C_LowThreshold_MASK                        0xffff
#define D0F0xBC_x1F30C_HighThreshold_OFFSET                     16
#define D0F0xBC_x1F30C_HighThreshold_WIDTH                      16
#define D0F0xBC_x1F30C_HighThreshold_MASK                       0xffff0000

/// D0F0xBC_x1F30C
typedef union {
  struct {                                                              ///<
    UINT32                                             LowThreshold:16; ///<
    UINT32                                            HighThreshold:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F30C_STRUCT;

// **** D0F0xBC_x1F380 Register Definition ****
// Address
#define D0F0xBC_x1F380_ADDRESS                                  0x1f380

// Type
#define D0F0xBC_x1F380_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F380_InterruptsEnabled_OFFSET                 0
#define D0F0xBC_x1F380_InterruptsEnabled_WIDTH                  1
#define D0F0xBC_x1F380_InterruptsEnabled_MASK                   0x1
#define D0F0xBC_x1F380_Reserved_23_1_OFFSET                     1
#define D0F0xBC_x1F380_Reserved_23_1_WIDTH                      23
#define D0F0xBC_x1F380_Reserved_23_1_MASK                       0xfffffe
#define D0F0xBC_x1F380_TestCount_OFFSET                         24
#define D0F0xBC_x1F380_TestCount_WIDTH                          8
#define D0F0xBC_x1F380_TestCount_MASK                           0xff000000

/// D0F0xBC_x1F380
typedef union {
  struct {                                                              ///<
    UINT32                                        InterruptsEnabled:1 ; ///<
    UINT32                                            Reserved_23_1:23; ///<
    UINT32                                                TestCount:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F380_STRUCT;

// **** D0F0xBC_x1F384 Register Definition ****
// Address
#define D0F0xBC_x1F384_ADDRESS                                  0x1f384

// Type
#define D0F0xBC_x1F384_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F384_FirmwareVid_OFFSET                       0
#define D0F0xBC_x1F384_FirmwareVid_WIDTH                        8
#define D0F0xBC_x1F384_FirmwareVid_MASK                         0xff
#define D0F0xBC_x1F384_Reserved_31_8_OFFSET                     8
#define D0F0xBC_x1F384_Reserved_31_8_WIDTH                      24
#define D0F0xBC_x1F384_Reserved_31_8_MASK                       0xffffff00

/// D0F0xBC_x1F384
typedef union {
  struct {                                                              ///<
    UINT32                                              FirmwareVid:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F384_STRUCT;

// **** D0F0xBC_x1F388 Register Definition ****
// Address
#define D0F0xBC_x1F388_ADDRESS                                  0x1f388

// Type
#define D0F0xBC_x1F388_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F388_CsrAddr_OFFSET                           0
#define D0F0xBC_x1F388_CsrAddr_WIDTH                            6
#define D0F0xBC_x1F388_CsrAddr_MASK                             0x3f
#define D0F0xBC_x1F388_TcenId_OFFSET                            6
#define D0F0xBC_x1F388_TcenId_WIDTH                             4
#define D0F0xBC_x1F388_TcenId_MASK                              0x3c0
#define D0F0xBC_x1F388_Reserved_31_10_OFFSET                    10
#define D0F0xBC_x1F388_Reserved_31_10_WIDTH                     22
#define D0F0xBC_x1F388_Reserved_31_10_MASK                      0xfffffc00

/// D0F0xBC_x1F388
typedef union {
  struct {                                                              ///<
    UINT32                                                  CsrAddr:6 ; ///<
    UINT32                                                   TcenId:4 ; ///<
    UINT32                                           Reserved_31_10:22; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F388_STRUCT;

// **** D0F0xBC_x1F39C Register Definition ****
// Address
#define D0F0xBC_x1F39C_ADDRESS                                  0x1f39c

// Type
#define D0F0xBC_x1F39C_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F39C_Rx_OFFSET                                0
#define D0F0xBC_x1F39C_Rx_WIDTH                                 1
#define D0F0xBC_x1F39C_Rx_MASK                                  0x1
#define D0F0xBC_x1F39C_Tx_OFFSET                                1
#define D0F0xBC_x1F39C_Tx_WIDTH                                 1
#define D0F0xBC_x1F39C_Tx_MASK                                  0x2
#define D0F0xBC_x1F39C_Core_OFFSET                              2
#define D0F0xBC_x1F39C_Core_WIDTH                               1
#define D0F0xBC_x1F39C_Core_MASK                                0x4
#define D0F0xBC_x1F39C_SkipPhy_OFFSET                           3
#define D0F0xBC_x1F39C_SkipPhy_WIDTH                            1
#define D0F0xBC_x1F39C_SkipPhy_MASK                             0x8
#define D0F0xBC_x1F39C_SkipCore_OFFSET                          4
#define D0F0xBC_x1F39C_SkipCore_WIDTH                           1
#define D0F0xBC_x1F39C_SkipCore_MASK                            0x10
#define D0F0xBC_x1F39C_Reserved_15_5_OFFSET                     5
#define D0F0xBC_x1F39C_Reserved_15_5_WIDTH                      11
#define D0F0xBC_x1F39C_Reserved_15_5_MASK                       0xffe0
#define D0F0xBC_x1F39C_LowerLaneID_OFFSET                       16
#define D0F0xBC_x1F39C_LowerLaneID_WIDTH                        8
#define D0F0xBC_x1F39C_LowerLaneID_MASK                         0xff0000
#define D0F0xBC_x1F39C_UpperLaneID_OFFSET                       24
#define D0F0xBC_x1F39C_UpperLaneID_WIDTH                        8
#define D0F0xBC_x1F39C_UpperLaneID_MASK                         0xff000000

/// D0F0xBC_x1F39C
typedef union {
  struct {                                                              ///<
    UINT32                                                       Rx:1 ; ///<
    UINT32                                                       Tx:1 ; ///<
    UINT32                                                     Core:1 ; ///<
    UINT32                                                  SkipPhy:1 ; ///<
    UINT32                                                 SkipCore:1 ; ///<
    UINT32                                            Reserved_15_5:11; ///<
    UINT32                                              LowerLaneID:8 ; ///<
    UINT32                                              UpperLaneID:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F39C_STRUCT;

// **** D0F0xBC_x1F3D8 Register Definition ****
// Address
#define D0F0xBC_x1F3D8_ADDRESS                                  0x1f3d8

// Type
#define D0F0xBC_x1F3D8_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F3D8_LoadLineTrim3_OFFSET                     0
#define D0F0xBC_x1F3D8_LoadLineTrim3_WIDTH                      8
#define D0F0xBC_x1F3D8_LoadLineTrim3_MASK                       0xff
#define D0F0xBC_x1F3D8_LoadLineTrim2_OFFSET                     8
#define D0F0xBC_x1F3D8_LoadLineTrim2_WIDTH                      8
#define D0F0xBC_x1F3D8_LoadLineTrim2_MASK                       0xff00
#define D0F0xBC_x1F3D8_LoadLineTrim1_OFFSET                     16
#define D0F0xBC_x1F3D8_LoadLineTrim1_WIDTH                      8
#define D0F0xBC_x1F3D8_LoadLineTrim1_MASK                       0xff0000
#define D0F0xBC_x1F3D8_LoadLineTrim0_OFFSET                     24
#define D0F0xBC_x1F3D8_LoadLineTrim0_WIDTH                      8
#define D0F0xBC_x1F3D8_LoadLineTrim0_MASK                       0xff000000

/// D0F0xBC_x1F3D8
typedef union {
  struct {                                                              ///<
    UINT32                                            LoadLineTrim3:8 ; ///<
    UINT32                                            LoadLineTrim2:8 ; ///<
    UINT32                                            LoadLineTrim1:8 ; ///<
    UINT32                                            LoadLineTrim0:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F3D8_STRUCT;

// **** D0F0xBC_x1F3DC Register Definition ****
// Address
#define D0F0xBC_x1F3DC_ADDRESS                                  0x1f3dc

// Type
#define D0F0xBC_x1F3DC_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F3DC_LoadLineTrim7_OFFSET                     0
#define D0F0xBC_x1F3DC_LoadLineTrim7_WIDTH                      8
#define D0F0xBC_x1F3DC_LoadLineTrim7_MASK                       0xff
#define D0F0xBC_x1F3DC_LoadLineTrim6_OFFSET                     8
#define D0F0xBC_x1F3DC_LoadLineTrim6_WIDTH                      8
#define D0F0xBC_x1F3DC_LoadLineTrim6_MASK                       0xff00
#define D0F0xBC_x1F3DC_LoadLineTrim5_OFFSET                     16
#define D0F0xBC_x1F3DC_LoadLineTrim5_WIDTH                      8
#define D0F0xBC_x1F3DC_LoadLineTrim5_MASK                       0xff0000
#define D0F0xBC_x1F3DC_LoadLineTrim4_OFFSET                     24
#define D0F0xBC_x1F3DC_LoadLineTrim4_WIDTH                      8
#define D0F0xBC_x1F3DC_LoadLineTrim4_MASK                       0xff000000

/// D0F0xBC_x1F3DC
typedef union {
  struct {                                                              ///<
    UINT32                                            LoadLineTrim7:8 ; ///<
    UINT32                                            LoadLineTrim6:8 ; ///<
    UINT32                                            LoadLineTrim5:8 ; ///<
    UINT32                                            LoadLineTrim4:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F3DC_STRUCT;

// **** D0F0xBC_x1F3F8 Register Definition ****
// Address
#define D0F0xBC_x1F3F8_ADDRESS                                  0x1f3f8

// Type
#define D0F0xBC_x1F3F8_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F3F8_SviInitLoadLineVdd_OFFSET                0
#define D0F0xBC_x1F3F8_SviInitLoadLineVdd_WIDTH                 8
#define D0F0xBC_x1F3F8_SviInitLoadLineVdd_MASK                  0xff
#define D0F0xBC_x1F3F8_SviInitLoadLineVddNB_OFFSET              8
#define D0F0xBC_x1F3F8_SviInitLoadLineVddNB_WIDTH               8
#define D0F0xBC_x1F3F8_SviInitLoadLineVddNB_MASK                0xff00
#define D0F0xBC_x1F3F8_SviTrimValueVdd_OFFSET                   16
#define D0F0xBC_x1F3F8_SviTrimValueVdd_WIDTH                    8
#define D0F0xBC_x1F3F8_SviTrimValueVdd_MASK                     0xff0000
#define D0F0xBC_x1F3F8_SviTrimValueVddNB_OFFSET                 24
#define D0F0xBC_x1F3F8_SviTrimValueVddNB_WIDTH                  8
#define D0F0xBC_x1F3F8_SviTrimValueVddNB_MASK                   0xff000000

/// D0F0xBC_x1F3F8
typedef union {
  struct {                                                              ///<
    UINT32                                       SviInitLoadLineVdd:8 ; ///<
    UINT32                                     SviInitLoadLineVddNB:8 ; ///<
    UINT32                                          SviTrimValueVdd:8 ; ///<
    UINT32                                        SviTrimValueVddNB:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F3F8_STRUCT;

// **** D0F0xBC_x1F3FC Register Definition ****
// Address
#define D0F0xBC_x1F3FC_ADDRESS                                  0x1f3fc

// Type
#define D0F0xBC_x1F3FC_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F3FC_SviVidStepBase_OFFSET                    0
#define D0F0xBC_x1F3FC_SviVidStepBase_WIDTH                     16
#define D0F0xBC_x1F3FC_SviVidStepBase_MASK                      0xffff
#define D0F0xBC_x1F3FC_SviVidStep_OFFSET                        16
#define D0F0xBC_x1F3FC_SviVidStep_WIDTH                         16
#define D0F0xBC_x1F3FC_SviVidStep_MASK                          0xffff0000

/// D0F0xBC_x1F3FC
typedef union {
  struct {                                                              ///<
    UINT32                                           SviVidStepBase:16; ///<
    UINT32                                               SviVidStep:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F3FC_STRUCT;

// **** D0F0xBC_x1F400 Register Definition ****
// Address
#define D0F0xBC_x1F400_ADDRESS                                  0x1f400

// Type
#define D0F0xBC_x1F400_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F400_SviLoadLineOffsetVdd_OFFSET              0
#define D0F0xBC_x1F400_SviLoadLineOffsetVdd_WIDTH               8
#define D0F0xBC_x1F400_SviLoadLineOffsetVdd_MASK                0xff
#define D0F0xBC_x1F400_SviLoadLineOffsetVddNB_OFFSET            8
#define D0F0xBC_x1F400_SviLoadLineOffsetVddNB_WIDTH             8
#define D0F0xBC_x1F400_SviLoadLineOffsetVddNB_MASK              0xff00
#define D0F0xBC_x1F400_PstateMax_OFFSET                         16
#define D0F0xBC_x1F400_PstateMax_WIDTH                          8
#define D0F0xBC_x1F400_PstateMax_MASK                           0xff0000
#define D0F0xBC_x1F400_Reserved_31_24_OFFSET                    24
#define D0F0xBC_x1F400_Reserved_31_24_WIDTH                     8
#define D0F0xBC_x1F400_Reserved_31_24_MASK                      0xff000000

/// D0F0xBC_x1F400
typedef union {
  struct {                                                              ///<
    UINT32                                     SviLoadLineOffsetVdd:8 ; ///<
    UINT32                                   SviLoadLineOffsetVddNB:8 ; ///<
    UINT32                                                PstateMax:8 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F400_STRUCT;

// **** D0F0xBC_x1F404 Register Definition ****
// Address
#define D0F0xBC_x1F404_ADDRESS                                  0x1f404

// Type
#define D0F0xBC_x1F404_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F404_LoadLineOffset3_OFFSET                   0
#define D0F0xBC_x1F404_LoadLineOffset3_WIDTH                    8
#define D0F0xBC_x1F404_LoadLineOffset3_MASK                     0xff
#define D0F0xBC_x1F404_LoadLineOffset2_OFFSET                   8
#define D0F0xBC_x1F404_LoadLineOffset2_WIDTH                    8
#define D0F0xBC_x1F404_LoadLineOffset2_MASK                     0xff00
#define D0F0xBC_x1F404_LoadLineOffset1_OFFSET                   16
#define D0F0xBC_x1F404_LoadLineOffset1_WIDTH                    8
#define D0F0xBC_x1F404_LoadLineOffset1_MASK                     0xff0000
#define D0F0xBC_x1F404_LoadLineOffset0_OFFSET                   24
#define D0F0xBC_x1F404_LoadLineOffset0_WIDTH                    8
#define D0F0xBC_x1F404_LoadLineOffset0_MASK                     0xff000000

/// D0F0xBC_x1F404
typedef union {
  struct {                                                              ///<
    UINT32                                          LoadLineOffset3:8 ; ///<
    UINT32                                          LoadLineOffset2:8 ; ///<
    UINT32                                          LoadLineOffset1:8 ; ///<
    UINT32                                          LoadLineOffset0:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F404_STRUCT;

// **** D0F0xBC_x1F428 Register Definition ****
// Address
#define D0F0xBC_x1F428_ADDRESS                                  0x1f428

// Type
#define D0F0xBC_x1F428_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F428_EnableVpcAccumulators_OFFSET             0
#define D0F0xBC_x1F428_EnableVpcAccumulators_WIDTH              1
#define D0F0xBC_x1F428_EnableVpcAccumulators_MASK               0x1
#define D0F0xBC_x1F428_EnableBapm_OFFSET                        1
#define D0F0xBC_x1F428_EnableBapm_WIDTH                         1
#define D0F0xBC_x1F428_EnableBapm_MASK                          0x2
#define D0F0xBC_x1F428_EnableTdcLimit_OFFSET                    2
#define D0F0xBC_x1F428_EnableTdcLimit_WIDTH                     1
#define D0F0xBC_x1F428_EnableTdcLimit_MASK                      0x4
#define D0F0xBC_x1F428_EnableLpmx_OFFSET                        3
#define D0F0xBC_x1F428_EnableLpmx_WIDTH                         1
#define D0F0xBC_x1F428_EnableLpmx_MASK                          0x8
#define D0F0xBC_x1F428_EnableHtcLimit_OFFSET                    4
#define D0F0xBC_x1F428_EnableHtcLimit_WIDTH                     1
#define D0F0xBC_x1F428_EnableHtcLimit_MASK                      0x10
#define D0F0xBC_x1F428_EnableNbDpm_OFFSET                       5
#define D0F0xBC_x1F428_EnableNbDpm_WIDTH                        1
#define D0F0xBC_x1F428_EnableNbDpm_MASK                         0x20
#define D0F0xBC_x1F428_EnableLoadline_OFFSET                    6
#define D0F0xBC_x1F428_EnableLoadline_WIDTH                     1
#define D0F0xBC_x1F428_EnableLoadline_MASK                      0x40
#define D0F0xBC_x1F428_Reserved_15_7_OFFSET                     7
#define D0F0xBC_x1F428_Reserved_15_7_WIDTH                      9
#define D0F0xBC_x1F428_Reserved_15_7_MASK                       0xff80
#define D0F0xBC_x1F428_Reserved_23_20_OFFSET                    20
#define D0F0xBC_x1F428_Reserved_23_20_WIDTH                     4
#define D0F0xBC_x1F428_Reserved_23_20_MASK                      0xf00000
#define D0F0xBC_x1F428_PstateAllCpusIdle_OFFSET                 24
#define D0F0xBC_x1F428_PstateAllCpusIdle_WIDTH                  3
#define D0F0xBC_x1F428_PstateAllCpusIdle_MASK                   0x7000000
#define D0F0xBC_x1F428_NbPstateAllCpusIdle_OFFSET               27
#define D0F0xBC_x1F428_NbPstateAllCpusIdle_WIDTH                1
#define D0F0xBC_x1F428_NbPstateAllCpusIdle_MASK                 0x8000000
#define D0F0xBC_x1F428_BapmCoeffOverride_OFFSET                 28
#define D0F0xBC_x1F428_BapmCoeffOverride_WIDTH                  1
#define D0F0xBC_x1F428_BapmCoeffOverride_MASK                   0x10000000
#define D0F0xBC_x1F428_SviMode_OFFSET                           29
#define D0F0xBC_x1F428_SviMode_WIDTH                            1
#define D0F0xBC_x1F428_SviMode_MASK                             0x20000000
#define D0F0xBC_x1F428_Reserved_31_30_OFFSET                    30
#define D0F0xBC_x1F428_Reserved_31_30_WIDTH                     2
#define D0F0xBC_x1F428_Reserved_31_30_MASK                      0xc0000000

/// D0F0xBC_x1F428
typedef union {
  struct {                                                              ///<
    UINT32                                    EnableVpcAccumulators:1 ; ///<
    UINT32                                               EnableBapm:1 ; ///<
    UINT32                                           EnableTdcLimit:1 ; ///<
    UINT32                                               EnableLpmx:1 ; ///<
    UINT32               field_4:1;
    UINT32                                              EnableNbDpm:1 ; ///<
    UINT32                                           EnableLoadline:1 ; ///<
    UINT32                                            Reserved_15_7:9 ; ///<
    UINT32                                       :1 ; ///<
    UINT32                                                  :1 ; ///<
    UINT32                                                 :1 ; ///<
    UINT32                                 line180        :1 ; ///<
    UINT32                                           Reserved_23_20:4 ; ///<
    UINT32                                        PstateAllCpusIdle:3 ; ///<
    UINT32                                      NbPstateAllCpusIdle:1 ; ///<
    UINT32                                        BapmCoeffOverride:1 ; ///<
    UINT32                                                  SviMode:1 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F428_STRUCT;

// **** D0F0xBC_x1F460 Register Definition ****
// Address
#define D0F0xBC_x1F460_ADDRESS                                  0x1f460

// Type
#define D0F0xBC_x1F460_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F460_LclkDpm_OFFSET                           0
#define D0F0xBC_x1F460_LclkDpm_WIDTH                            8
#define D0F0xBC_x1F460_LclkDpm_MASK                             0xff
#define D0F0xBC_x1F460_ThermalCntl_OFFSET                       8
#define D0F0xBC_x1F460_ThermalCntl_WIDTH                        8
#define D0F0xBC_x1F460_ThermalCntl_MASK                         0xff00
#define D0F0xBC_x1F460_VoltageCntl_OFFSET                       16
#define D0F0xBC_x1F460_VoltageCntl_WIDTH                        8
#define D0F0xBC_x1F460_VoltageCntl_MASK                         0xff0000
#define D0F0xBC_x1F460_Loadline_OFFSET                          24
#define D0F0xBC_x1F460_Loadline_WIDTH                           8
#define D0F0xBC_x1F460_Loadline_MASK                            0xff000000

/// D0F0xBC_x1F460
typedef union {
  struct {                                                              ///<
    UINT32                                                  LclkDpm:8 ; ///<
    UINT32                                              ThermalCntl:8 ; ///<
    UINT32                                              VoltageCntl:8 ; ///<
    UINT32                                                 Loadline:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F460_STRUCT;

// **** D0F0xBC_x1F464 Register Definition ****
// Address
#define D0F0xBC_x1F464_ADDRESS                                  0x1f464

// Type
#define D0F0xBC_x1F464_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F464_SclkDpm_OFFSET                           0
#define D0F0xBC_x1F464_SclkDpm_WIDTH                            8
#define D0F0xBC_x1F464_SclkDpm_MASK                             0xff
#define D0F0xBC_x1F464_StaticSimdPgCntl_OFFSET                  8
#define D0F0xBC_x1F464_StaticSimdPgCntl_WIDTH                   8
#define D0F0xBC_x1F464_StaticSimdPgCntl_MASK                    0xff00
#define D0F0xBC_x1F464_DynSimdPgCntl_OFFSET                     16
#define D0F0xBC_x1F464_DynSimdPgCntl_WIDTH                      8
#define D0F0xBC_x1F464_DynSimdPgCntl_MASK                       0xff0000
#define D0F0xBC_x1F464_TdpCntl_OFFSET                           24
#define D0F0xBC_x1F464_TdpCntl_WIDTH                            8
#define D0F0xBC_x1F464_TdpCntl_MASK                             0xff000000

/// D0F0xBC_x1F464
typedef union {
  struct {                                                              ///<
    UINT32                                                  SclkDpm:8 ; ///<
    UINT32                                         StaticSimdPgCntl:8 ; ///<
    UINT32                                            DynSimdPgCntl:8 ; ///<
    UINT32                                                  TdpCntl:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F464_STRUCT;

// **** D0F0xBC_x1F468 Register Definition ****
// Address
#define D0F0xBC_x1F468_ADDRESS                                  0x1f468

// Type
#define D0F0xBC_x1F468_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F468_TimerPeriod_OFFSET                       0
#define D0F0xBC_x1F468_TimerPeriod_WIDTH                        32
#define D0F0xBC_x1F468_TimerPeriod_MASK                         0xffffffff

/// D0F0xBC_x1F468
typedef union {
  struct {                                                              ///<
    UINT32                                              TimerPeriod:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F468_STRUCT;

// **** D0F0xBC_x1F46C Register Definition ****
// Address
#define D0F0xBC_x1F46C_ADDRESS                                  0x1f46c

// Type
#define D0F0xBC_x1F46C_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F46C_VpcPeriod_OFFSET                         0
#define D0F0xBC_x1F46C_VpcPeriod_WIDTH                          16
#define D0F0xBC_x1F46C_VpcPeriod_MASK                           0xffff
#define D0F0xBC_x1F46C_BapmPeriod_OFFSET                        16
#define D0F0xBC_x1F46C_BapmPeriod_WIDTH                         8
#define D0F0xBC_x1F46C_BapmPeriod_MASK                          0xff0000
#define D0F0xBC_x1F46C_LpmxPeriod_OFFSET                        24
#define D0F0xBC_x1F46C_LpmxPeriod_WIDTH                         8
#define D0F0xBC_x1F46C_LpmxPeriod_MASK                          0xff000000

/// D0F0xBC_x1F46C
typedef union {
  struct {                                                              ///<
    UINT32                                                VpcPeriod:16; ///<
    UINT32                                               BapmPeriod:8 ; ///<
    UINT32                                               LpmxPeriod:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F46C_STRUCT;

// **** D0F0xBC_x1F5F8 Register Definition ****
// Address
#define D0F0xBC_x1F5F8_ADDRESS                                  0x1f5f8

// Type
#define D0F0xBC_x1F5F8_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F5F8_Dpm0PgNbPsLo_OFFSET                      0
#define D0F0xBC_x1F5F8_Dpm0PgNbPsLo_WIDTH                       2
#define D0F0xBC_x1F5F8_Dpm0PgNbPsLo_MASK                        0x3
#define D0F0xBC_x1F5F8_Dpm0PgNbPsHi_OFFSET                      2
#define D0F0xBC_x1F5F8_Dpm0PgNbPsHi_WIDTH                       2
#define D0F0xBC_x1F5F8_Dpm0PgNbPsHi_MASK                        0xc
#define D0F0xBC_x1F5F8_DpmXNbPsLo_OFFSET                        4
#define D0F0xBC_x1F5F8_DpmXNbPsLo_WIDTH                         2
#define D0F0xBC_x1F5F8_DpmXNbPsLo_MASK                          0x30
#define D0F0xBC_x1F5F8_DpmXNbPsHi_OFFSET                        6
#define D0F0xBC_x1F5F8_DpmXNbPsHi_WIDTH                         2
#define D0F0xBC_x1F5F8_DpmXNbPsHi_MASK                          0xc0
#define D0F0xBC_x1F5F8_Hysteresis_OFFSET                        8
#define D0F0xBC_x1F5F8_Hysteresis_WIDTH                         8
#define D0F0xBC_x1F5F8_Hysteresis_MASK                          0xff00
#define D0F0xBC_x1F5F8_SkipPG_OFFSET                            16
#define D0F0xBC_x1F5F8_SkipPG_WIDTH                             1
#define D0F0xBC_x1F5F8_SkipPG_MASK                              0x10000
#define D0F0xBC_x1F5F8_SkipDPM0_OFFSET                          17
#define D0F0xBC_x1F5F8_SkipDPM0_WIDTH                           1
#define D0F0xBC_x1F5F8_SkipDPM0_MASK                            0x20000
#define D0F0xBC_x1F5F8_Reserved_21_18_OFFSET                    18
#define D0F0xBC_x1F5F8_Reserved_21_18_WIDTH                     4
#define D0F0xBC_x1F5F8_Reserved_21_18_MASK                      0x3c0000
#define D0F0xBC_x1F5F8_EnableNbPsi1_OFFSET                      22
#define D0F0xBC_x1F5F8_EnableNbPsi1_WIDTH                       1
#define D0F0xBC_x1F5F8_EnableNbPsi1_MASK                        0x400000
#define D0F0xBC_x1F5F8_EnableDpmPstatePoll_OFFSET               23
#define D0F0xBC_x1F5F8_EnableDpmPstatePoll_WIDTH                1
#define D0F0xBC_x1F5F8_EnableDpmPstatePoll_MASK                 0x800000
#define D0F0xBC_x1F5F8_Reserved_31_24_OFFSET                    24
#define D0F0xBC_x1F5F8_Reserved_31_24_WIDTH                     8
#define D0F0xBC_x1F5F8_Reserved_31_24_MASK                      0xff000000

/// D0F0xBC_x1F5F8
typedef union {
  struct {                                                              ///<
    UINT32                                             Dpm0PgNbPsLo:2 ; ///<
    UINT32                                             Dpm0PgNbPsHi:2 ; ///<
    UINT32                                               DpmXNbPsLo:2 ; ///<
    UINT32                                               DpmXNbPsHi:2 ; ///<
    UINT32                                               Hysteresis:8 ; ///<
    UINT32                                                   SkipPG:1 ; ///<
    UINT32                                                 SkipDPM0:1 ; ///<
    UINT32                                           Reserved_21_18:4 ; ///<
    UINT32                                             EnableNbPsi1:1 ; ///<
    UINT32                                      EnableDpmPstatePoll:1 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F5F8_STRUCT;

// **** D0F0xBC_x1F5FC Register Definition ****
// Address
#define D0F0xBC_x1F5FC_ADDRESS                                  0x1f5fc

// Type
#define D0F0xBC_x1F5FC_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F5FC_ChangeInProgress_OFFSET                  0
#define D0F0xBC_x1F5FC_ChangeInProgress_WIDTH                   1
#define D0F0xBC_x1F5FC_ChangeInProgress_MASK                    0x1
#define D0F0xBC_x1F5FC_CurrentPstatePair_OFFSET                 1
#define D0F0xBC_x1F5FC_CurrentPstatePair_WIDTH                  1
#define D0F0xBC_x1F5FC_CurrentPstatePair_MASK                   0x2
#define D0F0xBC_x1F5FC_Reserved_7_2_OFFSET                      2
#define D0F0xBC_x1F5FC_Reserved_7_2_WIDTH                       6
#define D0F0xBC_x1F5FC_Reserved_7_2_MASK                        0xfc
#define D0F0xBC_x1F5FC_PSI1Sts_OFFSET                           8
#define D0F0xBC_x1F5FC_PSI1Sts_WIDTH                            1
#define D0F0xBC_x1F5FC_PSI1Sts_MASK                             0x100
#define D0F0xBC_x1F5FC_Reserved_31_9_OFFSET                     9
#define D0F0xBC_x1F5FC_Reserved_31_9_WIDTH                      23
#define D0F0xBC_x1F5FC_Reserved_31_9_MASK                       0xfffffe00

/// D0F0xBC_x1F5FC
typedef union {
  struct {                                                              ///<
    UINT32                                         ChangeInProgress:1 ; ///<
    UINT32                                        CurrentPstatePair:1 ; ///<
    UINT32                                             Reserved_7_2:6 ; ///<
    UINT32                                                  PSI1Sts:1 ; ///<
    UINT32                                            Reserved_31_9:23; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F5FC_STRUCT;

// **** D0F0xBC_x1F610 Register Definition ****
// Address
#define D0F0xBC_x1F610_ADDRESS                                  0x1f610

// Type
#define D0F0xBC_x1F610_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F610_RESERVED_OFFSET                          0
#define D0F0xBC_x1F610_RESERVED_WIDTH                           8
#define D0F0xBC_x1F610_RESERVED_MASK                            0xff
#define D0F0xBC_x1F610_GFXH_OFFSET                              8
#define D0F0xBC_x1F610_GFXH_WIDTH                               8
#define D0F0xBC_x1F610_GFXH_MASK                                0xff00
#define D0F0xBC_x1F610_GFXL_OFFSET                              16
#define D0F0xBC_x1F610_GFXL_WIDTH                               8
#define D0F0xBC_x1F610_GFXL_MASK                                0xff0000
#define D0F0xBC_x1F610_GPPSB_OFFSET                             24
#define D0F0xBC_x1F610_GPPSB_WIDTH                              8
#define D0F0xBC_x1F610_GPPSB_MASK                               0xff000000

/// D0F0xBC_x1F610
typedef union {
  struct {                                                              ///<
    UINT32                                                 RESERVED:8 ; ///<
    UINT32                                                     GFXH:8 ; ///<
    UINT32                                                     GFXL:8 ; ///<
    UINT32                                                    GPPSB:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F610_STRUCT;


// **** D0F0xBC_x1F628 Register Definition ****
// Address
#define D0F0xBC_x1F628_ADDRESS                                  0x1f628

// Type
#define D0F0xBC_x1F628_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F628_Reserved_15_0_OFFSET                     0
#define D0F0xBC_x1F628_Reserved_15_0_WIDTH                      16
#define D0F0xBC_x1F628_Reserved_15_0_MASK                       0xffff
#define D0F0xBC_x1F628_HtcActivePstateLimit_OFFSET              16
#define D0F0xBC_x1F628_HtcActivePstateLimit_WIDTH               8
#define D0F0xBC_x1F628_HtcActivePstateLimit_MASK                0xff0000
#define D0F0xBC_x1F628_Reserved_31_24_OFFSET                    24
#define D0F0xBC_x1F628_Reserved_31_24_WIDTH                     8
#define D0F0xBC_x1F628_Reserved_31_24_MASK                      0xff000000

/// D0F0xBC_x1F628
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_15_0:16;///<
    UINT32                                      HtcActivePstateLimit:8; ///<
    UINT32                                            Reserved_31_24:8; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F628_STRUCT;

// **** D0F0xBC_x1F62C Register Definition ****
// Address
#define D0F0xBC_x1F62C_ADDRESS                                  0x1f62c

// Type
#define D0F0xBC_x1F62C_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F62C_Idd_OFFSET                               0
#define D0F0xBC_x1F62C_Idd_WIDTH                                16
#define D0F0xBC_x1F62C_Idd_MASK                                 0xffff
#define D0F0xBC_x1F62C_Iddnb_OFFSET                             16
#define D0F0xBC_x1F62C_Iddnb_WIDTH                              16
#define D0F0xBC_x1F62C_Iddnb_MASK                               0xffff0000

/// D0F0xBC_x1F62C
typedef union {
  struct {                                                              ///<
    UINT32                                                      Idd:16; ///<
    UINT32                                                    Iddnb:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F62C_STRUCT;

// **** D0F0xBC_x1F638 Register Definition ****
// Address
#define D0F0xBC_x1F638_ADDRESS                                  0x1f638

// Type
#define D0F0xBC_x1F638_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F638_TdcPeriod_OFFSET                         0
#define D0F0xBC_x1F638_TdcPeriod_WIDTH                          8
#define D0F0xBC_x1F638_TdcPeriod_MASK                           0xff
#define D0F0xBC_x1F638_HtcPeriod_OFFSET                         8
#define D0F0xBC_x1F638_HtcPeriod_WIDTH                          8
#define D0F0xBC_x1F638_HtcPeriod_MASK                           0xff00
#define D0F0xBC_x1F638_NbdpmPeriod_OFFSET                       16
#define D0F0xBC_x1F638_NbdpmPeriod_WIDTH                        8
#define D0F0xBC_x1F638_NbdpmPeriod_MASK                         0xff0000
#define D0F0xBC_x1F638_PginterlockPeriod_OFFSET                 24
#define D0F0xBC_x1F638_PginterlockPeriod_WIDTH                  8
#define D0F0xBC_x1F638_PginterlockPeriod_MASK                   0xff000000

/// D0F0xBC_x1F638
typedef union {
  struct {                                                              ///<
    UINT32                                                TdcPeriod:8 ; ///<
    UINT32                                                HtcPeriod:8 ; ///<
    UINT32                                              NbdpmPeriod:8 ; ///<
    UINT32                                        PginterlockPeriod:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F638_STRUCT;

// **** D0F0xBC_x1F6E4 Register Definition ****
// Address
#define D0F0xBC_x1F6E4_ADDRESS                                  0x1f6e4

// Type
#define D0F0xBC_x1F6E4_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F6E4_DdrVoltFloor_OFFSET                      0
#define D0F0xBC_x1F6E4_DdrVoltFloor_WIDTH                       8
#define D0F0xBC_x1F6E4_DdrVoltFloor_MASK                        0xff
#define D0F0xBC_x1F6E4_BapmDdrVoltFloor_OFFSET                  8
#define D0F0xBC_x1F6E4_BapmDdrVoltFloor_WIDTH                   8
#define D0F0xBC_x1F6E4_BapmDdrVoltFloor_MASK                    0xff00
#define D0F0xBC_x1F6E4_Reserved_OFFSET                          16
#define D0F0xBC_x1F6E4_Reserved_WIDTH                           16
#define D0F0xBC_x1F6E4_Reserved_MASK                            0xffff0000

/// D0F0xBC_x1F6E4
typedef union {
  struct {                                                              ///<
    UINT32                                             DdrVoltFloor:8 ; ///<
    UINT32                                         BapmDdrVoltFloor:8 ; ///<
    UINT32                                                 Reserved:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F6E4_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32          ex996_0:8 ;
    UINT32          ex996_1:8 ;
    UINT32          ex996_2:8 ;
    UINT32          ex996_3:8 ;
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex996_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32           ex997_0:16;
    UINT32           ex997_1:16;
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex997_STRUCT;

// **** D0F0xBC_x1F6B4 Register Definition ****
// Address
#define D0F0xBC_x1F6B4_ADDRESS                                  0x1f6b4

// Type
#define D0F0xBC_x1F6B4_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F6B4_TjOffset_OFFSET                          0
#define D0F0xBC_x1F6B4_TjOffset_WIDTH                           8
#define D0F0xBC_x1F6B4_TjOffset_MASK                            0xff
#define D0F0xBC_x1F6B4_Reserved_OFFSET                          8
#define D0F0xBC_x1F6B4_Reserved_WIDTH                           24
#define D0F0xBC_x1F6B4_Reserved_MASK                            0xffffff00

/// D0F0xBC_x1F6B4
typedef union {
  struct {                                                              ///<
    UINT32                                                 TjOffset:8 ; ///<
    UINT32                                                 Reserved:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F6B4_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32           ex998_0:16;
    UINT32           ex998_1:8;
    UINT32           ex998_2:8;
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex998_STRUCT;

// **** D0F0xBC_x1F844 Register Definition ****
// Address
#define D0F0xBC_x1F844_ADDRESS                                  0x1f844

// Type
#define D0F0xBC_x1F844_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F844_CsrAddr_OFFSET                           0
#define D0F0xBC_x1F844_CsrAddr_WIDTH                            6
#define D0F0xBC_x1F844_CsrAddr_MASK                             0x3f
#define D0F0xBC_x1F844_TcenId_OFFSET                            6
#define D0F0xBC_x1F844_TcenId_WIDTH                             4
#define D0F0xBC_x1F844_TcenId_MASK                              0x3c0
#define D0F0xBC_x1F844_Reserved_31_10_OFFSET                    10
#define D0F0xBC_x1F844_Reserved_31_10_WIDTH                     22
#define D0F0xBC_x1F844_Reserved_31_10_MASK                      0xfffffc00

/// D0F0xBC_x1F844
typedef union {
  struct {                                                              ///<
    UINT32                                                   CsrAddr:6; ///<
    UINT32                                                    TcenId:4; ///<
    UINT32                                           Reserved_31_10:22; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F844_STRUCT;

// **** D0F0xBC_x1F848 Register Definition ****
// Address
#define D0F0xBC_x1F848_ADDRESS                                  0x1f848

// Type
#define D0F0xBC_x1F848_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F848_CsrAddr_OFFSET                           0
#define D0F0xBC_x1F848_CsrAddr_WIDTH                            6
#define D0F0xBC_x1F848_CsrAddr_MASK                             0x3f
#define D0F0xBC_x1F848_TcenId_OFFSET                            6
#define D0F0xBC_x1F848_TcenId_WIDTH                             4
#define D0F0xBC_x1F848_TcenId_MASK                              0x3c0
#define D0F0xBC_x1F848_Reserved_31_10_OFFSET                    10
#define D0F0xBC_x1F848_Reserved_31_10_WIDTH                     22
#define D0F0xBC_x1F848_Reserved_31_10_MASK                      0xfffffc00

/// D0F0xBC_x1F848
typedef union {
  struct {                                                              ///<
    UINT32                                                   CsrAddr:6; ///<
    UINT32                                                    TcenId:4; ///<
    UINT32                                           Reserved_31_10:22; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F848_STRUCT;

// **** D0F0xBC_x1F84C Register Definition ****
// Address
#define D0F0xBC_x1F84C_ADDRESS                                  0x1f84c

// Type
#define D0F0xBC_x1F84C_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F84C_CsrAddr_OFFSET                           0
#define D0F0xBC_x1F84C_CsrAddr_WIDTH                            6
#define D0F0xBC_x1F84C_CsrAddr_MASK                             0x3f
#define D0F0xBC_x1F84C_TcenId_OFFSET                            6
#define D0F0xBC_x1F84C_TcenId_WIDTH                             4
#define D0F0xBC_x1F84C_TcenId_MASK                              0x3c0
#define D0F0xBC_x1F84C_Reserved_31_10_OFFSET                    10
#define D0F0xBC_x1F84C_Reserved_31_10_WIDTH                     22
#define D0F0xBC_x1F84C_Reserved_31_10_MASK                      0xfffffc00

/// D0F0xBC_x1F84C
typedef union {
  struct {                                                              ///<
    UINT32                                                   CsrAddr:6; ///<
    UINT32                                                    TcenId:4; ///<
    UINT32                                           Reserved_31_10:22; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F84C_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32           ex999_0:8;
    UINT32           ex999_1:8;
    UINT32           ex999_2:8;
    UINT32           ex999_3:8;
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex999_STRUCT;

// **** D0F0xBC_x1F870 Register Definition ****
// Address
#define D0F0xBC_x1F870_ADDRESS                                  0x1f870

// Type
#define D0F0xBC_x1F870_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F870_AmbientTempBase_OFFSET                   0
#define D0F0xBC_x1F870_AmbientTempBase_WIDTH                    8
#define D0F0xBC_x1F870_AmbientTempBase_MASK                     0xff
#define D0F0xBC_x1F870_BAPMTI_TjOffset_2_OFFSET                 8
#define D0F0xBC_x1F870_BAPMTI_TjOffset_2_WIDTH                  8
#define D0F0xBC_x1F870_BAPMTI_TjOffset_2_MASK                   0xff00
#define D0F0xBC_x1F870_BAPMTI_TjOffset_1_OFFSET                 16
#define D0F0xBC_x1F870_BAPMTI_TjOffset_1_WIDTH                  8
#define D0F0xBC_x1F870_BAPMTI_TjOffset_1_MASK                   0xff0000
#define D0F0xBC_x1F870_BAPMTI_TjOffset_0_OFFSET                 24
#define D0F0xBC_x1F870_BAPMTI_TjOffset_0_WIDTH                  8
#define D0F0xBC_x1F870_BAPMTI_TjOffset_0_MASK                   0xff000000

/// D0F0xBC_x1F870
typedef union {
  struct {                                                              ///<
    UINT32                                           AmbientTempBase:8; ///<
    UINT32                                          BAPMTI_TjOffset_2:8; ///<
    UINT32                                          BAPMTI_TjOffset_1:8; ///<
    UINT32                                          BAPMTI_TjOffset_0:8; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F870_STRUCT;

/// D0F0xBC_x1F878
typedef union {
  struct {                                                              ///<
    UINT32                                                FUSE_DATA:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F878_STRUCT;

// **** D0F0xBC_x1F87C Register Definition ****
// Address
#define D0F0xBC_x1F87C_ADDRESS                                  0x1f87c

// Type
#define D0F0xBC_x1F87C_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F87C_LL_PCIE_LoadStep_OFFSET                  0
#define D0F0xBC_x1F87C_LL_PCIE_LoadStep_WIDTH                   16
#define D0F0xBC_x1F87C_LL_PCIE_LoadStep_MASK                    0xffff
#define D0F0xBC_x1F87C_LL_VddNbLoadStepBase_OFFSET              16
#define D0F0xBC_x1F87C_LL_VddNbLoadStepBase_WIDTH               16
#define D0F0xBC_x1F87C_LL_VddNbLoadStepBase_MASK                0xffff0000

/// D0F0xBC_x1F87C
typedef union {
  struct {                                                              ///<
    UINT32                                         LL_PCIE_LoadStep:16; ///<
    UINT32                                     LL_VddNbLoadStepBase:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F87C_STRUCT;

// **** D0F0xBC_x1F880 Register Definition ****
// Address
#define D0F0xBC_x1F880_ADDRESS                                  0x1f880

// Type
#define D0F0xBC_x1F880_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F880_LL_VCE_LoadStep_OFFSET                   0
#define D0F0xBC_x1F880_LL_VCE_LoadStep_WIDTH                    16
#define D0F0xBC_x1F880_LL_VCE_LoadStep_MASK                     0xffff
#define D0F0xBC_x1F880_LL_UVD_LoadStep_OFFSET                   16
#define D0F0xBC_x1F880_LL_UVD_LoadStep_WIDTH                    16
#define D0F0xBC_x1F880_LL_UVD_LoadStep_MASK                     0xffff0000

/// D0F0xBC_x1F880
typedef union {
  struct {                                                              ///<
    UINT32                                          LL_VCE_LoadStep:16; ///<
    UINT32                                          LL_UVD_LoadStep:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F880_STRUCT;

// **** D0F0xBC_x1F884 Register Definition ****
// Address
#define D0F0xBC_x1F884_ADDRESS                                  0x1f884

// Type
#define D0F0xBC_x1F884_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F884_LL_DCE2_LoadStep_OFFSET                  0
#define D0F0xBC_x1F884_LL_DCE2_LoadStep_WIDTH                   16
#define D0F0xBC_x1F884_LL_DCE2_LoadStep_MASK                    0xffff
#define D0F0xBC_x1F884_LL_DCE_LoadStep_OFFSET                   16
#define D0F0xBC_x1F884_LL_DCE_LoadStep_WIDTH                    16
#define D0F0xBC_x1F884_LL_DCE_LoadStep_MASK                     0xffff0000

/// D0F0xBC_x1F884
typedef union {
  struct {                                                              ///<
    UINT32                                         LL_DCE2_LoadStep:16; ///<
    UINT32                                          LL_DCE_LoadStep:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F884_STRUCT;

// **** D0F0xBC_x1F888 Register Definition ****
// Address
#define D0F0xBC_x1F888_ADDRESS                                  0x1f888

// Type
#define D0F0xBC_x1F888_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F888_VddNbTdp_OFFSET                          0
#define D0F0xBC_x1F888_VddNbTdp_WIDTH                           16
#define D0F0xBC_x1F888_VddNbTdp_MASK                            0xffff
#define D0F0xBC_x1F888_LL_GPU_LoadStep_OFFSET                   16
#define D0F0xBC_x1F888_LL_GPU_LoadStep_WIDTH                    16
#define D0F0xBC_x1F888_LL_GPU_LoadStep_MASK                     0xffff0000

/// D0F0xBC_x1F888
typedef union {
  struct {                                                              ///<
    UINT32                                                 VddNbTdp:16; ///<
    UINT32                                          LL_GPU_LoadStep:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F888_STRUCT;

// **** D0F0xBC_x1F88C Register Definition ****
// Address
#define D0F0xBC_x1F88C_ADDRESS                                  0x1f88c

// Type
#define D0F0xBC_x1F88C_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F88C_NbVid_3_OFFSET                           0
#define D0F0xBC_x1F88C_NbVid_3_WIDTH                            8
#define D0F0xBC_x1F88C_NbVid_3_MASK                             0xff
#define D0F0xBC_x1F88C_NbVid_2_OFFSET                           8
#define D0F0xBC_x1F88C_NbVid_2_WIDTH                            8
#define D0F0xBC_x1F88C_NbVid_2_MASK                             0xff00
#define D0F0xBC_x1F88C_NbVid_1_OFFSET                           16
#define D0F0xBC_x1F88C_NbVid_1_WIDTH                            8
#define D0F0xBC_x1F88C_NbVid_1_MASK                             0xff0000
#define D0F0xBC_x1F88C_NbVid_0_OFFSET                           24
#define D0F0xBC_x1F88C_NbVid_0_WIDTH                            8
#define D0F0xBC_x1F88C_NbVid_0_MASK                             0xff000000

/// D0F0xBC_x1F88C
typedef union {
  struct {                                                              ///<
    UINT32                                                  NbVid_3:8 ; ///<
    UINT32                                                  NbVid_2:8 ; ///<
    UINT32                                                  NbVid_1:8 ; ///<
    UINT32                                                  NbVid_0:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F88C_STRUCT;

// **** D0F0xBC_x1F890 Register Definition ****
// Address
#define D0F0xBC_x1F890_ADDRESS                                  0x1f890

// Type
#define D0F0xBC_x1F890_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F890_CpuVid_3_OFFSET                           0
#define D0F0xBC_x1F890_CpuVid_3_WIDTH                            8
#define D0F0xBC_x1F890_CpuVid_3_MASK                             0xff
#define D0F0xBC_x1F890_CpuVid_2_OFFSET                           8
#define D0F0xBC_x1F890_CpuVid_2_WIDTH                            8
#define D0F0xBC_x1F890_CpuVid_2_MASK                             0xff00
#define D0F0xBC_x1F890_CpuVid_1_OFFSET                           16
#define D0F0xBC_x1F890_CpuVid_1_WIDTH                            8
#define D0F0xBC_x1F890_CpuVid_1_MASK                             0xff0000
#define D0F0xBC_x1F890_CpuVid_0_OFFSET                           24
#define D0F0xBC_x1F890_CpuVid_0_WIDTH                            8
#define D0F0xBC_x1F890_CpuVid_0_MASK                             0xff000000

/// D0F0xBC_x1F890
typedef union {
  struct {                                                              ///<
    UINT32                                                 CpuVid_3:8 ; ///<
    UINT32                                                 CpuVid_2:8 ; ///<
    UINT32                                                 CpuVid_1:8 ; ///<
    UINT32                                                 CpuVid_0:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F890_STRUCT;

// **** D0F0xBC_x1F894 Register Definition ****
// Address
#define D0F0xBC_x1F894_ADDRESS                                  0x1f894

// Type
#define D0F0xBC_x1F894_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F894_CpuVid_7_OFFSET                           0
#define D0F0xBC_x1F894_CpuVid_7_WIDTH                            8
#define D0F0xBC_x1F894_CpuVid_7_MASK                             0xff
#define D0F0xBC_x1F894_CpuVid_6_OFFSET                           8
#define D0F0xBC_x1F894_CpuVid_6_WIDTH                            8
#define D0F0xBC_x1F894_CpuVid_6_MASK                             0xff00
#define D0F0xBC_x1F894_CpuVid_5_OFFSET                           16
#define D0F0xBC_x1F894_CpuVid_5_WIDTH                            8
#define D0F0xBC_x1F894_CpuVid_5_MASK                             0xff0000
#define D0F0xBC_x1F894_CpuVid_4_OFFSET                           24
#define D0F0xBC_x1F894_CpuVid_4_WIDTH                            8
#define D0F0xBC_x1F894_CpuVid_4_MASK                             0xff000000

/// D0F0xBC_x1F894
typedef union {
  struct {                                                              ///<
    UINT32                                                 CpuVid_7:8 ; ///<
    UINT32                                                 CpuVid_6:8 ; ///<
    UINT32                                                 CpuVid_5:8 ; ///<
    UINT32                                                 CpuVid_4:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F894_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32            ex1000_0:16;
    UINT32            ex1000_1:16;
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1000_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32            ex1001_0:16;
    UINT32            ex1001_1:8;
    UINT32            ex1001_2:8;
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1001_STRUCT;

// **** D0F0xBC_x1F8D4 Register Definition ****
// Address
#define D0F0xBC_x1F8D4_ADDRESS                                  0x1f8d4

// Type
#define D0F0xBC_x1F8D4_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F8D4_BapmPstateVid_3_OFFSET                   0
#define D0F0xBC_x1F8D4_BapmPstateVid_3_WIDTH                    8
#define D0F0xBC_x1F8D4_BapmPstateVid_3_MASK                     0xff
#define D0F0xBC_x1F8D4_BapmPstateVid_2_OFFSET                   8
#define D0F0xBC_x1F8D4_BapmPstateVid_2_WIDTH                    8
#define D0F0xBC_x1F8D4_BapmPstateVid_2_MASK                     0xff00
#define D0F0xBC_x1F8D4_BapmPstateVid_1_OFFSET                   16
#define D0F0xBC_x1F8D4_BapmPstateVid_1_WIDTH                    8
#define D0F0xBC_x1F8D4_BapmPstateVid_1_MASK                     0xff0000
#define D0F0xBC_x1F8D4_BapmPstateVid_0_OFFSET                   24
#define D0F0xBC_x1F8D4_BapmPstateVid_0_WIDTH                    8
#define D0F0xBC_x1F8D4_BapmPstateVid_0_MASK                     0xff000000

/// D0F0xBC_x1F8D4
typedef union {
  struct {                                                              ///<
    UINT32                                           BapmPstateVid_3:8; ///<
    UINT32                                           BapmPstateVid_2:8; ///<
    UINT32                                           BapmPstateVid_1:8; ///<
    UINT32                                           BapmPstateVid_0:8; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F8D4_STRUCT;

// **** D0F0xBC_x1F8D4 Register Definition ****
// Address
#define D0F0xBC_x1F8D8_ADDRESS                                  0x1f8d8

// Type
#define D0F0xBC_x1F8D8_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F8D8_BapmPstateVid_7_OFFSET                   0
#define D0F0xBC_x1F8D8_BapmPstateVid_7_WIDTH                    8
#define D0F0xBC_x1F8D8_BapmPstateVid_7_MASK                     0xff
#define D0F0xBC_x1F8D8_BapmPstateVid_6_OFFSET                   8
#define D0F0xBC_x1F8D8_BapmPstateVid_6_WIDTH                    8
#define D0F0xBC_x1F8D8_BapmPstateVid_6_MASK                     0xff00
#define D0F0xBC_x1F8D8_BapmPstateVid_5_OFFSET                   16
#define D0F0xBC_x1F8D8_BapmPstateVid_5_WIDTH                    8
#define D0F0xBC_x1F8D8_BapmPstateVid_5_MASK                     0xff0000
#define D0F0xBC_x1F8D8_BapmPstateVid_4_OFFSET                   24
#define D0F0xBC_x1F8D8_BapmPstateVid_4_WIDTH                    8
#define D0F0xBC_x1F8D8_BapmPstateVid_4_MASK                     0xff000000

/// D0F0xBC_x1F8D8
typedef union {
  struct {                                                              ///<
    UINT32                                           BapmPstateVid_7:8; ///<
    UINT32                                           BapmPstateVid_6:8; ///<
    UINT32                                           BapmPstateVid_5:8; ///<
    UINT32                                           BapmPstateVid_4:8; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F8D8_STRUCT;

// **** D0F0xBC_x1F8DC Register Definition ****
// Address
#define D0F0xBC_x1F8DC_ADDRESS                                  0x1f8dc

// Type
#define D0F0xBC_x1F8DC_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F8DC_SClkVid3_OFFSET                          0
#define D0F0xBC_x1F8DC_SClkVid3_WIDTH                           8
#define D0F0xBC_x1F8DC_SClkVid3_MASK                            0xff
#define D0F0xBC_x1F8DC_SClkVid2_OFFSET                          8
#define D0F0xBC_x1F8DC_SClkVid2_WIDTH                           8
#define D0F0xBC_x1F8DC_SClkVid2_MASK                            0xff00
#define D0F0xBC_x1F8DC_SClkVid1_OFFSET                          16
#define D0F0xBC_x1F8DC_SClkVid1_WIDTH                           8
#define D0F0xBC_x1F8DC_SClkVid1_MASK                            0xff0000
#define D0F0xBC_x1F8DC_SClkVid0_OFFSET                          24
#define D0F0xBC_x1F8DC_SClkVid0_WIDTH                           8
#define D0F0xBC_x1F8DC_SClkVid0_MASK                            0xff000000

/// D0F0xBC_x1F8DC
typedef union {
  struct {                                                              ///<
    UINT32                                                  SClkVid3:8; ///<
    UINT32                                                  SClkVid2:8; ///<
    UINT32                                                  SClkVid1:8; ///<
    UINT32                                                  SClkVid0:8; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F8DC_STRUCT;

// **** D0F0xBC_x1F8E0 Register Definition ****
// Address
#define D0F0xBC_x1F8E0_ADDRESS                                  0x1f8e0

// Type
#define D0F0xBC_x1F8E0_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F8E0_BapmSclkVid_2_OFFSET                     0
#define D0F0xBC_x1F8E0_BapmSclkVid_2_WIDTH                      8
#define D0F0xBC_x1F8E0_BapmSclkVid_2_MASK                       0xff
#define D0F0xBC_x1F8E0_BapmSclkVid_1_OFFSET                     8
#define D0F0xBC_x1F8E0_BapmSclkVid_1_WIDTH                      8
#define D0F0xBC_x1F8E0_BapmSclkVid_1_MASK                       0xff00
#define D0F0xBC_x1F8E0_BapmSclkVid_0_OFFSET                     16
#define D0F0xBC_x1F8E0_BapmSclkVid_0_WIDTH                      8
#define D0F0xBC_x1F8E0_BapmSclkVid_0_MASK                       0xff0000
#define D0F0xBC_x1F8E0_DdrVoltFloor_OFFSET                      24
#define D0F0xBC_x1F8E0_DdrVoltFloor_WIDTH                       8
#define D0F0xBC_x1F8E0_DdrVoltFloor_MASK                        0xff000000

/// D0F0xBC_x1F8E0
typedef union {
  struct {                                                              ///<
    UINT32                                             BapmSclkVid_2:8; ///<
    UINT32                                             BapmSclkVid_1:8; ///<
    UINT32                                             BapmSclkVid_0:8; ///<
    UINT32                                              DdrVoltFloor:8; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F8E0_STRUCT;

// **** D0F0xBC_x1F8E4 Register Definition ****
// Address
#define D0F0xBC_x1F8E4_ADDRESS                                  0x1f8e4

// Type
#define D0F0xBC_x1F8E4_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F8E4_BapmNbVid_1_OFFSET                       0
#define D0F0xBC_x1F8E4_BapmNbVid_1_WIDTH                        8
#define D0F0xBC_x1F8E4_BapmNbVid_1_MASK                         0xff
#define D0F0xBC_x1F8E4_BapmNbVid_0_OFFSET                       8
#define D0F0xBC_x1F8E4_BapmNbVid_0_WIDTH                        8
#define D0F0xBC_x1F8E4_BapmNbVid_0_MASK                         0xff00
#define D0F0xBC_x1F8E4_BapmDdrVoltFloor_OFFSET                  16
#define D0F0xBC_x1F8E4_BapmDdrVoltFloor_WIDTH                   8
#define D0F0xBC_x1F8E4_BapmDdrVoltFloor_MASK                    0xff0000
#define D0F0xBC_x1F8E4_BapmSclkVid_3_OFFSET                     24
#define D0F0xBC_x1F8E4_BapmSclkVid_3_WIDTH                      8
#define D0F0xBC_x1F8E4_BapmSclkVid_3_MASK                       0xff000000

/// D0F0xBC_x1F8E4
typedef union {
  struct {                                                              ///<
    UINT32                                               BapmNbVid_1:8; ///<
    UINT32                                               BapmNbVid_0:8; ///<
    UINT32                                          BapmDdrVoltFloor:8; ///<
    UINT32                                             BapmSclkVid_3:8; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F8E4_STRUCT;

// **** D0F0xBC_x1F8E8 Register Definition ****
// Address
#define D0F0xBC_x1F8E8_ADDRESS                                  0x1f8e8

// Type
#define D0F0xBC_x1F8E8_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F8E8_Reserved_15_0_OFFSET                     0
#define D0F0xBC_x1F8E8_Reserved_15_0_WIDTH                      16
#define D0F0xBC_x1F8E8_Reserved_15_0_MASK                       0xffff
#define D0F0xBC_x1F8E8_BapmNbVid_3_OFFSET                       16
#define D0F0xBC_x1F8E8_BapmNbVid_3_WIDTH                        8
#define D0F0xBC_x1F8E8_BapmNbVid_3_MASK                         0xff0000
#define D0F0xBC_x1F8E8_BapmNbVid_2_OFFSET                       24
#define D0F0xBC_x1F8E8_BapmNbVid_2_WIDTH                        8
#define D0F0xBC_x1F8E8_BapmNbVid_2_MASK                         0xff000000

/// D0F0xBC_x1F8E8
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_15_0:16; ///<
    UINT32                                              BapmNbVid_3:8;  ///<
    UINT32                                              BapmNbVid_2:8;  ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F8E8_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32            ex1002_0:10;
    UINT32            ex1002_1:20;
    UINT32            ex1002_2:2;
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1002_STRUCT;

// **** D0F0xBC_x1F85C Register Definition ****
// Address
#define D0F0xBC_x1F85C_ADDRESS                                  0x1f85c

// Type
#define D0F0xBC_x1F85C_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F85C_VCETdp_OFFSET                            0
#define D0F0xBC_x1F85C_VCETdp_WIDTH                             20
#define D0F0xBC_x1F85C_VCETdp_MASK                              0xfffff
#define D0F0xBC_x1F85C_spare8_OFFSET                            20
#define D0F0xBC_x1F85C_spare8_WIDTH                             1
#define D0F0xBC_x1F85C_spare8_MASK                              0x100000
#define D0F0xBC_x1F85C_TdpAgeValue_OFFSET                       21
#define D0F0xBC_x1F85C_TdpAgeValue_WIDTH                        3
#define D0F0xBC_x1F85C_TdpAgeValue_MASK                         0xe00000
#define D0F0xBC_x1F85C_TdpAgeRate_OFFSET                        24
#define D0F0xBC_x1F85C_TdpAgeRate_WIDTH                         8
#define D0F0xBC_x1F85C_TdpAgeRate_MASK                          0xff000000

/// D0F0xBC_x1F85C
typedef union {
  struct {                                                               ///<
    UINT32                                                    VCETdp:20; ///<
    UINT32                                                    spare8:1;  ///<
    UINT32                                               TdpAgeValue:3;  ///<
    UINT32                                                TdpAgeRate:8;  ///<
  } Field;                                                               ///<
  UINT32 Value;                                                          ///<
} D0F0xBC_x1F85C_STRUCT;

// **** D0F0xBC_x1F860 Register Definition ****
// Address
#define D0F0xBC_x1F860_ADDRESS                                  0x1f860

// Type
#define D0F0xBC_x1F860_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F860_BAPMTI_TjHyst_1_OFFSET                   0
#define D0F0xBC_x1F860_BAPMTI_TjHyst_1_WIDTH                    8
#define D0F0xBC_x1F860_BAPMTI_TjHyst_1_MASK                     0xff
#define D0F0xBC_x1F860_BAPMTI_TjMax_1_OFFSET                    8
#define D0F0xBC_x1F860_BAPMTI_TjMax_1_WIDTH                     8
#define D0F0xBC_x1F860_BAPMTI_TjMax_1_MASK                      0xff00
#define D0F0xBC_x1F860_BAPMTI_TjHyst_0_OFFSET                   16
#define D0F0xBC_x1F860_BAPMTI_TjHyst_0_WIDTH                    8
#define D0F0xBC_x1F860_BAPMTI_TjHyst_0_MASK                     0xff0000
#define D0F0xBC_x1F860_BAPMTI_TjMax_0_OFFSET                    24
#define D0F0xBC_x1F860_BAPMTI_TjMax_0_WIDTH                     8
#define D0F0xBC_x1F860_BAPMTI_TjMax_0_MASK                      0xff000000

/// D0F0xBC_x1F860
typedef union {
  struct {                                                              ///<
    UINT32                                           BAPMTI_TjHyst_1:8; ///<
    UINT32                                            BAPMTI_TjMax_1:8; ///<
    UINT32                                           BAPMTI_TjHyst_0:8; ///<
    UINT32                                            BAPMTI_TjMax_0:8; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F860_STRUCT;

// **** D0F0xBC_x1F864 Register Definition ****
// Address
#define D0F0xBC_x1F864_ADDRESS                                  0x1f864

// Type
#define D0F0xBC_x1F864_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F864_PCIe2PhyOffset_OFFSET                    0
#define D0F0xBC_x1F864_PCIe2PhyOffset_WIDTH                     8
#define D0F0xBC_x1F864_PCIe2PhyOffset_MASK                      0xff
#define D0F0xBC_x1F864_PCIe1PhyOffset_OFFSET                    8
#define D0F0xBC_x1F864_PCIe1PhyOffset_WIDTH                     8
#define D0F0xBC_x1F864_PCIe1PhyOffset_MASK                      0xff00
#define D0F0xBC_x1F864_BAPMTI_GpuTjHyst_OFFSET                  16
#define D0F0xBC_x1F864_BAPMTI_GpuTjHyst_WIDTH                   8
#define D0F0xBC_x1F864_BAPMTI_GpuTjHyst_MASK                    0xff0000
#define D0F0xBC_x1F864_BAPMTI_GpuTjMax_OFFSET                   24
#define D0F0xBC_x1F864_BAPMTI_GpuTjMax_WIDTH                    8
#define D0F0xBC_x1F864_BAPMTI_GpuTjMax_MASK                     0xff000000

/// D0F0xBC_x1F864
typedef union {
  struct {                                                              ///<
    UINT32                                            PCIe2PhyOffset:8; ///<
    UINT32                                            PCIe1PhyOffset:8; ///<
    UINT32                                          BAPMTI_GpuTjHyst:8; ///<
    UINT32                                           BAPMTI_GpuTjMax:8; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F864_STRUCT;

// **** D0F0xBC_x1F86C Register Definition ****
// Address
#define D0F0xBC_x1F86C_ADDRESS                                  0x1f86c

// Type
#define D0F0xBC_x1F86C_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F86C_Reserved_22_0_OFFSET                     0
#define D0F0xBC_x1F86C_Reserved_22_0_WIDTH                      23
#define D0F0xBC_x1F86C_Reserved_22_0_MASK                       0x7fffff
#define D0F0xBC_x1F86C_BapmLhtcCap_OFFSET                       23
#define D0F0xBC_x1F86C_BapmLhtcCap_WIDTH                        1
#define D0F0xBC_x1F86C_BapmLhtcCap_MASK                         0x800000
#define D0F0xBC_x1F86C_Reserved_31_24_OFFSET                    24
#define D0F0xBC_x1F86C_Reserved_31_24_WIDTH                     8
#define D0F0xBC_x1F86C_Reserved_31_24_MASK                      0xff000000

/// D0F0xBC_x1F86C
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_22_0:23;///<
    UINT32                                               BapmLhtcCap:1; ///<
    UINT32                                            Reserved_31_24:8; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F86C_STRUCT;


typedef union {
  struct {                                                              ///<
    UINT32            ex1003_0:32;
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1003_STRUCT;



// **** D0F0xBC_x1FE00 Register Definition ****
// Address
#define D0F0xBC_x1FE00_ADDRESS                                  0x1fe00

// Type
#define D0F0xBC_x1FE00_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1FE00_Data_OFFSET                              0
#define D0F0xBC_x1FE00_Data_WIDTH                               32
#define D0F0xBC_x1FE00_Data_MASK                                0xffffffff

/// D0F0xBC_x1FE00
typedef union {
  struct {                                                              ///<
    UINT32                                                     Data:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1FE00_STRUCT;


typedef union {
  struct {                                                              ///<
    UINT32                                              INTR_MASK_0:1 ; ///<
    UINT32                                              INTR_MASK_1:1 ; ///<
    UINT32                                              INTR_MASK_2:1 ; ///<
    UINT32                                              INTR_MASK_3:1 ; ///<
    UINT32                                              INTR_MASK_4:1 ; ///<
    UINT32                                              INTR_MASK_5:1 ; ///<
    UINT32                                              INTR_MASK_6:1 ; ///<
    UINT32                                              INTR_MASK_7:1 ; ///<
    UINT32                                              INTR_MASK_8:1 ; ///<
    UINT32                                              INTR_MASK_9:1 ; ///<
    UINT32                                             INTR_MASK_10:1 ; ///<
    UINT32                                             INTR_MASK_11:1 ; ///<
    UINT32                                             INTR_MASK_12:1 ; ///<
    UINT32                                             INTR_MASK_13:1 ; ///<
    UINT32                                             INTR_MASK_14:1 ; ///<
    UINT32                                             INTR_MASK_15:1 ; ///<
    UINT32                                             INTR_MASK_16:1 ; ///<
    UINT32                                             INTR_MASK_17:1 ; ///<
    UINT32                                             INTR_MASK_18:1 ; ///<
    UINT32                                             INTR_MASK_19:1 ; ///<
    UINT32                                             INTR_MASK_20:1 ; ///<
    UINT32                                             INTR_MASK_21:1 ; ///<
    UINT32                                             INTR_MASK_22:1 ; ///<
    UINT32                                             INTR_MASK_23:1 ; ///<
    UINT32                                             INTR_MASK_24:1 ; ///<
    UINT32                                             INTR_MASK_25:1 ; ///<
    UINT32                                             INTR_MASK_26:1 ; ///<
    UINT32                                             INTR_MASK_27:1 ; ///<
    UINT32                                             INTR_MASK_28:1 ; ///<
    UINT32                                             INTR_MASK_29:1 ; ///<
    UINT32                                             INTR_MASK_30:1 ; ///<
    UINT32                                             INTR_MASK_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1005_STRUCT;

// **** D0F0xBC_xE0000004 Register Definition ****
// Address
#define D0F0xBC_xE0000004_ADDRESS                               0xe0000004

// Type
#define D0F0xBC_xE0000004_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_req_OFFSET            0
#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_req_WIDTH             1
#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_req_MASK              0x1
#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_done_OFFSET           1
#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_done_WIDTH            1
#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_done_MASK             0x2
#define D0F0xBC_xE0000004_drv_rst_mode_OFFSET                   2
#define D0F0xBC_xE0000004_drv_rst_mode_WIDTH                    1
#define D0F0xBC_xE0000004_drv_rst_mode_MASK                     0x4
#define D0F0xBC_xE0000004_SMU_DC_efuse_status_invalid_OFFSET    3
#define D0F0xBC_xE0000004_SMU_DC_efuse_status_invalid_WIDTH     1
#define D0F0xBC_xE0000004_SMU_DC_efuse_status_invalid_MASK      0x8
#define D0F0xBC_xE0000004_Reserved_OFFSET                       4
#define D0F0xBC_xE0000004_Reserved_WIDTH                        1
#define D0F0xBC_xE0000004_Reserved_MASK                         0x10
#define D0F0xBC_xE0000004_TST_RCU_jpc_DtmSMSCntDone_OFFSET      5
#define D0F0xBC_xE0000004_TST_RCU_jpc_DtmSMSCntDone_WIDTH       1
#define D0F0xBC_xE0000004_TST_RCU_jpc_DtmSMSCntDone_MASK        0x20
#define D0F0xBC_xE0000004_TP_Tester_OFFSET                      6
#define D0F0xBC_xE0000004_TP_Tester_WIDTH                       1
#define D0F0xBC_xE0000004_TP_Tester_MASK                        0x40
#define D0F0xBC_xE0000004_boot_seq_done_OFFSET                  7
#define D0F0xBC_xE0000004_boot_seq_done_WIDTH                   1
#define D0F0xBC_xE0000004_boot_seq_done_MASK                    0x80
#define D0F0xBC_xE0000004_sclk_deep_sleep_exit_OFFSET           8
#define D0F0xBC_xE0000004_sclk_deep_sleep_exit_WIDTH            1
#define D0F0xBC_xE0000004_sclk_deep_sleep_exit_MASK             0x100
#define D0F0xBC_xE0000004_BREAK_PT1_ACTIVE_OFFSET               9
#define D0F0xBC_xE0000004_BREAK_PT1_ACTIVE_WIDTH                1
#define D0F0xBC_xE0000004_BREAK_PT1_ACTIVE_MASK                 0x200
#define D0F0xBC_xE0000004_BREAK_PT2_ACTIVE_OFFSET               10
#define D0F0xBC_xE0000004_BREAK_PT2_ACTIVE_WIDTH                1
#define D0F0xBC_xE0000004_BREAK_PT2_ACTIVE_MASK                 0x400
#define D0F0xBC_xE0000004_FCH_HALT_OFFSET                       11
#define D0F0xBC_xE0000004_FCH_HALT_WIDTH                        1
#define D0F0xBC_xE0000004_FCH_HALT_MASK                         0x800
#define D0F0xBC_xE0000004_FCH_LOCKDOWN_WRITE_DIS_OFFSET         12
#define D0F0xBC_xE0000004_FCH_LOCKDOWN_WRITE_DIS_WIDTH          1
#define D0F0xBC_xE0000004_FCH_LOCKDOWN_WRITE_DIS_MASK           0x1000
#define D0F0xBC_xE0000004_RCU_GIO_fch_lockdown_OFFSET           13
#define D0F0xBC_xE0000004_RCU_GIO_fch_lockdown_WIDTH            1
#define D0F0xBC_xE0000004_RCU_GIO_fch_lockdown_MASK             0x2000
#define D0F0xBC_xE0000004_Reserved14_23_OFFSET                  14
#define D0F0xBC_xE0000004_Reserved14_23_WIDTH                   10
#define D0F0xBC_xE0000004_Reserved14_23_MASK                    0xffc000
#define D0F0xBC_xE0000004_lm32_irq31_sel_OFFSET                 24
#define D0F0xBC_xE0000004_lm32_irq31_sel_WIDTH                  2
#define D0F0xBC_xE0000004_lm32_irq31_sel_MASK                   0x3000000
#define D0F0xBC_xE0000004_Reserved26_31_OFFSET                  26
#define D0F0xBC_xE0000004_Reserved26_31_WIDTH                   6
#define D0F0xBC_xE0000004_Reserved26_31_MASK                    0xfc000000

/// D0F0xBC_xE0000004
typedef union {
  struct {                                                              ///<
    UINT32                                      RCU_TST_jpc_rep_req:1 ; ///<
    UINT32                                     RCU_TST_jpc_rep_done:1 ; ///<
    UINT32                                             drv_rst_mode:1 ; ///<
    UINT32                              SMU_DC_efuse_status_invalid:1 ; ///<
    UINT32                                                 Reserved:1 ; ///<
    UINT32                                TST_RCU_jpc_DtmSMSCntDone:1 ; ///<
    UINT32                                                TP_Tester:1 ; ///<
    UINT32                                            boot_seq_done:1 ; ///<
    UINT32                                     sclk_deep_sleep_exit:1 ; ///<
    UINT32                                         BREAK_PT1_ACTIVE:1 ; ///<
    UINT32                                         BREAK_PT2_ACTIVE:1 ; ///<
    UINT32                                                 FCH_HALT:1 ; ///<
    UINT32                                   FCH_LOCKDOWN_WRITE_DIS:1 ; ///<
    UINT32                                     RCU_GIO_fch_lockdown:1 ; ///<
    UINT32                                            Reserved14_23:10; ///<
    UINT32                                           lm32_irq31_sel:2 ; ///<
    UINT32                                            Reserved26_31:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0000004_STRUCT;

// **** D0F0xBC_xE0000120 Register Definition ****
// Address
#define D0F0xBC_xE0000120_ADDRESS                               0xe0000120

// Type
#define D0F0xBC_xE0000120_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0000120_ActivityCntRst_OFFSET                 0
#define D0F0xBC_xE0000120_ActivityCntRst_WIDTH                  1
#define D0F0xBC_xE0000120_ActivityCntRst_MASK                   0x1
#define D0F0xBC_xE0000120_PeriodCntRst_OFFSET                   1
#define D0F0xBC_xE0000120_PeriodCntRst_WIDTH                    1
#define D0F0xBC_xE0000120_PeriodCntRst_MASK                     0x2
#define D0F0xBC_xE0000120_Reserved_2_2_OFFSET                   2
#define D0F0xBC_xE0000120_Reserved_2_2_WIDTH                    1
#define D0F0xBC_xE0000120_Reserved_2_2_MASK                     0x4
#define D0F0xBC_xE0000120_BusyCntSel_OFFSET                     3
#define D0F0xBC_xE0000120_BusyCntSel_WIDTH                      2
#define D0F0xBC_xE0000120_BusyCntSel_MASK                       0x18
#define D0F0xBC_xE0000120_Reserved_7_5_OFFSET                   5
#define D0F0xBC_xE0000120_Reserved_7_5_WIDTH                    3
#define D0F0xBC_xE0000120_Reserved_7_5_MASK                     0xe0
#define D0F0xBC_xE0000120_EnBifCnt_OFFSET                       8
#define D0F0xBC_xE0000120_EnBifCnt_WIDTH                        1
#define D0F0xBC_xE0000120_EnBifCnt_MASK                         0x100
#define D0F0xBC_xE0000120_EnOrbUsCnt_OFFSET                     9
#define D0F0xBC_xE0000120_EnOrbUsCnt_WIDTH                      1
#define D0F0xBC_xE0000120_EnOrbUsCnt_MASK                       0x200
#define D0F0xBC_xE0000120_EnOrbDsCnt_OFFSET                     10
#define D0F0xBC_xE0000120_EnOrbDsCnt_WIDTH                      1
#define D0F0xBC_xE0000120_EnOrbDsCnt_MASK                       0x400
#define D0F0xBC_xE0000120_Reserved_31_11_OFFSET                 11
#define D0F0xBC_xE0000120_Reserved_31_11_WIDTH                  21
#define D0F0xBC_xE0000120_Reserved_31_11_MASK                   0xfffff800

/// D0F0xBC_xE0000120
typedef union {
  struct {                                                              ///<
    UINT32                                           ActivityCntRst:1 ; ///<
    UINT32                                             PeriodCntRst:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                               BusyCntSel:2 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                                 EnBifCnt:1 ; ///<
    UINT32                                               EnOrbUsCnt:1 ; ///<
    UINT32                                               EnOrbDsCnt:1 ; ///<
    UINT32                                           Reserved_31_11:21; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0000120_STRUCT;

// **** D0F0xBC_xE0001008 Register Definition ****
// Address
#define D0F0xBC_xE0001008_ADDRESS                               0xe0001008

// Type
#define D0F0xBC_xE0001008_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0001008_SClkVid0_OFFSET                       0
#define D0F0xBC_xE0001008_SClkVid0_WIDTH                        8
#define D0F0xBC_xE0001008_SClkVid0_MASK                         0xff
#define D0F0xBC_xE0001008_SClkVid1_OFFSET                       8
#define D0F0xBC_xE0001008_SClkVid1_WIDTH                        8
#define D0F0xBC_xE0001008_SClkVid1_MASK                         0xff00
#define D0F0xBC_xE0001008_SClkVid2_OFFSET                       16
#define D0F0xBC_xE0001008_SClkVid2_WIDTH                        8
#define D0F0xBC_xE0001008_SClkVid2_MASK                         0xff0000
#define D0F0xBC_xE0001008_SClkVid3_OFFSET                       24
#define D0F0xBC_xE0001008_SClkVid3_WIDTH                        8
#define D0F0xBC_xE0001008_SClkVid3_MASK                         0xff000000

/// D0F0xBC_xE0001008
typedef union {
  struct {                                                              ///<
    UINT32                                                 SClkVid0:8 ; ///<
    UINT32                                                 SClkVid1:8 ; ///<
    UINT32                                                 SClkVid2:8 ; ///<
    UINT32                                                 SClkVid3:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0001008_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32                                                 WriteDis:1 ; ///<
    UINT32                                                    RfRm7:1 ; ///<
    UINT32                                                      Rme:1 ; ///<
    UINT32                                             MbistDisable:1 ; ///<
    UINT32                                        HardRepairDisable:1 ; ///<
    UINT32                                        SoftRepairDisable:1 ; ///<
    UINT32                                         SmsPwrdwnDisable:1 ; ///<
    UINT32                                           Crbbmp1500Disa:1 ; ///<
    UINT32                                           Crbbmp1500Disb:1 ; ///<
    UINT32                                                   GpuDis:1 ; ///<
    UINT32                      ex1006_0:6;
    UINT32                      ex1006_1:2;
    UINT32                                                DftSpare1:1 ; ///<
    UINT32                                                DftSpare2:1 ; ///<
    UINT32                                                DftSpare3:1 ; ///<
    UINT32                                               VceDisable:1 ; ///<
    UINT32                                           DceScanDisable:1 ; ///<
    UINT32                                           Reserved_31_23:9 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1006_STRUCT;

// **** D0F0xBC_xE0003000 Register Definition ****
// Address
#define D0F0xBC_xE0003000_ADDRESS                               0xe0003000

// Type
#define D0F0xBC_xE0003000_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0003000_IntToggle_OFFSET                      0
#define D0F0xBC_xE0003000_IntToggle_WIDTH                       1
#define D0F0xBC_xE0003000_IntToggle_MASK                        0x1
#define D0F0xBC_xE0003000_ServiceIndex_OFFSET                   1
#define D0F0xBC_xE0003000_ServiceIndex_WIDTH                    16
#define D0F0xBC_xE0003000_ServiceIndex_MASK                     0x1fffe
#define D0F0xBC_xE0003000_Reserved_31_17_OFFSET                 17
#define D0F0xBC_xE0003000_Reserved_31_17_WIDTH                  15
#define D0F0xBC_xE0003000_Reserved_31_17_MASK                   0xfffe0000

/// D0F0xBC_xE0003000
typedef union {
  struct {                                                              ///<
    UINT32                                                IntToggle:1 ; ///<
    UINT32                                             ServiceIndex:16; ///<
    UINT32                                           Reserved_31_17:15; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0003000_STRUCT;

// **** D0F0xBC_xE0003004 Register Definition ****
// Address
#define D0F0xBC_xE0003004_ADDRESS                               0xe0003004

// Type
#define D0F0xBC_xE0003004_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0003004_IntAck_OFFSET                         0
#define D0F0xBC_xE0003004_IntAck_WIDTH                          1
#define D0F0xBC_xE0003004_IntAck_MASK                           0x1
#define D0F0xBC_xE0003004_IntDone_OFFSET                        1
#define D0F0xBC_xE0003004_IntDone_WIDTH                         1
#define D0F0xBC_xE0003004_IntDone_MASK                          0x2
#define D0F0xBC_xE0003004_Reserved_31_2_OFFSET                  2
#define D0F0xBC_xE0003004_Reserved_31_2_WIDTH                   30
#define D0F0xBC_xE0003004_Reserved_31_2_MASK                    0xfffffffc

/// D0F0xBC_xE0003004
typedef union {
  struct {                                                              ///<
    UINT32                                                   IntAck:1 ; ///<
    UINT32                                                  IntDone:1 ; ///<
    UINT32                                            Reserved_31_2:30; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0003004_STRUCT;

// **** D0F0xBC_xE0003024 Register Definition ****
// Address
#define D0F0xBC_xE0003024_ADDRESS                               0xe0003024

// Type
#define D0F0xBC_xE0003024_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0003024_SMU_SCRATCH_A_OFFSET                  0
#define D0F0xBC_xE0003024_SMU_SCRATCH_A_WIDTH                   32
#define D0F0xBC_xE0003024_SMU_SCRATCH_A_MASK                    0xffffffff

/// D0F0xBC_xE0003024
typedef union {
  struct {                                                              ///<
    UINT32                                            SMU_SCRATCH_A:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0003024_STRUCT;

// **** D0F0xBC_xE0003034 Register Definition ****
// Address
#define D0F0xBC_xE0003034_ADDRESS                               0xe0003034

// Type
#define D0F0xBC_xE0003034_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0003034_PmAllcpusincc6_OFFSET                 0
#define D0F0xBC_xE0003034_PmAllcpusincc6_WIDTH                  1
#define D0F0xBC_xE0003034_PmAllcpusincc6_MASK                   0x1
#define D0F0xBC_xE0003034_PmNbps_OFFSET                         1
#define D0F0xBC_xE0003034_PmNbps_WIDTH                          1
#define D0F0xBC_xE0003034_PmNbps_MASK                           0x2
#define D0F0xBC_xE0003034_PmCommitselfrefr_OFFSET               2
#define D0F0xBC_xE0003034_PmCommitselfrefr_WIDTH                2
#define D0F0xBC_xE0003034_PmCommitselfrefr_MASK                 0xc
#define D0F0xBC_xE0003034_PmPreselfrefresh_OFFSET               4
#define D0F0xBC_xE0003034_PmPreselfrefresh_WIDTH                1
#define D0F0xBC_xE0003034_PmPreselfrefresh_MASK                 0x10
#define D0F0xBC_xE0003034_PmReqnbpstate_OFFSET                  5
#define D0F0xBC_xE0003034_PmReqnbpstate_WIDTH                   1
#define D0F0xBC_xE0003034_PmReqnbpstate_MASK                    0x20
#define D0F0xBC_xE0003034_Reserved_8_6_OFFSET                   6
#define D0F0xBC_xE0003034_Reserved_8_6_WIDTH                    3
#define D0F0xBC_xE0003034_Reserved_8_6_MASK                     0x1c0
#define D0F0xBC_xE0003034_NbNbps_OFFSET                         9
#define D0F0xBC_xE0003034_NbNbps_WIDTH                          1
#define D0F0xBC_xE0003034_NbNbps_MASK                           0x200
#define D0F0xBC_xE0003034_NbCommitselfrefr_OFFSET               10
#define D0F0xBC_xE0003034_NbCommitselfrefr_WIDTH                2
#define D0F0xBC_xE0003034_NbCommitselfrefr_MASK                 0xc00
#define D0F0xBC_xE0003034_NbPreselfrefresh_OFFSET               12
#define D0F0xBC_xE0003034_NbPreselfrefresh_WIDTH                1
#define D0F0xBC_xE0003034_NbPreselfrefresh_MASK                 0x1000
#define D0F0xBC_xE0003034_NbReqnbpstate_OFFSET                  13
#define D0F0xBC_xE0003034_NbReqnbpstate_WIDTH                   1
#define D0F0xBC_xE0003034_NbReqnbpstate_MASK                    0x2000
#define D0F0xBC_xE0003034_McNbps_OFFSET                         14
#define D0F0xBC_xE0003034_McNbps_WIDTH                          1
#define D0F0xBC_xE0003034_McNbps_MASK                           0x4000
#define D0F0xBC_xE0003034_GmconCommitselfrefr_OFFSET            15
#define D0F0xBC_xE0003034_GmconCommitselfrefr_WIDTH             2
#define D0F0xBC_xE0003034_GmconCommitselfrefr_MASK              0x18000
#define D0F0xBC_xE0003034_GmconPreselfrefresh_OFFSET            17
#define D0F0xBC_xE0003034_GmconPreselfrefresh_WIDTH             1
#define D0F0xBC_xE0003034_GmconPreselfrefresh_MASK              0x20000
#define D0F0xBC_xE0003034_GmconReqnbpstate_OFFSET               18
#define D0F0xBC_xE0003034_GmconReqnbpstate_WIDTH                1
#define D0F0xBC_xE0003034_GmconReqnbpstate_MASK                 0x40000
#define D0F0xBC_xE0003034_SysIso_OFFSET                         19
#define D0F0xBC_xE0003034_SysIso_WIDTH                          1
#define D0F0xBC_xE0003034_SysIso_MASK                           0x80000
#define D0F0xBC_xE0003034_CpIso_OFFSET                          20
#define D0F0xBC_xE0003034_CpIso_WIDTH                           1
#define D0F0xBC_xE0003034_CpIso_MASK                            0x100000
#define D0F0xBC_xE0003034_Dc0Iso_OFFSET                         21
#define D0F0xBC_xE0003034_Dc0Iso_WIDTH                          1
#define D0F0xBC_xE0003034_Dc0Iso_MASK                           0x200000
#define D0F0xBC_xE0003034_Dc1Iso_OFFSET                         22
#define D0F0xBC_xE0003034_Dc1Iso_WIDTH                          1
#define D0F0xBC_xE0003034_Dc1Iso_MASK                           0x400000
#define D0F0xBC_xE0003034_DciIso_OFFSET                         23
#define D0F0xBC_xE0003034_DciIso_WIDTH                          1
#define D0F0xBC_xE0003034_DciIso_MASK                           0x800000
#define D0F0xBC_xE0003034_DcipgIso_OFFSET                       24
#define D0F0xBC_xE0003034_DcipgIso_WIDTH                        1
#define D0F0xBC_xE0003034_DcipgIso_MASK                         0x1000000
#define D0F0xBC_xE0003034_DdiIso_OFFSET                         25
#define D0F0xBC_xE0003034_DdiIso_WIDTH                          1
#define D0F0xBC_xE0003034_DdiIso_MASK                           0x2000000
#define D0F0xBC_xE0003034_GmcIso_OFFSET                         26
#define D0F0xBC_xE0003034_GmcIso_WIDTH                          1
#define D0F0xBC_xE0003034_GmcIso_MASK                           0x4000000
#define D0F0xBC_xE0003034_Reserved_27_27_OFFSET                 27
#define D0F0xBC_xE0003034_Reserved_27_27_WIDTH                  1
#define D0F0xBC_xE0003034_Reserved_27_27_MASK                   0x8000000
#define D0F0xBC_xE0003034_GmcPmSel_OFFSET                       28
#define D0F0xBC_xE0003034_GmcPmSel_WIDTH                        2
#define D0F0xBC_xE0003034_GmcPmSel_MASK                         0x30000000
#define D0F0xBC_xE0003034_CpPmSel_OFFSET                        30
#define D0F0xBC_xE0003034_CpPmSel_WIDTH                         2
#define D0F0xBC_xE0003034_CpPmSel_MASK                          0xc0000000

/// D0F0xBC_xE0003034
typedef union {
  struct {                                                              ///<
    UINT32                                           PmAllcpusincc6:1 ; ///<
    UINT32                                                   PmNbps:1 ; ///<
    UINT32                                         PmCommitselfrefr:2 ; ///<
    UINT32                                         PmPreselfrefresh:1 ; ///<
    UINT32                                            PmReqnbpstate:1 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                                   NbNbps:1 ; ///<
    UINT32                                         NbCommitselfrefr:2 ; ///<
    UINT32                                         NbPreselfrefresh:1 ; ///<
    UINT32                                            NbReqnbpstate:1 ; ///<
    UINT32                                                   McNbps:1 ; ///<
    UINT32                                      GmconCommitselfrefr:2 ; ///<
    UINT32                                      GmconPreselfrefresh:1 ; ///<
    UINT32                                         GmconReqnbpstate:1 ; ///<
    UINT32                                                   SysIso:1 ; ///<
    UINT32                                                    CpIso:1 ; ///<
    UINT32                                                   Dc0Iso:1 ; ///<
    UINT32                                                   Dc1Iso:1 ; ///<
    UINT32                                                   DciIso:1 ; ///<
    UINT32                                                 DcipgIso:1 ; ///<
    UINT32                                                   DdiIso:1 ; ///<
    UINT32                                                   GmcIso:1 ; ///<
    UINT32                                           Reserved_27_27:1 ; ///<
    UINT32                                                 GmcPmSel:2 ; ///<
    UINT32                                                  CpPmSel:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0003034_STRUCT;

// **** D0F0xBC_xE0003048 Register Definition ****
// Address
#define D0F0xBC_xE0003048_ADDRESS                               0xe0003048

// Type
#define D0F0xBC_xE0003048_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0003048_Fracv_OFFSET                          0
#define D0F0xBC_xE0003048_Fracv_WIDTH                           12
#define D0F0xBC_xE0003048_Fracv_MASK                            0xfff
#define D0F0xBC_xE0003048_Intv_OFFSET                           12
#define D0F0xBC_xE0003048_Intv_WIDTH                            7
#define D0F0xBC_xE0003048_Intv_MASK                             0x7f000
#define D0F0xBC_xE0003048_Reserved_31_19_OFFSET                 19
#define D0F0xBC_xE0003048_Reserved_31_19_WIDTH                  13
#define D0F0xBC_xE0003048_Reserved_31_19_MASK                   0xfff80000

/// D0F0xBC_xE0003048
typedef union {
  struct {                                                              ///<
    UINT32                                                    Fracv:12; ///<
    UINT32                                                     Intv:7 ; ///<
    UINT32                                           Reserved_31_19:13; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0003048_STRUCT;

// **** D0F0xBC_xE0003088 Register Definition ****
// Address
#define D0F0xBC_xE0003088_ADDRESS                               0xe0003088

// Type
#define D0F0xBC_xE0003088_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0003088_SmuAuthDone_OFFSET                    0
#define D0F0xBC_xE0003088_SmuAuthDone_WIDTH                     1
#define D0F0xBC_xE0003088_SmuAuthDone_MASK                      0x1
#define D0F0xBC_xE0003088_SmuAuthPass_OFFSET                    1
#define D0F0xBC_xE0003088_SmuAuthPass_WIDTH                     1
#define D0F0xBC_xE0003088_SmuAuthPass_MASK                      0x2
#define D0F0xBC_xE0003088_Reserved_31_2_OFFSET                  2
#define D0F0xBC_xE0003088_Reserved_31_2_WIDTH                   30
#define D0F0xBC_xE0003088_Reserved_31_2_MASK                    0xfffffffc

/// D0F0xBC_xE0003088
typedef union {
  struct {                                                              ///<
    UINT32                                              SmuAuthDone:1 ; ///<
    UINT32                                              SmuAuthPass:1 ; ///<
    UINT32                                            Reserved_31_2:30; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0003088_STRUCT;

// **** D0F0xBC_xE00030A4 Register Definition ****
// Address
#define D0F0xBC_xE00030A4_ADDRESS                               0xe00030a4

// Type
#define D0F0xBC_xE00030A4_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE00030A4_Reserved_15_0_OFFSET                  0
#define D0F0xBC_xE00030A4_Reserved_15_0_WIDTH                   16
#define D0F0xBC_xE00030A4_Reserved_15_0_MASK                    0xffff
#define D0F0xBC_xE00030A4_SmuProtectedMode_OFFSET               16
#define D0F0xBC_xE00030A4_SmuProtectedMode_WIDTH                1
#define D0F0xBC_xE00030A4_SmuProtectedMode_MASK                 0x10000
#define D0F0xBC_xE00030A4_Reserved_31_17_OFFSET                 17
#define D0F0xBC_xE00030A4_Reserved_31_17_WIDTH                  15
#define D0F0xBC_xE00030A4_Reserved_31_17_MASK                   0xfffe0000

/// D0F0xBC_xE00030A4
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_15_0:16; ///<
    UINT32                                         SmuProtectedMode:1 ; ///<
    UINT32                                           Reserved_31_17:15; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE00030A4_STRUCT;

// **** D0F0xBC_xE0104040 Register Definition ****
// Address
#define D0F0xBC_xE0104040_ADDRESS                               0xe0104040

// Type
#define D0F0xBC_xE0104040_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0104040_Reserved_6_0_OFFSET                   0
#define D0F0xBC_xE0104040_Reserved_6_0_WIDTH                    7
#define D0F0xBC_xE0104040_Reserved_6_0_MASK                     0x7f
#define D0F0xBC_xE0104040_DeviceID_OFFSET                       7
#define D0F0xBC_xE0104040_DeviceID_WIDTH                        16
#define D0F0xBC_xE0104040_DeviceID_MASK                         0x7fff80
#define D0F0xBC_xE0104040_Reserved_31_17_OFFSET                 23
#define D0F0xBC_xE0104040_Reserved_31_17_WIDTH                  9
#define D0F0xBC_xE0104040_Reserved_31_17_MASK                   0xff800000

/// D0F0xBC_xE0104040
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_6_0:7;  ///<
    UINT32                                                DeviceID:16 ; ///<
    UINT32                                           Reserved_31_23:9; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0104040_STRUCT;

// **** D0F0xBC_xE0104168 Register Definition ****
// Address
#define D0F0xBC_xE0104168_ADDRESS                               0xe0104168

// Type
#define D0F0xBC_xE0104168_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0104168_GnbLPML15_5_0_OFFSET                  0
#define D0F0xBC_xE0104168_GnbLPML15_5_0_WIDTH                   6
#define D0F0xBC_xE0104168_GnbLPML15_5_0_MASK                    0x3f
#define D0F0xBC_xE0104168_MemClkVid0_7_0_OFFSET                 6
#define D0F0xBC_xE0104168_MemClkVid0_7_0_WIDTH                  8
#define D0F0xBC_xE0104168_MemClkVid0_7_0_MASK                   0x3fc0
#define D0F0xBC_xE0104168_MemClkVid1_7_0_OFFSET                 14
#define D0F0xBC_xE0104168_MemClkVid1_7_0_WIDTH                  8
#define D0F0xBC_xE0104168_MemClkVid1_7_0_MASK                   0x3fc000
#define D0F0xBC_xE0104168_MemClkVid2_7_0_OFFSET                 22
#define D0F0xBC_xE0104168_MemClkVid2_7_0_WIDTH                  8
#define D0F0xBC_xE0104168_MemClkVid2_7_0_MASK                   0x3fc00000
#define D0F0xBC_xE0104168_MemClkVid3_1_0_OFFSET                 30
#define D0F0xBC_xE0104168_MemClkVid3_1_0_WIDTH                  2
#define D0F0xBC_xE0104168_MemClkVid3_1_0_MASK                   0xc0000000

/// D0F0xBC_xE0104168
typedef union {
  struct {                                                              ///<
    UINT32                                            GnbLPML15_5_0:6 ; ///<
    UINT32                                           MemClkVid0_7_0:8 ; ///<
    UINT32                                           MemClkVid1_7_0:8 ; ///<
    UINT32                                           MemClkVid2_7_0:8 ; ///<
    UINT32                                           MemClkVid3_1_0:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0104168_STRUCT;

// **** D0F0xBC_xE010416C Register Definition ****
// Address
#define D0F0xBC_xE010416C_ADDRESS                               0xe010416c

// Type
#define D0F0xBC_xE010416C_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE010416C_MemClkVid3_7_2_OFFSET                 0
#define D0F0xBC_xE010416C_MemClkVid3_7_2_WIDTH                  6
#define D0F0xBC_xE010416C_MemClkVid3_7_2_MASK                   0x3f
#define D0F0xBC_xE010416C_MemClkVid4_7_0_OFFSET                 6
#define D0F0xBC_xE010416C_MemClkVid4_7_0_WIDTH                  8
#define D0F0xBC_xE010416C_MemClkVid4_7_0_MASK                   0x3fc0
#define D0F0xBC_xE010416C_MemClkVid5_7_0_OFFSET                 14
#define D0F0xBC_xE010416C_MemClkVid5_7_0_WIDTH                  8
#define D0F0xBC_xE010416C_MemClkVid5_7_0_MASK                   0x3fc000
#define D0F0xBC_xE010416C_MemClkVid6_7_0_OFFSET                 22
#define D0F0xBC_xE010416C_MemClkVid6_7_0_WIDTH                  8
#define D0F0xBC_xE010416C_MemClkVid6_7_0_MASK                   0x3fc00000
#define D0F0xBC_xE010416C_MemClkVid7_1_0_OFFSET                 30
#define D0F0xBC_xE010416C_MemClkVid7_1_0_WIDTH                  2
#define D0F0xBC_xE010416C_MemClkVid7_1_0_MASK                   0xc0000000

/// D0F0xBC_xE010416C
typedef union {
  struct {                                                              ///<
    UINT32                                           MemClkVid3_7_2:6 ; ///<
    UINT32                                           MemClkVid4_7_0:8 ; ///<
    UINT32                                           MemClkVid5_7_0:8 ; ///<
    UINT32                                           MemClkVid6_7_0:8 ; ///<
    UINT32                                           MemClkVid7_1_0:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE010416C_STRUCT;

// **** D0F0xBC_xE0104170 Register Definition ****
// Address
#define D0F0xBC_xE0104170_ADDRESS                               0xe0104170

// Type
#define D0F0xBC_xE0104170_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0104170_MemClkVid7_7_2_OFFSET                 0
#define D0F0xBC_xE0104170_MemClkVid7_7_2_WIDTH                  6
#define D0F0xBC_xE0104170_MemClkVid7_7_2_MASK                   0x3f
#define D0F0xBC_xE0104170_MemClkVid8_7_0_OFFSET                 6
#define D0F0xBC_xE0104170_MemClkVid8_7_0_WIDTH                  8
#define D0F0xBC_xE0104170_MemClkVid8_7_0_MASK                   0x3fc0
#define D0F0xBC_xE0104170_AmbientTempBase_7_0_OFFSET            14
#define D0F0xBC_xE0104170_AmbientTempBase_7_0_WIDTH             8
#define D0F0xBC_xE0104170_AmbientTempBase_7_0_MASK              0x3fc000
#define D0F0xBC_xE0104170_SMU_SPARE31_9_0_OFFSET                22
#define D0F0xBC_xE0104170_SMU_SPARE31_9_0_WIDTH                 10
#define D0F0xBC_xE0104170_SMU_SPARE31_9_0_MASK                  0xffc00000

/// D0F0xBC_xE0104170
typedef union {
  struct {                                                              ///<
    UINT32                                           MemClkVid7_7_2:6 ; ///<
    UINT32                                           MemClkVid8_7_0:8 ; ///<
    UINT32                                      AmbientTempBase_7_0:8 ; ///<
    UINT32                                          SMU_SPARE31_9_0:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0104170_STRUCT;

// **** D0F0xBC_xE0300000 Register Definition ****
// Address
#define D0F0xBC_xE0300000_ADDRESS                               0xe0300000

// Type
#define D0F0xBC_xE0300000_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300000_FsmAddr_OFFSET                        0
#define D0F0xBC_xE0300000_FsmAddr_WIDTH                         8
#define D0F0xBC_xE0300000_FsmAddr_MASK                          0xff
#define D0F0xBC_xE0300000_PowerDown_OFFSET                      8
#define D0F0xBC_xE0300000_PowerDown_WIDTH                       1
#define D0F0xBC_xE0300000_PowerDown_MASK                        0x100
#define D0F0xBC_xE0300000_PowerUp_OFFSET                        9
#define D0F0xBC_xE0300000_PowerUp_WIDTH                         1
#define D0F0xBC_xE0300000_PowerUp_MASK                          0x200
#define D0F0xBC_xE0300000_P1Select_OFFSET                       10
#define D0F0xBC_xE0300000_P1Select_WIDTH                        1
#define D0F0xBC_xE0300000_P1Select_MASK                         0x400
#define D0F0xBC_xE0300000_P2Select_OFFSET                       11
#define D0F0xBC_xE0300000_P2Select_WIDTH                        1
#define D0F0xBC_xE0300000_P2Select_MASK                         0x800
#define D0F0xBC_xE0300000_WriteOp_OFFSET                        12
#define D0F0xBC_xE0300000_WriteOp_WIDTH                         1
#define D0F0xBC_xE0300000_WriteOp_MASK                          0x1000
#define D0F0xBC_xE0300000_ReadOp_OFFSET                         13
#define D0F0xBC_xE0300000_ReadOp_WIDTH                          1
#define D0F0xBC_xE0300000_ReadOp_MASK                           0x2000
#define D0F0xBC_xE0300000_Reserved_27_14_OFFSET                 14
#define D0F0xBC_xE0300000_Reserved_27_14_WIDTH                  14
#define D0F0xBC_xE0300000_Reserved_27_14_MASK                   0xfffc000
#define D0F0xBC_xE0300000_RegAddr_OFFSET                        28
#define D0F0xBC_xE0300000_RegAddr_WIDTH                         4
#define D0F0xBC_xE0300000_RegAddr_MASK                          0xf0000000

/// D0F0xBC_xE0300000
typedef union {
  struct {                                                              ///<
    UINT32                                                  FsmAddr:8 ; ///<
    UINT32                                                PowerDown:1 ; ///<
    UINT32                                                  PowerUp:1 ; ///<
    UINT32                                                 P1Select:1 ; ///<
    UINT32                                                 P2Select:1 ; ///<
    UINT32                                                  WriteOp:1 ; ///<
    UINT32                                                   ReadOp:1 ; ///<
    UINT32                                           Reserved_27_14:14; ///<
    UINT32                                                  RegAddr:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300000_STRUCT;

// **** D0F0xBC_xE0300004 Register Definition ****
// Address
#define D0F0xBC_xE0300004_ADDRESS                               0xe0300004

// Type
#define D0F0xBC_xE0300004_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300004_Write_value_OFFSET                    0
#define D0F0xBC_xE0300004_Write_value_WIDTH                     32
#define D0F0xBC_xE0300004_Write_value_MASK                      0xffffffff

/// D0F0xBC_xE0300004
typedef union {
  struct {                                                              ///<
    UINT32                                              Write_value:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300004_STRUCT;

// **** D0F0xBC_xE0300008 Register Definition ****
// Address
#define D0F0xBC_xE0300008_ADDRESS                               0xe0300008

// Type
#define D0F0xBC_xE0300008_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300008_ReadValue_OFFSET                      0
#define D0F0xBC_xE0300008_ReadValue_WIDTH                       24
#define D0F0xBC_xE0300008_ReadValue_MASK                        0xffffff
#define D0F0xBC_xE0300008_ReadValid_OFFSET                      24
#define D0F0xBC_xE0300008_ReadValid_WIDTH                       1
#define D0F0xBC_xE0300008_ReadValid_MASK                        0x1000000
#define D0F0xBC_xE0300008_Reserved_31_25_OFFSET                 25
#define D0F0xBC_xE0300008_Reserved_31_25_WIDTH                  7
#define D0F0xBC_xE0300008_Reserved_31_25_MASK                   0xfe000000

/// D0F0xBC_xE0300008
typedef union {
  struct {                                                              ///<
    UINT32                                                ReadValue:24; ///<
    UINT32                                                ReadValid:1 ; ///<
    UINT32                                           Reserved_31_25:7 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300008_STRUCT;

// **** D0F0xBC_xE030000C Register Definition ****
// Address
#define D0F0xBC_xE030000C_ADDRESS                               0xe030000c

// Type
#define D0F0xBC_xE030000C_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE030000C_FsmAddr_OFFSET                        0
#define D0F0xBC_xE030000C_FsmAddr_WIDTH                         8
#define D0F0xBC_xE030000C_FsmAddr_MASK                          0xff
#define D0F0xBC_xE030000C_PowerDown_OFFSET                      8
#define D0F0xBC_xE030000C_PowerDown_WIDTH                       1
#define D0F0xBC_xE030000C_PowerDown_MASK                        0x100
#define D0F0xBC_xE030000C_PowerUp_OFFSET                        9
#define D0F0xBC_xE030000C_PowerUp_WIDTH                         1
#define D0F0xBC_xE030000C_PowerUp_MASK                          0x200
#define D0F0xBC_xE030000C_P1Select_OFFSET                       10
#define D0F0xBC_xE030000C_P1Select_WIDTH                        1
#define D0F0xBC_xE030000C_P1Select_MASK                         0x400
#define D0F0xBC_xE030000C_P2Select_OFFSET                       11
#define D0F0xBC_xE030000C_P2Select_WIDTH                        1
#define D0F0xBC_xE030000C_P2Select_MASK                         0x800
#define D0F0xBC_xE030000C_WriteOp_OFFSET                        12
#define D0F0xBC_xE030000C_WriteOp_WIDTH                         1
#define D0F0xBC_xE030000C_WriteOp_MASK                          0x1000
#define D0F0xBC_xE030000C_ReadOp_OFFSET                         13
#define D0F0xBC_xE030000C_ReadOp_WIDTH                          1
#define D0F0xBC_xE030000C_ReadOp_MASK                           0x2000
#define D0F0xBC_xE030000C_Reserved_27_14_OFFSET                 14
#define D0F0xBC_xE030000C_Reserved_27_14_WIDTH                  14
#define D0F0xBC_xE030000C_Reserved_27_14_MASK                   0xfffc000
#define D0F0xBC_xE030000C_RegAddr_OFFSET                        28
#define D0F0xBC_xE030000C_RegAddr_WIDTH                         4
#define D0F0xBC_xE030000C_RegAddr_MASK                          0xf0000000

/// D0F0xBC_xE030000C
typedef union {
  struct {                                                              ///<
    UINT32                                                  FsmAddr:8 ; ///<
    UINT32                                                PowerDown:1 ; ///<
    UINT32                                                  PowerUp:1 ; ///<
    UINT32                                                 P1Select:1 ; ///<
    UINT32                                                 P2Select:1 ; ///<
    UINT32                                                  WriteOp:1 ; ///<
    UINT32                                                   ReadOp:1 ; ///<
    UINT32                                           Reserved_27_14:14; ///<
    UINT32                                                  RegAddr:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE030000C_STRUCT;

// **** D0F0xBC_xE0300010 Register Definition ****
// Address
#define D0F0xBC_xE0300010_ADDRESS                               0xe0300010

// Type
#define D0F0xBC_xE0300010_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300010_Write_value_OFFSET                    0
#define D0F0xBC_xE0300010_Write_value_WIDTH                     32
#define D0F0xBC_xE0300010_Write_value_MASK                      0xffffffff

/// D0F0xBC_xE0300010
typedef union {
  struct {                                                              ///<
    UINT32                                              Write_value:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300010_STRUCT;

// **** D0F0xBC_xE0300018 Register Definition ****
// Address
#define D0F0xBC_xE0300018_ADDRESS                               0xe0300018

// Type
#define D0F0xBC_xE0300018_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300018_FsmAddr_OFFSET                        0
#define D0F0xBC_xE0300018_FsmAddr_WIDTH                         8
#define D0F0xBC_xE0300018_FsmAddr_MASK                          0xff
#define D0F0xBC_xE0300018_PowerDown_OFFSET                      8
#define D0F0xBC_xE0300018_PowerDown_WIDTH                       1
#define D0F0xBC_xE0300018_PowerDown_MASK                        0x100
#define D0F0xBC_xE0300018_PowerUp_OFFSET                        9
#define D0F0xBC_xE0300018_PowerUp_WIDTH                         1
#define D0F0xBC_xE0300018_PowerUp_MASK                          0x200
#define D0F0xBC_xE0300018_P1Select_OFFSET                       10
#define D0F0xBC_xE0300018_P1Select_WIDTH                        1
#define D0F0xBC_xE0300018_P1Select_MASK                         0x400
#define D0F0xBC_xE0300018_P2Select_OFFSET                       11
#define D0F0xBC_xE0300018_P2Select_WIDTH                        1
#define D0F0xBC_xE0300018_P2Select_MASK                         0x800
#define D0F0xBC_xE0300018_WriteOp_OFFSET                        12
#define D0F0xBC_xE0300018_WriteOp_WIDTH                         1
#define D0F0xBC_xE0300018_WriteOp_MASK                          0x1000
#define D0F0xBC_xE0300018_ReadOp_OFFSET                         13
#define D0F0xBC_xE0300018_ReadOp_WIDTH                          1
#define D0F0xBC_xE0300018_ReadOp_MASK                           0x2000
#define D0F0xBC_xE0300018_Reserved_27_14_OFFSET                 14
#define D0F0xBC_xE0300018_Reserved_27_14_WIDTH                  14
#define D0F0xBC_xE0300018_Reserved_27_14_MASK                   0xfffc000
#define D0F0xBC_xE0300018_RegAddr_OFFSET                        28
#define D0F0xBC_xE0300018_RegAddr_WIDTH                         4
#define D0F0xBC_xE0300018_RegAddr_MASK                          0xf0000000

/// D0F0xBC_xE0300018
typedef union {
  struct {                                                              ///<
    UINT32                                                  FsmAddr:8 ; ///<
    UINT32                                                PowerDown:1 ; ///<
    UINT32                                                  PowerUp:1 ; ///<
    UINT32                                                 P1Select:1 ; ///<
    UINT32                                                 P2Select:1 ; ///<
    UINT32                                                  WriteOp:1 ; ///<
    UINT32                                                   ReadOp:1 ; ///<
    UINT32                                           Reserved_27_14:14; ///<
    UINT32                                                  RegAddr:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300018_STRUCT;

// **** D0F0xBC_xE030001C Register Definition ****
// Address
#define D0F0xBC_xE030001C_ADDRESS                               0xe030001c

// Type
#define D0F0xBC_xE030001C_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE030001C_Write_value_OFFSET                    0
#define D0F0xBC_xE030001C_Write_value_WIDTH                     32
#define D0F0xBC_xE030001C_Write_value_MASK                      0xffffffff

/// D0F0xBC_xE030001C
typedef union {
  struct {                                                              ///<
    UINT32                                              Write_value:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE030001C_STRUCT;

// **** D0F0xBC_xE0300024 Register Definition ****
// Address
#define D0F0xBC_xE0300024_ADDRESS                               0xe0300024

// Type
#define D0F0xBC_xE0300024_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300024_FsmAddr_OFFSET                        0
#define D0F0xBC_xE0300024_FsmAddr_WIDTH                         8
#define D0F0xBC_xE0300024_FsmAddr_MASK                          0xff
#define D0F0xBC_xE0300024_PowerDown_OFFSET                      8
#define D0F0xBC_xE0300024_PowerDown_WIDTH                       1
#define D0F0xBC_xE0300024_PowerDown_MASK                        0x100
#define D0F0xBC_xE0300024_PowerUp_OFFSET                        9
#define D0F0xBC_xE0300024_PowerUp_WIDTH                         1
#define D0F0xBC_xE0300024_PowerUp_MASK                          0x200
#define D0F0xBC_xE0300024_P1Select_OFFSET                       10
#define D0F0xBC_xE0300024_P1Select_WIDTH                        1
#define D0F0xBC_xE0300024_P1Select_MASK                         0x400
#define D0F0xBC_xE0300024_P2Select_OFFSET                       11
#define D0F0xBC_xE0300024_P2Select_WIDTH                        1
#define D0F0xBC_xE0300024_P2Select_MASK                         0x800
#define D0F0xBC_xE0300024_WriteOp_OFFSET                        12
#define D0F0xBC_xE0300024_WriteOp_WIDTH                         1
#define D0F0xBC_xE0300024_WriteOp_MASK                          0x1000
#define D0F0xBC_xE0300024_ReadOp_OFFSET                         13
#define D0F0xBC_xE0300024_ReadOp_WIDTH                          1
#define D0F0xBC_xE0300024_ReadOp_MASK                           0x2000
#define D0F0xBC_xE0300024_Reserved_27_14_OFFSET                 14
#define D0F0xBC_xE0300024_Reserved_27_14_WIDTH                  14
#define D0F0xBC_xE0300024_Reserved_27_14_MASK                   0xfffc000
#define D0F0xBC_xE0300024_RegAddr_OFFSET                        28
#define D0F0xBC_xE0300024_RegAddr_WIDTH                         4
#define D0F0xBC_xE0300024_RegAddr_MASK                          0xf0000000

/// D0F0xBC_xE0300024
typedef union {
  struct {                                                              ///<
    UINT32                                                  FsmAddr:8 ; ///<
    UINT32                                                PowerDown:1 ; ///<
    UINT32                                                  PowerUp:1 ; ///<
    UINT32                                                 P1Select:1 ; ///<
    UINT32                                                 P2Select:1 ; ///<
    UINT32                                                  WriteOp:1 ; ///<
    UINT32                                                   ReadOp:1 ; ///<
    UINT32                                           Reserved_27_14:14; ///<
    UINT32                                                  RegAddr:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300024_STRUCT;

// **** D0F0xBC_xE0300028 Register Definition ****
// Address
#define D0F0xBC_xE0300028_ADDRESS                               0xe0300028

// Type
#define D0F0xBC_xE0300028_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300028_Write_value_OFFSET                    0
#define D0F0xBC_xE0300028_Write_value_WIDTH                     32
#define D0F0xBC_xE0300028_Write_value_MASK                      0xffffffff

/// D0F0xBC_xE0300028
typedef union {
  struct {                                                              ///<
    UINT32                                              Write_value:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300028_STRUCT;

// **** D0F0xBC_xE0300030 Register Definition ****
// Address
#define D0F0xBC_xE0300030_ADDRESS                               0xe0300030

// Type
#define D0F0xBC_xE0300030_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300030_FsmAddr_OFFSET                        0
#define D0F0xBC_xE0300030_FsmAddr_WIDTH                         8
#define D0F0xBC_xE0300030_FsmAddr_MASK                          0xff
#define D0F0xBC_xE0300030_PowerDown_OFFSET                      8
#define D0F0xBC_xE0300030_PowerDown_WIDTH                       1
#define D0F0xBC_xE0300030_PowerDown_MASK                        0x100
#define D0F0xBC_xE0300030_PowerUp_OFFSET                        9
#define D0F0xBC_xE0300030_PowerUp_WIDTH                         1
#define D0F0xBC_xE0300030_PowerUp_MASK                          0x200
#define D0F0xBC_xE0300030_P1Select_OFFSET                       10
#define D0F0xBC_xE0300030_P1Select_WIDTH                        1
#define D0F0xBC_xE0300030_P1Select_MASK                         0x400
#define D0F0xBC_xE0300030_P2Select_OFFSET                       11
#define D0F0xBC_xE0300030_P2Select_WIDTH                        1
#define D0F0xBC_xE0300030_P2Select_MASK                         0x800
#define D0F0xBC_xE0300030_WriteOp_OFFSET                        12
#define D0F0xBC_xE0300030_WriteOp_WIDTH                         1
#define D0F0xBC_xE0300030_WriteOp_MASK                          0x1000
#define D0F0xBC_xE0300030_ReadOp_OFFSET                         13
#define D0F0xBC_xE0300030_ReadOp_WIDTH                          1
#define D0F0xBC_xE0300030_ReadOp_MASK                           0x2000
#define D0F0xBC_xE0300030_Reserved_27_14_OFFSET                 14
#define D0F0xBC_xE0300030_Reserved_27_14_WIDTH                  14
#define D0F0xBC_xE0300030_Reserved_27_14_MASK                   0xfffc000
#define D0F0xBC_xE0300030_RegAddr_OFFSET                        28
#define D0F0xBC_xE0300030_RegAddr_WIDTH                         4
#define D0F0xBC_xE0300030_RegAddr_MASK                          0xf0000000

/// D0F0xBC_xE0300030
typedef union {
  struct {                                                              ///<
    UINT32                                                  FsmAddr:8 ; ///<
    UINT32                                                PowerDown:1 ; ///<
    UINT32                                                  PowerUp:1 ; ///<
    UINT32                                                 P1Select:1 ; ///<
    UINT32                                                 P2Select:1 ; ///<
    UINT32                                                  WriteOp:1 ; ///<
    UINT32                                                   ReadOp:1 ; ///<
    UINT32                                           Reserved_27_14:14; ///<
    UINT32                                                  RegAddr:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300030_STRUCT;

// **** D0F0xBC_xE0300034 Register Definition ****
// Address
#define D0F0xBC_xE0300034_ADDRESS                               0xe0300034

// Type
#define D0F0xBC_xE0300034_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300034_Write_value_OFFSET                    0
#define D0F0xBC_xE0300034_Write_value_WIDTH                     32
#define D0F0xBC_xE0300034_Write_value_MASK                      0xffffffff

/// D0F0xBC_xE0300034
typedef union {
  struct {                                                              ///<
    UINT32                                              Write_value:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300034_STRUCT;

// **** D0F0xBC_xE030003C Register Definition ****
// Address
#define D0F0xBC_xE030003C_ADDRESS                               0xe030003c

// Type
#define D0F0xBC_xE030003C_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE030003C_FsmAddr_OFFSET                        0
#define D0F0xBC_xE030003C_FsmAddr_WIDTH                         8
#define D0F0xBC_xE030003C_FsmAddr_MASK                          0xff
#define D0F0xBC_xE030003C_PowerDown_OFFSET                      8
#define D0F0xBC_xE030003C_PowerDown_WIDTH                       1
#define D0F0xBC_xE030003C_PowerDown_MASK                        0x100
#define D0F0xBC_xE030003C_PowerUp_OFFSET                        9
#define D0F0xBC_xE030003C_PowerUp_WIDTH                         1
#define D0F0xBC_xE030003C_PowerUp_MASK                          0x200
#define D0F0xBC_xE030003C_P1Select_OFFSET                       10
#define D0F0xBC_xE030003C_P1Select_WIDTH                        1
#define D0F0xBC_xE030003C_P1Select_MASK                         0x400
#define D0F0xBC_xE030003C_P2Select_OFFSET                       11
#define D0F0xBC_xE030003C_P2Select_WIDTH                        1
#define D0F0xBC_xE030003C_P2Select_MASK                         0x800
#define D0F0xBC_xE030003C_WriteOp_OFFSET                        12
#define D0F0xBC_xE030003C_WriteOp_WIDTH                         1
#define D0F0xBC_xE030003C_WriteOp_MASK                          0x1000
#define D0F0xBC_xE030003C_ReadOp_OFFSET                         13
#define D0F0xBC_xE030003C_ReadOp_WIDTH                          1
#define D0F0xBC_xE030003C_ReadOp_MASK                           0x2000
#define D0F0xBC_xE030003C_Reserved_27_14_OFFSET                 14
#define D0F0xBC_xE030003C_Reserved_27_14_WIDTH                  14
#define D0F0xBC_xE030003C_Reserved_27_14_MASK                   0xfffc000
#define D0F0xBC_xE030003C_RegAddr_OFFSET                        28
#define D0F0xBC_xE030003C_RegAddr_WIDTH                         4
#define D0F0xBC_xE030003C_RegAddr_MASK                          0xf0000000

/// D0F0xBC_xE030003C
typedef union {
  struct {                                                              ///<
    UINT32                                                  FsmAddr:8 ; ///<
    UINT32                                                PowerDown:1 ; ///<
    UINT32                                                  PowerUp:1 ; ///<
    UINT32                                                 P1Select:1 ; ///<
    UINT32                                                 P2Select:1 ; ///<
    UINT32                                                  WriteOp:1 ; ///<
    UINT32                                                   ReadOp:1 ; ///<
    UINT32                                           Reserved_27_14:14; ///<
    UINT32                                                  RegAddr:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE030003C_STRUCT;

// **** D0F0xBC_xE0300040 Register Definition ****
// Address
#define D0F0xBC_xE0300040_ADDRESS                               0xe0300040

// Type
#define D0F0xBC_xE0300040_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300040_Write_value_OFFSET                    0
#define D0F0xBC_xE0300040_Write_value_WIDTH                     32
#define D0F0xBC_xE0300040_Write_value_MASK                      0xffffffff

/// D0F0xBC_xE0300040
typedef union {
  struct {                                                              ///<
    UINT32                                              Write_value:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300040_STRUCT;

// **** D0F0xBC_xE0300054 Register Definition ****
// Address
#define D0F0xBC_xE0300054_ADDRESS                               0xe0300054

// Type
#define D0F0xBC_xE0300054_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300054_FsmAddr_OFFSET                        0
#define D0F0xBC_xE0300054_FsmAddr_WIDTH                         8
#define D0F0xBC_xE0300054_FsmAddr_MASK                          0xff
#define D0F0xBC_xE0300054_PowerDown_OFFSET                      8
#define D0F0xBC_xE0300054_PowerDown_WIDTH                       1
#define D0F0xBC_xE0300054_PowerDown_MASK                        0x100
#define D0F0xBC_xE0300054_PowerUp_OFFSET                        9
#define D0F0xBC_xE0300054_PowerUp_WIDTH                         1
#define D0F0xBC_xE0300054_PowerUp_MASK                          0x200
#define D0F0xBC_xE0300054_P1Select_OFFSET                       10
#define D0F0xBC_xE0300054_P1Select_WIDTH                        1
#define D0F0xBC_xE0300054_P1Select_MASK                         0x400
#define D0F0xBC_xE0300054_P2Select_OFFSET                       11
#define D0F0xBC_xE0300054_P2Select_WIDTH                        1
#define D0F0xBC_xE0300054_P2Select_MASK                         0x800
#define D0F0xBC_xE0300054_WriteOp_OFFSET                        12
#define D0F0xBC_xE0300054_WriteOp_WIDTH                         1
#define D0F0xBC_xE0300054_WriteOp_MASK                          0x1000
#define D0F0xBC_xE0300054_ReadOp_OFFSET                         13
#define D0F0xBC_xE0300054_ReadOp_WIDTH                          1
#define D0F0xBC_xE0300054_ReadOp_MASK                           0x2000
#define D0F0xBC_xE0300054_Reserved_27_14_OFFSET                 14
#define D0F0xBC_xE0300054_Reserved_27_14_WIDTH                  14
#define D0F0xBC_xE0300054_Reserved_27_14_MASK                   0xfffc000
#define D0F0xBC_xE0300054_RegAddr_OFFSET                        28
#define D0F0xBC_xE0300054_RegAddr_WIDTH                         4
#define D0F0xBC_xE0300054_RegAddr_MASK                          0xf0000000

/// D0F0xBC_xE0300054
typedef union {
  struct {                                                              ///<
    UINT32                                                  FsmAddr:8 ; ///<
    UINT32                                                PowerDown:1 ; ///<
    UINT32                                                  PowerUp:1 ; ///<
    UINT32                                                 P1Select:1 ; ///<
    UINT32                                                 P2Select:1 ; ///<
    UINT32                                                  WriteOp:1 ; ///<
    UINT32                                                   ReadOp:1 ; ///<
    UINT32                                           Reserved_27_14:14; ///<
    UINT32                                                  RegAddr:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300054_STRUCT;

// **** D0F0xBC_xE0300058 Register Definition ****
// Address
#define D0F0xBC_xE0300058_ADDRESS                               0xe0300058

// Type
#define D0F0xBC_xE0300058_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300058_WriteValue_OFFSET                     0
#define D0F0xBC_xE0300058_WriteValue_WIDTH                      32
#define D0F0xBC_xE0300058_WriteValue_MASK                       0xffffffff

/// D0F0xBC_xE0300058
typedef union {
  struct {                                                              ///<
    UINT32                                               WriteValue:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300058_STRUCT;

// **** D0F0xBC_xE0300070 Register Definition ****
// Address
#define D0F0xBC_xE0300070_ADDRESS                               0xe0300070

// Type
#define D0F0xBC_xE0300070_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300070_FsmAddr_OFFSET                        0
#define D0F0xBC_xE0300070_FsmAddr_WIDTH                         8
#define D0F0xBC_xE0300070_FsmAddr_MASK                          0xff
#define D0F0xBC_xE0300070_PowerDown_OFFSET                      8
#define D0F0xBC_xE0300070_PowerDown_WIDTH                       1
#define D0F0xBC_xE0300070_PowerDown_MASK                        0x100
#define D0F0xBC_xE0300070_PowerUp_OFFSET                        9
#define D0F0xBC_xE0300070_PowerUp_WIDTH                         1
#define D0F0xBC_xE0300070_PowerUp_MASK                          0x200
#define D0F0xBC_xE0300070_P1Select_OFFSET                       10
#define D0F0xBC_xE0300070_P1Select_WIDTH                        1
#define D0F0xBC_xE0300070_P1Select_MASK                         0x400
#define D0F0xBC_xE0300070_P2Select_OFFSET                       11
#define D0F0xBC_xE0300070_P2Select_WIDTH                        1
#define D0F0xBC_xE0300070_P2Select_MASK                         0x800
#define D0F0xBC_xE0300070_WriteOp_OFFSET                        12
#define D0F0xBC_xE0300070_WriteOp_WIDTH                         1
#define D0F0xBC_xE0300070_WriteOp_MASK                          0x1000
#define D0F0xBC_xE0300070_ReadOp_OFFSET                         13
#define D0F0xBC_xE0300070_ReadOp_WIDTH                          1
#define D0F0xBC_xE0300070_ReadOp_MASK                           0x2000
#define D0F0xBC_xE0300070_Reserved_27_14_OFFSET                 14
#define D0F0xBC_xE0300070_Reserved_27_14_WIDTH                  14
#define D0F0xBC_xE0300070_Reserved_27_14_MASK                   0xfffc000
#define D0F0xBC_xE0300070_RegAddr_OFFSET                        28
#define D0F0xBC_xE0300070_RegAddr_WIDTH                         4
#define D0F0xBC_xE0300070_RegAddr_MASK                          0xf0000000

/// D0F0xBC_xE0300070
typedef union {
  struct {                                                              ///<
    UINT32                                                  FsmAddr:8 ; ///<
    UINT32                                                PowerDown:1 ; ///<
    UINT32                                                  PowerUp:1 ; ///<
    UINT32                                                 P1Select:1 ; ///<
    UINT32                                                 P2Select:1 ; ///<
    UINT32                                                  WriteOp:1 ; ///<
    UINT32                                                   ReadOp:1 ; ///<
    UINT32                                           Reserved_27_14:14; ///<
    UINT32                                                  RegAddr:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300070_STRUCT;

// **** D0F0xBC_xE0300074 Register Definition ****
// Address
#define D0F0xBC_xE0300074_ADDRESS                               0xe0300074

// Type
#define D0F0xBC_xE0300074_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300074_WriteValue_OFFSET                     0
#define D0F0xBC_xE0300074_WriteValue_WIDTH                      32
#define D0F0xBC_xE0300074_WriteValue_MASK                       0xffffffff

/// D0F0xBC_xE0300074
typedef union {
  struct {                                                              ///<
    UINT32                                               WriteValue:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300074_STRUCT;

// **** D0F0xBC_xE030008C Register Definition ****
// Address
#define D0F0xBC_xE030008C_ADDRESS                               0xe030008c

// Type
#define D0F0xBC_xE030008C_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE030008C_FsmAddr_OFFSET                        0
#define D0F0xBC_xE030008C_FsmAddr_WIDTH                         8
#define D0F0xBC_xE030008C_FsmAddr_MASK                          0xff
#define D0F0xBC_xE030008C_PowerDown_OFFSET                      8
#define D0F0xBC_xE030008C_PowerDown_WIDTH                       1
#define D0F0xBC_xE030008C_PowerDown_MASK                        0x100
#define D0F0xBC_xE030008C_PowerUp_OFFSET                        9
#define D0F0xBC_xE030008C_PowerUp_WIDTH                         1
#define D0F0xBC_xE030008C_PowerUp_MASK                          0x200
#define D0F0xBC_xE030008C_P1Select_OFFSET                       10
#define D0F0xBC_xE030008C_P1Select_WIDTH                        1
#define D0F0xBC_xE030008C_P1Select_MASK                         0x400
#define D0F0xBC_xE030008C_P2Select_OFFSET                       11
#define D0F0xBC_xE030008C_P2Select_WIDTH                        1
#define D0F0xBC_xE030008C_P2Select_MASK                         0x800
#define D0F0xBC_xE030008C_WriteOp_OFFSET                        12
#define D0F0xBC_xE030008C_WriteOp_WIDTH                         1
#define D0F0xBC_xE030008C_WriteOp_MASK                          0x1000
#define D0F0xBC_xE030008C_ReadOp_OFFSET                         13
#define D0F0xBC_xE030008C_ReadOp_WIDTH                          1
#define D0F0xBC_xE030008C_ReadOp_MASK                           0x2000
#define D0F0xBC_xE030008C_Reserved_27_14_OFFSET                 14
#define D0F0xBC_xE030008C_Reserved_27_14_WIDTH                  14
#define D0F0xBC_xE030008C_Reserved_27_14_MASK                   0xfffc000
#define D0F0xBC_xE030008C_RegAddr_OFFSET                        28
#define D0F0xBC_xE030008C_RegAddr_WIDTH                         4
#define D0F0xBC_xE030008C_RegAddr_MASK                          0xf0000000

/// D0F0xBC_xE030008C
typedef union {
  struct {                                                              ///<
    UINT32                                                  FsmAddr:8 ; ///<
    UINT32                                                PowerDown:1 ; ///<
    UINT32                                                  PowerUp:1 ; ///<
    UINT32                                                 P1Select:1 ; ///<
    UINT32                                                 P2Select:1 ; ///<
    UINT32                                                  WriteOp:1 ; ///<
    UINT32                                                   ReadOp:1 ; ///<
    UINT32                                           Reserved_27_14:14; ///<
    UINT32                                                  RegAddr:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE030008C_STRUCT;

// **** D0F0xBC_xE0300090 Register Definition ****
// Address
#define D0F0xBC_xE0300090_ADDRESS                               0xe0300090

// Type
#define D0F0xBC_xE0300090_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300090_WriteValue_OFFSET                     0
#define D0F0xBC_xE0300090_WriteValue_WIDTH                      32
#define D0F0xBC_xE0300090_WriteValue_MASK                       0xffffffff

/// D0F0xBC_xE0300090
typedef union {
  struct {                                                              ///<
    UINT32                                               WriteValue:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300090_STRUCT;

// **** D0F0xBC_xE03000A8 Register Definition ****
// Address
#define D0F0xBC_xE03000A8_ADDRESS                               0xe03000a8

// Type
#define D0F0xBC_xE03000A8_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE03000A8_FsmAddr_OFFSET                        0
#define D0F0xBC_xE03000A8_FsmAddr_WIDTH                         8
#define D0F0xBC_xE03000A8_FsmAddr_MASK                          0xff
#define D0F0xBC_xE03000A8_PowerDown_OFFSET                      8
#define D0F0xBC_xE03000A8_PowerDown_WIDTH                       1
#define D0F0xBC_xE03000A8_PowerDown_MASK                        0x100
#define D0F0xBC_xE03000A8_PowerUp_OFFSET                        9
#define D0F0xBC_xE03000A8_PowerUp_WIDTH                         1
#define D0F0xBC_xE03000A8_PowerUp_MASK                          0x200
#define D0F0xBC_xE03000A8_P1Select_OFFSET                       10
#define D0F0xBC_xE03000A8_P1Select_WIDTH                        1
#define D0F0xBC_xE03000A8_P1Select_MASK                         0x400
#define D0F0xBC_xE03000A8_P2Select_OFFSET                       11
#define D0F0xBC_xE03000A8_P2Select_WIDTH                        1
#define D0F0xBC_xE03000A8_P2Select_MASK                         0x800
#define D0F0xBC_xE03000A8_WriteOp_OFFSET                        12
#define D0F0xBC_xE03000A8_WriteOp_WIDTH                         1
#define D0F0xBC_xE03000A8_WriteOp_MASK                          0x1000
#define D0F0xBC_xE03000A8_ReadOp_OFFSET                         13
#define D0F0xBC_xE03000A8_ReadOp_WIDTH                          1
#define D0F0xBC_xE03000A8_ReadOp_MASK                           0x2000
#define D0F0xBC_xE03000A8_Reserved_27_14_OFFSET                 14
#define D0F0xBC_xE03000A8_Reserved_27_14_WIDTH                  14
#define D0F0xBC_xE03000A8_Reserved_27_14_MASK                   0xfffc000
#define D0F0xBC_xE03000A8_RegAddr_OFFSET                        28
#define D0F0xBC_xE03000A8_RegAddr_WIDTH                         4
#define D0F0xBC_xE03000A8_RegAddr_MASK                          0xf0000000

/// D0F0xBC_xE03000A8
typedef union {
  struct {                                                              ///<
    UINT32                                                  FsmAddr:8 ; ///<
    UINT32                                                PowerDown:1 ; ///<
    UINT32                                                  PowerUp:1 ; ///<
    UINT32                                                 P1Select:1 ; ///<
    UINT32                                                 P2Select:1 ; ///<
    UINT32                                                  WriteOp:1 ; ///<
    UINT32                                                   ReadOp:1 ; ///<
    UINT32                                           Reserved_27_14:14; ///<
    UINT32                                                  RegAddr:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE03000A8_STRUCT;

// **** D0F0xBC_xE03000AC Register Definition ****
// Address
#define D0F0xBC_xE03000AC_ADDRESS                               0xe03000ac

// Type
#define D0F0xBC_xE03000AC_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE03000AC_WriteValue_OFFSET                     0
#define D0F0xBC_xE03000AC_WriteValue_WIDTH                      32
#define D0F0xBC_xE03000AC_WriteValue_MASK                       0xffffffff

/// D0F0xBC_xE03000AC
typedef union {
  struct {                                                              ///<
    UINT32                                               WriteValue:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE03000AC_STRUCT;

// **** D0F0xBC_xE03000C4 Register Definition ****
// Address
#define D0F0xBC_xE03000C4_ADDRESS                               0xe03000c4

// Type
#define D0F0xBC_xE03000C4_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE03000C4_FsmAddr_OFFSET                        0
#define D0F0xBC_xE03000C4_FsmAddr_WIDTH                         8
#define D0F0xBC_xE03000C4_FsmAddr_MASK                          0xff
#define D0F0xBC_xE03000C4_PowerDown_OFFSET                      8
#define D0F0xBC_xE03000C4_PowerDown_WIDTH                       1
#define D0F0xBC_xE03000C4_PowerDown_MASK                        0x100
#define D0F0xBC_xE03000C4_PowerUp_OFFSET                        9
#define D0F0xBC_xE03000C4_PowerUp_WIDTH                         1
#define D0F0xBC_xE03000C4_PowerUp_MASK                          0x200
#define D0F0xBC_xE03000C4_P1Select_OFFSET                       10
#define D0F0xBC_xE03000C4_P1Select_WIDTH                        1
#define D0F0xBC_xE03000C4_P1Select_MASK                         0x400
#define D0F0xBC_xE03000C4_P2Select_OFFSET                       11
#define D0F0xBC_xE03000C4_P2Select_WIDTH                        1
#define D0F0xBC_xE03000C4_P2Select_MASK                         0x800
#define D0F0xBC_xE03000C4_WriteOp_OFFSET                        12
#define D0F0xBC_xE03000C4_WriteOp_WIDTH                         1
#define D0F0xBC_xE03000C4_WriteOp_MASK                          0x1000
#define D0F0xBC_xE03000C4_ReadOp_OFFSET                         13
#define D0F0xBC_xE03000C4_ReadOp_WIDTH                          1
#define D0F0xBC_xE03000C4_ReadOp_MASK                           0x2000
#define D0F0xBC_xE03000C4_Reserved_27_14_OFFSET                 14
#define D0F0xBC_xE03000C4_Reserved_27_14_WIDTH                  14
#define D0F0xBC_xE03000C4_Reserved_27_14_MASK                   0xfffc000
#define D0F0xBC_xE03000C4_RegAddr_OFFSET                        28
#define D0F0xBC_xE03000C4_RegAddr_WIDTH                         4
#define D0F0xBC_xE03000C4_RegAddr_MASK                          0xf0000000

/// D0F0xBC_xE03000C4
typedef union {
  struct {                                                              ///<
    UINT32                                                  FsmAddr:8 ; ///<
    UINT32                                                PowerDown:1 ; ///<
    UINT32                                                  PowerUp:1 ; ///<
    UINT32                                                 P1Select:1 ; ///<
    UINT32                                                 P2Select:1 ; ///<
    UINT32                                                  WriteOp:1 ; ///<
    UINT32                                                   ReadOp:1 ; ///<
    UINT32                                           Reserved_27_14:14; ///<
    UINT32                                                  RegAddr:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE03000C4_STRUCT;

// **** D0F0xBC_xE03000C8 Register Definition ****
// Address
#define D0F0xBC_xE03000C8_ADDRESS                               0xe03000c8

// Type
#define D0F0xBC_xE03000C8_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE03000C8_WriteValue_OFFSET                     0
#define D0F0xBC_xE03000C8_WriteValue_WIDTH                      32
#define D0F0xBC_xE03000C8_WriteValue_MASK                       0xffffffff

/// D0F0xBC_xE03000C8
typedef union {
  struct {                                                              ///<
    UINT32                                               WriteValue:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE03000C8_STRUCT;

// **** D0F0xBC_xE03000E0 Register Definition ****
// Address
#define D0F0xBC_xE03000E0_ADDRESS                               0xe03000e0

// Type
#define D0F0xBC_xE03000E0_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE03000E0_FsmAddr_OFFSET                        0
#define D0F0xBC_xE03000E0_FsmAddr_WIDTH                         8
#define D0F0xBC_xE03000E0_FsmAddr_MASK                          0xff
#define D0F0xBC_xE03000E0_PowerDown_OFFSET                      8
#define D0F0xBC_xE03000E0_PowerDown_WIDTH                       1
#define D0F0xBC_xE03000E0_PowerDown_MASK                        0x100
#define D0F0xBC_xE03000E0_PowerUp_OFFSET                        9
#define D0F0xBC_xE03000E0_PowerUp_WIDTH                         1
#define D0F0xBC_xE03000E0_PowerUp_MASK                          0x200
#define D0F0xBC_xE03000E0_P1Select_OFFSET                       10
#define D0F0xBC_xE03000E0_P1Select_WIDTH                        1
#define D0F0xBC_xE03000E0_P1Select_MASK                         0x400
#define D0F0xBC_xE03000E0_P2Select_OFFSET                       11
#define D0F0xBC_xE03000E0_P2Select_WIDTH                        1
#define D0F0xBC_xE03000E0_P2Select_MASK                         0x800
#define D0F0xBC_xE03000E0_WriteOp_OFFSET                        12
#define D0F0xBC_xE03000E0_WriteOp_WIDTH                         1
#define D0F0xBC_xE03000E0_WriteOp_MASK                          0x1000
#define D0F0xBC_xE03000E0_ReadOp_OFFSET                         13
#define D0F0xBC_xE03000E0_ReadOp_WIDTH                          1
#define D0F0xBC_xE03000E0_ReadOp_MASK                           0x2000
#define D0F0xBC_xE03000E0_Reserved_27_14_OFFSET                 14
#define D0F0xBC_xE03000E0_Reserved_27_14_WIDTH                  14
#define D0F0xBC_xE03000E0_Reserved_27_14_MASK                   0xfffc000
#define D0F0xBC_xE03000E0_RegAddr_OFFSET                        28
#define D0F0xBC_xE03000E0_RegAddr_WIDTH                         4
#define D0F0xBC_xE03000E0_RegAddr_MASK                          0xf0000000

/// D0F0xBC_xE03000E0
typedef union {
  struct {                                                              ///<
    UINT32                                                  FsmAddr:8 ; ///<
    UINT32                                                PowerDown:1 ; ///<
    UINT32                                                  PowerUp:1 ; ///<
    UINT32                                                 P1Select:1 ; ///<
    UINT32                                                 P2Select:1 ; ///<
    UINT32                                                  WriteOp:1 ; ///<
    UINT32                                                   ReadOp:1 ; ///<
    UINT32                                           Reserved_27_14:14; ///<
    UINT32                                                  RegAddr:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE03000E0_STRUCT;

// **** D0F0xBC_xE03000E4 Register Definition ****
// Address
#define D0F0xBC_xE03000E4_ADDRESS                               0xe03000e4

// Type
#define D0F0xBC_xE03000E4_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE03000E4_WriteValue_OFFSET                     0
#define D0F0xBC_xE03000E4_WriteValue_WIDTH                      32
#define D0F0xBC_xE03000E4_WriteValue_MASK                       0xffffffff

/// D0F0xBC_xE03000E4
typedef union {
  struct {                                                              ///<
    UINT32                                               WriteValue:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE03000E4_STRUCT;

// **** D0F0xBC_xE03000FC Register Definition ****
// Address
#define D0F0xBC_xE03000FC_ADDRESS                               0xe03000fc

// Type
#define D0F0xBC_xE03000FC_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE03000FC_FsmAddr_OFFSET                        0
#define D0F0xBC_xE03000FC_FsmAddr_WIDTH                         8
#define D0F0xBC_xE03000FC_FsmAddr_MASK                          0xff
#define D0F0xBC_xE03000FC_PowerDown_OFFSET                      8
#define D0F0xBC_xE03000FC_PowerDown_WIDTH                       1
#define D0F0xBC_xE03000FC_PowerDown_MASK                        0x100
#define D0F0xBC_xE03000FC_PowerUp_OFFSET                        9
#define D0F0xBC_xE03000FC_PowerUp_WIDTH                         1
#define D0F0xBC_xE03000FC_PowerUp_MASK                          0x200
#define D0F0xBC_xE03000FC_P1Select_OFFSET                       10
#define D0F0xBC_xE03000FC_P1Select_WIDTH                        1
#define D0F0xBC_xE03000FC_P1Select_MASK                         0x400
#define D0F0xBC_xE03000FC_P2Select_OFFSET                       11
#define D0F0xBC_xE03000FC_P2Select_WIDTH                        1
#define D0F0xBC_xE03000FC_P2Select_MASK                         0x800
#define D0F0xBC_xE03000FC_WriteOp_OFFSET                        12
#define D0F0xBC_xE03000FC_WriteOp_WIDTH                         1
#define D0F0xBC_xE03000FC_WriteOp_MASK                          0x1000
#define D0F0xBC_xE03000FC_ReadOp_OFFSET                         13
#define D0F0xBC_xE03000FC_ReadOp_WIDTH                          1
#define D0F0xBC_xE03000FC_ReadOp_MASK                           0x2000
#define D0F0xBC_xE03000FC_Reserved_27_14_OFFSET                 14
#define D0F0xBC_xE03000FC_Reserved_27_14_WIDTH                  14
#define D0F0xBC_xE03000FC_Reserved_27_14_MASK                   0xfffc000
#define D0F0xBC_xE03000FC_RegAddr_OFFSET                        28
#define D0F0xBC_xE03000FC_RegAddr_WIDTH                         4
#define D0F0xBC_xE03000FC_RegAddr_MASK                          0xf0000000

/// D0F0xBC_xE03000FC
typedef union {
  struct {                                                              ///<
    UINT32                                                  FsmAddr:8 ; ///<
    UINT32                                                PowerDown:1 ; ///<
    UINT32                                                  PowerUp:1 ; ///<
    UINT32                                                 P1Select:1 ; ///<
    UINT32                                                 P2Select:1 ; ///<
    UINT32                                                  WriteOp:1 ; ///<
    UINT32                                                   ReadOp:1 ; ///<
    UINT32                                           Reserved_27_14:14; ///<
    UINT32                                                  RegAddr:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE03000FC_STRUCT;

// **** D0F0xBC_xE0300100 Register Definition ****
// Address
#define D0F0xBC_xE0300100_ADDRESS                               0xe0300100

// Type
#define D0F0xBC_xE0300100_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300100_WriteValue_OFFSET                     0
#define D0F0xBC_xE0300100_WriteValue_WIDTH                      32
#define D0F0xBC_xE0300100_WriteValue_MASK                       0xffffffff

/// D0F0xBC_xE0300100
typedef union {
  struct {                                                              ///<
    UINT32                                               WriteValue:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300100_STRUCT;

// **** D0F0xBC_xE0300200 Register Definition ****
// Address
#define D0F0xBC_xE0300200_ADDRESS                               0xe0300200

// Type
#define D0F0xBC_xE0300200_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300200_Reserved_9_0_OFFSET                   0
#define D0F0xBC_xE0300200_Reserved_9_0_WIDTH                    10
#define D0F0xBC_xE0300200_Reserved_9_0_MASK                     0x3ff
#define D0F0xBC_xE0300200_P1IsoN_OFFSET                         10
#define D0F0xBC_xE0300200_P1IsoN_WIDTH                          1
#define D0F0xBC_xE0300200_P1IsoN_MASK                           0x400
#define D0F0xBC_xE0300200_Reserved_31_11_OFFSET                 11
#define D0F0xBC_xE0300200_Reserved_31_11_WIDTH                  21
#define D0F0xBC_xE0300200_Reserved_31_11_MASK                   0xfffff800

/// D0F0xBC_xE0300200
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_9_0:10; ///<
    UINT32                                                   P1IsoN:1 ; ///<
    UINT32                                           Reserved_31_11:21; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300200_STRUCT;


// Type
#define D0F0xBC_xE0300208_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300208_Reserved_9_0_OFFSET                   0
#define D0F0xBC_xE0300208_Reserved_9_0_WIDTH                    10
#define D0F0xBC_xE0300208_Reserved_9_0_MASK                     0x3ff
#define D0F0xBC_xE0300208_P1IsoN_OFFSET                         10
#define D0F0xBC_xE0300208_P1IsoN_WIDTH                          1
#define D0F0xBC_xE0300208_P1IsoN_MASK                           0x400
#define D0F0xBC_xE0300208_Reserved_12_11_OFFSET                 11
#define D0F0xBC_xE0300208_Reserved_12_11_WIDTH                  2
#define D0F0xBC_xE0300208_Reserved_12_11_MASK                   0x1800
#define D0F0xBC_xE0300208_P1PsoDaug_OFFSET                      13
#define D0F0xBC_xE0300208_P1PsoDaug_WIDTH                       1
#define D0F0xBC_xE0300208_P1PsoDaug_MASK                        0x2000
#define D0F0xBC_xE0300208_Reserved_31_14_OFFSET                 14
#define D0F0xBC_xE0300208_Reserved_31_14_WIDTH                  18
#define D0F0xBC_xE0300208_Reserved_31_14_MASK                   0xffffc000

/// D0F0xBC_xE0300208
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_9_0:10; ///<
    UINT32                                                   P1IsoN:1 ; ///<
    UINT32                                           Reserved_12_11:2 ; ///<
    UINT32                                                :1 ; ///<
    UINT32                                           Reserved_31_14:18; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300208_STRUCT;

// **** D0F0xBC_xE030020C Register Definition ****
// Address
#define D0F0xBC_xE030020C_ADDRESS                               0xe030020c

// Type
#define D0F0xBC_xE030020C_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE030020C_Reserved_9_0_OFFSET                   0
#define D0F0xBC_xE030020C_Reserved_9_0_WIDTH                    10
#define D0F0xBC_xE030020C_Reserved_9_0_MASK                     0x3ff
#define D0F0xBC_xE030020C_P1IsoN_OFFSET                         10
#define D0F0xBC_xE030020C_P1IsoN_WIDTH                          1
#define D0F0xBC_xE030020C_P1IsoN_MASK                           0x400
#define D0F0xBC_xE030020C_Reserved_31_11_OFFSET                 11
#define D0F0xBC_xE030020C_Reserved_31_11_WIDTH                  21
#define D0F0xBC_xE030020C_Reserved_31_11_MASK                   0xfffff800

/// D0F0xBC_xE030020C
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_9_0:10; ///<
    UINT32                                                   P1IsoN:1 ; ///<
    UINT32                                           Reserved_31_11:21; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE030020C_STRUCT;

// **** D0F0xBC_xE0300210 Register Definition ****
// Address
#define D0F0xBC_xE0300210_ADDRESS                               0xe0300210

// Type
#define D0F0xBC_xE0300210_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300210_Reserved_9_0_OFFSET                   0
#define D0F0xBC_xE0300210_Reserved_9_0_WIDTH                    10
#define D0F0xBC_xE0300210_Reserved_9_0_MASK                     0x3ff
#define D0F0xBC_xE0300210_P1IsoN_OFFSET                         10
#define D0F0xBC_xE0300210_P1IsoN_WIDTH                          1
#define D0F0xBC_xE0300210_P1IsoN_MASK                           0x400
#define D0F0xBC_xE0300210_Reserved_12_11_OFFSET                 11
#define D0F0xBC_xE0300210_Reserved_12_11_WIDTH                  2
#define D0F0xBC_xE0300210_Reserved_12_11_MASK                   0x1800
#define D0F0xBC_xE0300210_Reserved_31_14_OFFSET                 14
#define D0F0xBC_xE0300210_Reserved_31_14_WIDTH                  18
#define D0F0xBC_xE0300210_Reserved_31_14_MASK                   0xffffc000

/// D0F0xBC_xE0300210
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_9_0:10; ///<
    UINT32                                                   P1IsoN:1 ; ///<
    UINT32                                           Reserved_12_11:2 ; ///<
    UINT32                                                :1 ; ///<
    UINT32                                           Reserved_31_14:18; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300210_STRUCT;

// **** D0F0xBC_xE0300218 Register Definition ****
// Address
#define D0F0xBC_xE0300218_ADDRESS                               0xe0300218

// Type
#define D0F0xBC_xE0300218_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300218_Reserved_9_0_OFFSET                   0
#define D0F0xBC_xE0300218_Reserved_9_0_WIDTH                    10
#define D0F0xBC_xE0300218_Reserved_9_0_MASK                     0x3ff
#define D0F0xBC_xE0300218_P1IsoN_OFFSET                         10
#define D0F0xBC_xE0300218_P1IsoN_WIDTH                          1
#define D0F0xBC_xE0300218_P1IsoN_MASK                           0x400
#define D0F0xBC_xE0300218_Reserved_31_11_OFFSET                 11
#define D0F0xBC_xE0300218_Reserved_31_11_WIDTH                  21
#define D0F0xBC_xE0300218_Reserved_31_11_MASK                   0xfffff800

/// D0F0xBC_xE0300218
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_9_0:10; ///<
    UINT32                                                   P1IsoN:1 ; ///<
    UINT32                                           Reserved_31_11:21; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300218_STRUCT;

// **** D0F0xBC_xE03002DC Register Definition ****
// Address
#define D0F0xBC_xE03002DC_ADDRESS                               0xe03002dc

// Type
#define D0F0xBC_xE03002DC_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_OFFSET              0
#define D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_WIDTH               1
#define D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_MASK                0x1
#define D0F0xBC_xE03002DC_Reserved_OFFSET                       1
#define D0F0xBC_xE03002DC_Reserved_WIDTH                        31
#define D0F0xBC_xE03002DC_Reserved_MASK                         0xfffffffe

/// D0F0xBC_xE03002DC
typedef union {
  struct {                                                              ///<
    UINT32                                        DC2_PGFSM_CONTROL:1 ; ///<
    UINT32                                                 Reserved:31; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE03002DC_STRUCT;

// **** D0F0xBC_xE03002E4 Register Definition ****
// Address
#define D0F0xBC_xE03002E4_ADDRESS                               0xe03002e4

// Type
#define D0F0xBC_xE03002E4_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE03002E4_SmuCb0PsoDaug_OFFSET                  0
#define D0F0xBC_xE03002E4_SmuCb0PsoDaug_WIDTH                   1
#define D0F0xBC_xE03002E4_SmuCb0PsoDaug_MASK                    0x1
#define D0F0xBC_xE03002E4_SmuCb1PsoDaug_OFFSET                  1
#define D0F0xBC_xE03002E4_SmuCb1PsoDaug_WIDTH                   1
#define D0F0xBC_xE03002E4_SmuCb1PsoDaug_MASK                    0x2
#define D0F0xBC_xE03002E4_SmuDb0PsoDaug_OFFSET                  2
#define D0F0xBC_xE03002E4_SmuDb0PsoDaug_WIDTH                   1
#define D0F0xBC_xE03002E4_SmuDb0PsoDaug_MASK                    0x4
#define D0F0xBC_xE03002E4_SmuDb1PsoDaug_OFFSET                  3
#define D0F0xBC_xE03002E4_SmuDb1PsoDaug_WIDTH                   1
#define D0F0xBC_xE03002E4_SmuDb1PsoDaug_MASK                    0x8
#define D0F0xBC_xE03002E4_SmuPaPsoDaug_OFFSET                   4
#define D0F0xBC_xE03002E4_SmuPaPsoDaug_WIDTH                    1
#define D0F0xBC_xE03002E4_SmuPaPsoDaug_MASK                     0x10
#define D0F0xBC_xE03002E4_SmuSpmPsoDaug_OFFSET                  5
#define D0F0xBC_xE03002E4_SmuSpmPsoDaug_WIDTH                   1
#define D0F0xBC_xE03002E4_SmuSpmPsoDaug_MASK                    0x20
#define D0F0xBC_xE03002E4_SmuSpsPsoDaug_OFFSET                  6
#define D0F0xBC_xE03002E4_SmuSpsPsoDaug_WIDTH                   1
#define D0F0xBC_xE03002E4_SmuSpsPsoDaug_MASK                    0x40
#define D0F0xBC_xE03002E4_SmuSqbPsoDaug_OFFSET                  7
#define D0F0xBC_xE03002E4_SmuSqbPsoDaug_WIDTH                   1
#define D0F0xBC_xE03002E4_SmuSqbPsoDaug_MASK                    0x80
#define D0F0xBC_xE03002E4_SmuSxmPsoDaug_OFFSET                  8
#define D0F0xBC_xE03002E4_SmuSxmPsoDaug_WIDTH                   1
#define D0F0xBC_xE03002E4_SmuSxmPsoDaug_MASK                    0x100
#define D0F0xBC_xE03002E4_SmuSxs0PsoDaug_OFFSET                 9
#define D0F0xBC_xE03002E4_SmuSxs0PsoDaug_WIDTH                  1
#define D0F0xBC_xE03002E4_SmuSxs0PsoDaug_MASK                   0x200
#define D0F0xBC_xE03002E4_SmuSxs1PsoDaug_OFFSET                 10
#define D0F0xBC_xE03002E4_SmuSxs1PsoDaug_WIDTH                  1
#define D0F0xBC_xE03002E4_SmuSxs1PsoDaug_MASK                   0x400
#define D0F0xBC_xE03002E4_SmuXbrPsoDaug_OFFSET                  11
#define D0F0xBC_xE03002E4_SmuXbrPsoDaug_WIDTH                   1
#define D0F0xBC_xE03002E4_SmuXbrPsoDaug_MASK                    0x800
#define D0F0xBC_xE03002E4_SmuGdsPsoDaug_OFFSET                  12
#define D0F0xBC_xE03002E4_SmuGdsPsoDaug_WIDTH                   1
#define D0F0xBC_xE03002E4_SmuGdsPsoDaug_MASK                    0x1000
#define D0F0xBC_xE03002E4_SmuVgtPsoDaug_OFFSET                  13
#define D0F0xBC_xE03002E4_SmuVgtPsoDaug_WIDTH                   1
#define D0F0xBC_xE03002E4_SmuVgtPsoDaug_MASK                    0x2000
#define D0F0xBC_xE03002E4_SmuSqaPsoDaug_OFFSET                  14
#define D0F0xBC_xE03002E4_SmuSqaPsoDaug_WIDTH                   1
#define D0F0xBC_xE03002E4_SmuSqaPsoDaug_MASK                    0x4000
#define D0F0xBC_xE03002E4_SmuSqcPsoDaug_OFFSET                  15
#define D0F0xBC_xE03002E4_SmuSqcPsoDaug_WIDTH                   1
#define D0F0xBC_xE03002E4_SmuSqcPsoDaug_MASK                    0x8000
#define D0F0xBC_xE03002E4_SmuTcPsoDaug_OFFSET                   16
#define D0F0xBC_xE03002E4_SmuTcPsoDaug_WIDTH                    1
#define D0F0xBC_xE03002E4_SmuTcPsoDaug_MASK                     0x10000
#define D0F0xBC_xE03002E4_SmuScPsoDaug_OFFSET                   17
#define D0F0xBC_xE03002E4_SmuScPsoDaug_WIDTH                    1
#define D0F0xBC_xE03002E4_SmuScPsoDaug_MASK                     0x20000
#define D0F0xBC_xE03002E4_Reserved_31_18_OFFSET                 18
#define D0F0xBC_xE03002E4_Reserved_31_18_WIDTH                  14
#define D0F0xBC_xE03002E4_Reserved_31_18_MASK                   0xfffc0000

/// D0F0xBC_xE03002E4
typedef union {
  struct {                                                              ///<
    UINT32                                            SmuCb0PsoDaug:1 ; ///<
    UINT32                                            SmuCb1PsoDaug:1 ; ///<
    UINT32                                            SmuDb0PsoDaug:1 ; ///<
    UINT32                                            SmuDb1PsoDaug:1 ; ///<
    UINT32                                             SmuPaPsoDaug:1 ; ///<
    UINT32                                            SmuSpmPsoDaug:1 ; ///<
    UINT32                                            SmuSpsPsoDaug:1 ; ///<
    UINT32                                            SmuSqbPsoDaug:1 ; ///<
    UINT32                                            SmuSxmPsoDaug:1 ; ///<
    UINT32                                           SmuSxs0PsoDaug:1 ; ///<
    UINT32                                           SmuSxs1PsoDaug:1 ; ///<
    UINT32                                            SmuXbrPsoDaug:1 ; ///<
    UINT32                                            SmuGdsPsoDaug:1 ; ///<
    UINT32                                            SmuVgtPsoDaug:1 ; ///<
    UINT32                                            SmuSqaPsoDaug:1 ; ///<
    UINT32                                            SmuSqcPsoDaug:1 ; ///<
    UINT32                                             SmuTcPsoDaug:1 ; ///<
    UINT32                                             SmuScPsoDaug:1 ; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE03002E4_STRUCT;

// **** D0F0xBC_xE03002F0 Register Definition ****
// Address
#define D0F0xBC_xE03002F0_ADDRESS                               0xe03002f0

// Type
#define D0F0xBC_xE03002F0_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE03002F0_SmuTatd0P1IsoN_OFFSET                 0
#define D0F0xBC_xE03002F0_SmuTatd0P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuTatd0P1IsoN_MASK                   0x1
#define D0F0xBC_xE03002F0_SmuSp000P1IsoN_OFFSET                 1
#define D0F0xBC_xE03002F0_SmuSp000P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuSp000P1IsoN_MASK                   0x2
#define D0F0xBC_xE03002F0_SmuSp002P1IsoN_OFFSET                 2
#define D0F0xBC_xE03002F0_SmuSp002P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuSp002P1IsoN_MASK                   0x4
#define D0F0xBC_xE03002F0_SmuLds0P1IsoN_OFFSET                  3
#define D0F0xBC_xE03002F0_SmuLds0P1IsoN_WIDTH                   1
#define D0F0xBC_xE03002F0_SmuLds0P1IsoN_MASK                    0x8
#define D0F0xBC_xE03002F0_SmuTcp0P1IsoN_OFFSET                  4
#define D0F0xBC_xE03002F0_SmuTcp0P1IsoN_WIDTH                   1
#define D0F0xBC_xE03002F0_SmuTcp0P1IsoN_MASK                    0x10
#define D0F0xBC_xE03002F0_SmuTatd1P1IsoN_OFFSET                 5
#define D0F0xBC_xE03002F0_SmuTatd1P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuTatd1P1IsoN_MASK                   0x20
#define D0F0xBC_xE03002F0_SmuSp010P1IsoN_OFFSET                 6
#define D0F0xBC_xE03002F0_SmuSp010P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuSp010P1IsoN_MASK                   0x40
#define D0F0xBC_xE03002F0_SmuSp012P1IsoN_OFFSET                 7
#define D0F0xBC_xE03002F0_SmuSp012P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuSp012P1IsoN_MASK                   0x80
#define D0F0xBC_xE03002F0_SmuLds1P1IsoN_OFFSET                  8
#define D0F0xBC_xE03002F0_SmuLds1P1IsoN_WIDTH                   1
#define D0F0xBC_xE03002F0_SmuLds1P1IsoN_MASK                    0x100
#define D0F0xBC_xE03002F0_SmuTcp1P1IsoN_OFFSET                  9
#define D0F0xBC_xE03002F0_SmuTcp1P1IsoN_WIDTH                   1
#define D0F0xBC_xE03002F0_SmuTcp1P1IsoN_MASK                    0x200
#define D0F0xBC_xE03002F0_SmuTatd2P1IsoN_OFFSET                 10
#define D0F0xBC_xE03002F0_SmuTatd2P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuTatd2P1IsoN_MASK                   0x400
#define D0F0xBC_xE03002F0_SmuSp020P1IsoN_OFFSET                 11
#define D0F0xBC_xE03002F0_SmuSp020P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuSp020P1IsoN_MASK                   0x800
#define D0F0xBC_xE03002F0_SmuSp022P1IsoN_OFFSET                 12
#define D0F0xBC_xE03002F0_SmuSp022P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuSp022P1IsoN_MASK                   0x1000
#define D0F0xBC_xE03002F0_SmuLds2P1IsoN_OFFSET                  13
#define D0F0xBC_xE03002F0_SmuLds2P1IsoN_WIDTH                   1
#define D0F0xBC_xE03002F0_SmuLds2P1IsoN_MASK                    0x2000
#define D0F0xBC_xE03002F0_SmuTcp2P1IsoN_OFFSET                  14
#define D0F0xBC_xE03002F0_SmuTcp2P1IsoN_WIDTH                   1
#define D0F0xBC_xE03002F0_SmuTcp2P1IsoN_MASK                    0x4000
#define D0F0xBC_xE03002F0_SmuTatd3P1IsoN_OFFSET                 15
#define D0F0xBC_xE03002F0_SmuTatd3P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuTatd3P1IsoN_MASK                   0x8000
#define D0F0xBC_xE03002F0_SmuSp030P1IsoN_OFFSET                 16
#define D0F0xBC_xE03002F0_SmuSp030P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuSp030P1IsoN_MASK                   0x10000
#define D0F0xBC_xE03002F0_SmuSp032P1IsoN_OFFSET                 17
#define D0F0xBC_xE03002F0_SmuSp032P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuSp032P1IsoN_MASK                   0x20000
#define D0F0xBC_xE03002F0_SmuLds3P1IsoN_OFFSET                  18
#define D0F0xBC_xE03002F0_SmuLds3P1IsoN_WIDTH                   1
#define D0F0xBC_xE03002F0_SmuLds3P1IsoN_MASK                    0x40000
#define D0F0xBC_xE03002F0_SmuTcp3P1IsoN_OFFSET                  19
#define D0F0xBC_xE03002F0_SmuTcp3P1IsoN_WIDTH                   1
#define D0F0xBC_xE03002F0_SmuTcp3P1IsoN_MASK                    0x80000
#define D0F0xBC_xE03002F0_SmuTatd4P1IsoN_OFFSET                 20
#define D0F0xBC_xE03002F0_SmuTatd4P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuTatd4P1IsoN_MASK                   0x100000
#define D0F0xBC_xE03002F0_SmuSp040P1IsoN_OFFSET                 21
#define D0F0xBC_xE03002F0_SmuSp040P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuSp040P1IsoN_MASK                   0x200000
#define D0F0xBC_xE03002F0_SmuSp042P1IsoN_OFFSET                 22
#define D0F0xBC_xE03002F0_SmuSp042P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuSp042P1IsoN_MASK                   0x400000
#define D0F0xBC_xE03002F0_SmuLds4P1IsoN_OFFSET                  23
#define D0F0xBC_xE03002F0_SmuLds4P1IsoN_WIDTH                   1
#define D0F0xBC_xE03002F0_SmuLds4P1IsoN_MASK                    0x800000
#define D0F0xBC_xE03002F0_SmuTcp4P1IsoN_OFFSET                  24
#define D0F0xBC_xE03002F0_SmuTcp4P1IsoN_WIDTH                   1
#define D0F0xBC_xE03002F0_SmuTcp4P1IsoN_MASK                    0x1000000
#define D0F0xBC_xE03002F0_SmuTatd5P1IsoN_OFFSET                 25
#define D0F0xBC_xE03002F0_SmuTatd5P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuTatd5P1IsoN_MASK                   0x2000000
#define D0F0xBC_xE03002F0_SmuSp050P1IsoN_OFFSET                 26
#define D0F0xBC_xE03002F0_SmuSp050P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuSp050P1IsoN_MASK                   0x4000000
#define D0F0xBC_xE03002F0_SmuSp052P1IsoN_OFFSET                 27
#define D0F0xBC_xE03002F0_SmuSp052P1IsoN_WIDTH                  1
#define D0F0xBC_xE03002F0_SmuSp052P1IsoN_MASK                   0x8000000
#define D0F0xBC_xE03002F0_SmuLds5P1IsoN_OFFSET                  28
#define D0F0xBC_xE03002F0_SmuLds5P1IsoN_WIDTH                   1
#define D0F0xBC_xE03002F0_SmuLds5P1IsoN_MASK                    0x10000000
#define D0F0xBC_xE03002F0_SmuTcp5P1IsoN_OFFSET                  29
#define D0F0xBC_xE03002F0_SmuTcp5P1IsoN_WIDTH                   1
#define D0F0xBC_xE03002F0_SmuTcp5P1IsoN_MASK                    0x20000000
#define D0F0xBC_xE03002F0_Reserved_31_30_OFFSET                 30
#define D0F0xBC_xE03002F0_Reserved_31_30_WIDTH                  2
#define D0F0xBC_xE03002F0_Reserved_31_30_MASK                   0xc0000000

/// D0F0xBC_xE03002F0
typedef union {
  struct {                                                              ///<
    UINT32                                           SmuTatd0P1IsoN:1 ; ///<
    UINT32                                           SmuSp000P1IsoN:1 ; ///<
    UINT32                                           SmuSp002P1IsoN:1 ; ///<
    UINT32                                            SmuLds0P1IsoN:1 ; ///<
    UINT32                                            SmuTcp0P1IsoN:1 ; ///<
    UINT32                                           SmuTatd1P1IsoN:1 ; ///<
    UINT32                                           SmuSp010P1IsoN:1 ; ///<
    UINT32                                           SmuSp012P1IsoN:1 ; ///<
    UINT32                                            SmuLds1P1IsoN:1 ; ///<
    UINT32                                            SmuTcp1P1IsoN:1 ; ///<
    UINT32                                           SmuTatd2P1IsoN:1 ; ///<
    UINT32                                           SmuSp020P1IsoN:1 ; ///<
    UINT32                                           SmuSp022P1IsoN:1 ; ///<
    UINT32                                            SmuLds2P1IsoN:1 ; ///<
    UINT32                                            SmuTcp2P1IsoN:1 ; ///<
    UINT32                                           SmuTatd3P1IsoN:1 ; ///<
    UINT32                                           SmuSp030P1IsoN:1 ; ///<
    UINT32                                           SmuSp032P1IsoN:1 ; ///<
    UINT32                                            SmuLds3P1IsoN:1 ; ///<
    UINT32                                            SmuTcp3P1IsoN:1 ; ///<
    UINT32                                           SmuTatd4P1IsoN:1 ; ///<
    UINT32                                           SmuSp040P1IsoN:1 ; ///<
    UINT32                                           SmuSp042P1IsoN:1 ; ///<
    UINT32                                            SmuLds4P1IsoN:1 ; ///<
    UINT32                                            SmuTcp4P1IsoN:1 ; ///<
    UINT32                                           SmuTatd5P1IsoN:1 ; ///<
    UINT32                                           SmuSp050P1IsoN:1 ; ///<
    UINT32                                           SmuSp052P1IsoN:1 ; ///<
    UINT32                                            SmuLds5P1IsoN:1 ; ///<
    UINT32                                            SmuTcp5P1IsoN:1 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE03002F0_STRUCT;

// **** D0F0xBC_xE03002F4 Register Definition ****
// Address
#define D0F0xBC_xE03002F4_ADDRESS                               0xe03002f4

// Type
#define D0F0xBC_xE03002F4_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE03002F4_SmuCb0IsoN_OFFSET                     0
#define D0F0xBC_xE03002F4_SmuCb0IsoN_WIDTH                      1
#define D0F0xBC_xE03002F4_SmuCb0IsoN_MASK                       0x1
#define D0F0xBC_xE03002F4_SmuCb1IsoN_OFFSET                     1
#define D0F0xBC_xE03002F4_SmuCb1IsoN_WIDTH                      1
#define D0F0xBC_xE03002F4_SmuCb1IsoN_MASK                       0x2
#define D0F0xBC_xE03002F4_SmuDb0IsoN_OFFSET                     2
#define D0F0xBC_xE03002F4_SmuDb0IsoN_WIDTH                      1
#define D0F0xBC_xE03002F4_SmuDb0IsoN_MASK                       0x4
#define D0F0xBC_xE03002F4_SmuDb1IsoN_OFFSET                     3
#define D0F0xBC_xE03002F4_SmuDb1IsoN_WIDTH                      1
#define D0F0xBC_xE03002F4_SmuDb1IsoN_MASK                       0x8
#define D0F0xBC_xE03002F4_SmuPaIsoN_OFFSET                      4
#define D0F0xBC_xE03002F4_SmuPaIsoN_WIDTH                       1
#define D0F0xBC_xE03002F4_SmuPaIsoN_MASK                        0x10
#define D0F0xBC_xE03002F4_SmuSpmIsoN_OFFSET                     5
#define D0F0xBC_xE03002F4_SmuSpmIsoN_WIDTH                      1
#define D0F0xBC_xE03002F4_SmuSpmIsoN_MASK                       0x20
#define D0F0xBC_xE03002F4_SmuSpsIsoN_OFFSET                     6
#define D0F0xBC_xE03002F4_SmuSpsIsoN_WIDTH                      1
#define D0F0xBC_xE03002F4_SmuSpsIsoN_MASK                       0x40
#define D0F0xBC_xE03002F4_SmuSqbIsoN_OFFSET                     7
#define D0F0xBC_xE03002F4_SmuSqbIsoN_WIDTH                      1
#define D0F0xBC_xE03002F4_SmuSqbIsoN_MASK                       0x80
#define D0F0xBC_xE03002F4_SmuSxmIsoN_OFFSET                     8
#define D0F0xBC_xE03002F4_SmuSxmIsoN_WIDTH                      1
#define D0F0xBC_xE03002F4_SmuSxmIsoN_MASK                       0x100
#define D0F0xBC_xE03002F4_SmuSxs0IsoN_OFFSET                    9
#define D0F0xBC_xE03002F4_SmuSxs0IsoN_WIDTH                     1
#define D0F0xBC_xE03002F4_SmuSxs0IsoN_MASK                      0x200
#define D0F0xBC_xE03002F4_SmuSxs1IsoN_OFFSET                    10
#define D0F0xBC_xE03002F4_SmuSxs1IsoN_WIDTH                     1
#define D0F0xBC_xE03002F4_SmuSxs1IsoN_MASK                      0x400
#define D0F0xBC_xE03002F4_SmuXbrIsoN_OFFSET                     11
#define D0F0xBC_xE03002F4_SmuXbrIsoN_WIDTH                      1
#define D0F0xBC_xE03002F4_SmuXbrIsoN_MASK                       0x800
#define D0F0xBC_xE03002F4_SmuGdsIsoN_OFFSET                     12
#define D0F0xBC_xE03002F4_SmuGdsIsoN_WIDTH                      1
#define D0F0xBC_xE03002F4_SmuGdsIsoN_MASK                       0x1000
#define D0F0xBC_xE03002F4_SmuVgtIsoN_OFFSET                     13
#define D0F0xBC_xE03002F4_SmuVgtIsoN_WIDTH                      1
#define D0F0xBC_xE03002F4_SmuVgtIsoN_MASK                       0x2000
#define D0F0xBC_xE03002F4_SmuSqaIsoN_OFFSET                     14
#define D0F0xBC_xE03002F4_SmuSqaIsoN_WIDTH                      1
#define D0F0xBC_xE03002F4_SmuSqaIsoN_MASK                       0x4000
#define D0F0xBC_xE03002F4_SmuSqcIsoN_OFFSET                     15
#define D0F0xBC_xE03002F4_SmuSqcIsoN_WIDTH                      1
#define D0F0xBC_xE03002F4_SmuSqcIsoN_MASK                       0x8000
#define D0F0xBC_xE03002F4_SmuTcIsoN_OFFSET                      16
#define D0F0xBC_xE03002F4_SmuTcIsoN_WIDTH                       1
#define D0F0xBC_xE03002F4_SmuTcIsoN_MASK                        0x10000
#define D0F0xBC_xE03002F4_SmuScIsoN_OFFSET                      17
#define D0F0xBC_xE03002F4_SmuScIsoN_WIDTH                       1
#define D0F0xBC_xE03002F4_SmuScIsoN_MASK                        0x20000
#define D0F0xBC_xE03002F4_Reserved_31_18_OFFSET                 18
#define D0F0xBC_xE03002F4_Reserved_31_18_WIDTH                  14
#define D0F0xBC_xE03002F4_Reserved_31_18_MASK                   0xfffc0000

/// D0F0xBC_xE03002F4
typedef union {
  struct {                                                              ///<
    UINT32                                               SmuCb0IsoN:1 ; ///<
    UINT32                                               SmuCb1IsoN:1 ; ///<
    UINT32                                               SmuDb0IsoN:1 ; ///<
    UINT32                                               SmuDb1IsoN:1 ; ///<
    UINT32                                                SmuPaIsoN:1 ; ///<
    UINT32                                               SmuSpmIsoN:1 ; ///<
    UINT32                                               SmuSpsIsoN:1 ; ///<
    UINT32                                               SmuSqbIsoN:1 ; ///<
    UINT32                                               SmuSxmIsoN:1 ; ///<
    UINT32                                              SmuSxs0IsoN:1 ; ///<
    UINT32                                              SmuSxs1IsoN:1 ; ///<
    UINT32                                               SmuXbrIsoN:1 ; ///<
    UINT32                                               SmuGdsIsoN:1 ; ///<
    UINT32                                               SmuVgtIsoN:1 ; ///<
    UINT32                                               SmuSqaIsoN:1 ; ///<
    UINT32                                               SmuSqcIsoN:1 ; ///<
    UINT32                                                SmuTcIsoN:1 ; ///<
    UINT32                                                SmuScIsoN:1 ; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE03002F4_STRUCT;

// **** D0F0xBC_xE03002F8 Register Definition ****
// Address
#define D0F0xBC_xE03002F8_ADDRESS                               0xe03002f8

// Type
#define D0F0xBC_xE03002F8_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE03002F8_SmuTatd0P2IsoN_OFFSET                 0
#define D0F0xBC_xE03002F8_SmuTatd0P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuTatd0P2IsoN_MASK                   0x1
#define D0F0xBC_xE03002F8_SmuSp000P2IsoN_OFFSET                 1
#define D0F0xBC_xE03002F8_SmuSp000P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuSp000P2IsoN_MASK                   0x2
#define D0F0xBC_xE03002F8_SmuSp002P2IsoN_OFFSET                 2
#define D0F0xBC_xE03002F8_SmuSp002P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuSp002P2IsoN_MASK                   0x4
#define D0F0xBC_xE03002F8_SmuLds0P2IsoN_OFFSET                  3
#define D0F0xBC_xE03002F8_SmuLds0P2IsoN_WIDTH                   1
#define D0F0xBC_xE03002F8_SmuLds0P2IsoN_MASK                    0x8
#define D0F0xBC_xE03002F8_SmuTcp0P2IsoN_OFFSET                  4
#define D0F0xBC_xE03002F8_SmuTcp0P2IsoN_WIDTH                   1
#define D0F0xBC_xE03002F8_SmuTcp0P2IsoN_MASK                    0x10
#define D0F0xBC_xE03002F8_SmuTatd1P2IsoN_OFFSET                 5
#define D0F0xBC_xE03002F8_SmuTatd1P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuTatd1P2IsoN_MASK                   0x20
#define D0F0xBC_xE03002F8_SmuSp010P2IsoN_OFFSET                 6
#define D0F0xBC_xE03002F8_SmuSp010P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuSp010P2IsoN_MASK                   0x40
#define D0F0xBC_xE03002F8_SmuSp012P2IsoN_OFFSET                 7
#define D0F0xBC_xE03002F8_SmuSp012P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuSp012P2IsoN_MASK                   0x80
#define D0F0xBC_xE03002F8_SmuLds1P2IsoN_OFFSET                  8
#define D0F0xBC_xE03002F8_SmuLds1P2IsoN_WIDTH                   1
#define D0F0xBC_xE03002F8_SmuLds1P2IsoN_MASK                    0x100
#define D0F0xBC_xE03002F8_SmuTcp1P2IsoN_OFFSET                  9
#define D0F0xBC_xE03002F8_SmuTcp1P2IsoN_WIDTH                   1
#define D0F0xBC_xE03002F8_SmuTcp1P2IsoN_MASK                    0x200
#define D0F0xBC_xE03002F8_SmuTatd2P2IsoN_OFFSET                 10
#define D0F0xBC_xE03002F8_SmuTatd2P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuTatd2P2IsoN_MASK                   0x400
#define D0F0xBC_xE03002F8_SmuSp020P2IsoN_OFFSET                 11
#define D0F0xBC_xE03002F8_SmuSp020P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuSp020P2IsoN_MASK                   0x800
#define D0F0xBC_xE03002F8_SmuSp022P2IsoN_OFFSET                 12
#define D0F0xBC_xE03002F8_SmuSp022P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuSp022P2IsoN_MASK                   0x1000
#define D0F0xBC_xE03002F8_SmuLds2P2IsoN_OFFSET                  13
#define D0F0xBC_xE03002F8_SmuLds2P2IsoN_WIDTH                   1
#define D0F0xBC_xE03002F8_SmuLds2P2IsoN_MASK                    0x2000
#define D0F0xBC_xE03002F8_SmuTcp2P2IsoN_OFFSET                  14
#define D0F0xBC_xE03002F8_SmuTcp2P2IsoN_WIDTH                   1
#define D0F0xBC_xE03002F8_SmuTcp2P2IsoN_MASK                    0x4000
#define D0F0xBC_xE03002F8_SmuTatd3P2IsoN_OFFSET                 15
#define D0F0xBC_xE03002F8_SmuTatd3P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuTatd3P2IsoN_MASK                   0x8000
#define D0F0xBC_xE03002F8_SmuSp030P2IsoN_OFFSET                 16
#define D0F0xBC_xE03002F8_SmuSp030P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuSp030P2IsoN_MASK                   0x10000
#define D0F0xBC_xE03002F8_SmuSp032P2IsoN_OFFSET                 17
#define D0F0xBC_xE03002F8_SmuSp032P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuSp032P2IsoN_MASK                   0x20000
#define D0F0xBC_xE03002F8_SmuLds3P2IsoN_OFFSET                  18
#define D0F0xBC_xE03002F8_SmuLds3P2IsoN_WIDTH                   1
#define D0F0xBC_xE03002F8_SmuLds3P2IsoN_MASK                    0x40000
#define D0F0xBC_xE03002F8_SmuTcp3P2IsoN_OFFSET                  19
#define D0F0xBC_xE03002F8_SmuTcp3P2IsoN_WIDTH                   1
#define D0F0xBC_xE03002F8_SmuTcp3P2IsoN_MASK                    0x80000
#define D0F0xBC_xE03002F8_SmuTatd4P2IsoN_OFFSET                 20
#define D0F0xBC_xE03002F8_SmuTatd4P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuTatd4P2IsoN_MASK                   0x100000
#define D0F0xBC_xE03002F8_SmuSp040P2IsoN_OFFSET                 21
#define D0F0xBC_xE03002F8_SmuSp040P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuSp040P2IsoN_MASK                   0x200000
#define D0F0xBC_xE03002F8_SmuSp042P2IsoN_OFFSET                 22
#define D0F0xBC_xE03002F8_SmuSp042P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuSp042P2IsoN_MASK                   0x400000
#define D0F0xBC_xE03002F8_SmuLds4P2IsoN_OFFSET                  23
#define D0F0xBC_xE03002F8_SmuLds4P2IsoN_WIDTH                   1
#define D0F0xBC_xE03002F8_SmuLds4P2IsoN_MASK                    0x800000
#define D0F0xBC_xE03002F8_SmuTcp4P2IsoN_OFFSET                  24
#define D0F0xBC_xE03002F8_SmuTcp4P2IsoN_WIDTH                   1
#define D0F0xBC_xE03002F8_SmuTcp4P2IsoN_MASK                    0x1000000
#define D0F0xBC_xE03002F8_SmuTatd5P2IsoN_OFFSET                 25
#define D0F0xBC_xE03002F8_SmuTatd5P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuTatd5P2IsoN_MASK                   0x2000000
#define D0F0xBC_xE03002F8_SmuSp050P2IsoN_OFFSET                 26
#define D0F0xBC_xE03002F8_SmuSp050P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuSp050P2IsoN_MASK                   0x4000000
#define D0F0xBC_xE03002F8_SmuSp052P2IsoN_OFFSET                 27
#define D0F0xBC_xE03002F8_SmuSp052P2IsoN_WIDTH                  1
#define D0F0xBC_xE03002F8_SmuSp052P2IsoN_MASK                   0x8000000
#define D0F0xBC_xE03002F8_SmuLds5P2IsoN_OFFSET                  28
#define D0F0xBC_xE03002F8_SmuLds5P2IsoN_WIDTH                   1
#define D0F0xBC_xE03002F8_SmuLds5P2IsoN_MASK                    0x10000000
#define D0F0xBC_xE03002F8_SmuTcp5P2IsoN_OFFSET                  29
#define D0F0xBC_xE03002F8_SmuTcp5P2IsoN_WIDTH                   1
#define D0F0xBC_xE03002F8_SmuTcp5P2IsoN_MASK                    0x20000000
#define D0F0xBC_xE03002F8_Reserved_31_30_OFFSET                 30
#define D0F0xBC_xE03002F8_Reserved_31_30_WIDTH                  2
#define D0F0xBC_xE03002F8_Reserved_31_30_MASK                   0xc0000000

/// D0F0xBC_xE03002F8
typedef union {
  struct {                                                              ///<
    UINT32                                           SmuTatd0P2IsoN:1 ; ///<
    UINT32                                           SmuSp000P2IsoN:1 ; ///<
    UINT32                                           SmuSp002P2IsoN:1 ; ///<
    UINT32                                            SmuLds0P2IsoN:1 ; ///<
    UINT32                                            SmuTcp0P2IsoN:1 ; ///<
    UINT32                                           SmuTatd1P2IsoN:1 ; ///<
    UINT32                                           SmuSp010P2IsoN:1 ; ///<
    UINT32                                           SmuSp012P2IsoN:1 ; ///<
    UINT32                                            SmuLds1P2IsoN:1 ; ///<
    UINT32                                            SmuTcp1P2IsoN:1 ; ///<
    UINT32                                           SmuTatd2P2IsoN:1 ; ///<
    UINT32                                           SmuSp020P2IsoN:1 ; ///<
    UINT32                                           SmuSp022P2IsoN:1 ; ///<
    UINT32                                            SmuLds2P2IsoN:1 ; ///<
    UINT32                                            SmuTcp2P2IsoN:1 ; ///<
    UINT32                                           SmuTatd3P2IsoN:1 ; ///<
    UINT32                                           SmuSp030P2IsoN:1 ; ///<
    UINT32                                           SmuSp032P2IsoN:1 ; ///<
    UINT32                                            SmuLds3P2IsoN:1 ; ///<
    UINT32                                            SmuTcp3P2IsoN:1 ; ///<
    UINT32                                           SmuTatd4P2IsoN:1 ; ///<
    UINT32                                           SmuSp040P2IsoN:1 ; ///<
    UINT32                                           SmuSp042P2IsoN:1 ; ///<
    UINT32                                            SmuLds4P2IsoN:1 ; ///<
    UINT32                                            SmuTcp4P2IsoN:1 ; ///<
    UINT32                                           SmuTatd5P2IsoN:1 ; ///<
    UINT32                                           SmuSp050P2IsoN:1 ; ///<
    UINT32                                           SmuSp052P2IsoN:1 ; ///<
    UINT32                                            SmuLds5P2IsoN:1 ; ///<
    UINT32                                            SmuTcp5P2IsoN:1 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE03002F8_STRUCT;

// **** D0F0xBC_xE03002FC Register Definition ****
// Address
#define D0F0xBC_xE03002FC_ADDRESS                               0xe03002fc

// Type
#define D0F0xBC_xE03002FC_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE03002FC_SmuTatd0P2PsoDaug_OFFSET              0
#define D0F0xBC_xE03002FC_SmuTatd0P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuTatd0P2PsoDaug_MASK                0x1
#define D0F0xBC_xE03002FC_SmuSp000P2PsoDaug_OFFSET              1
#define D0F0xBC_xE03002FC_SmuSp000P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuSp000P2PsoDaug_MASK                0x2
#define D0F0xBC_xE03002FC_SmuSp002P2PsoDaug_OFFSET              2
#define D0F0xBC_xE03002FC_SmuSp002P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuSp002P2PsoDaug_MASK                0x4
#define D0F0xBC_xE03002FC_SmuLds0P2PsoDaug_OFFSET               3
#define D0F0xBC_xE03002FC_SmuLds0P2PsoDaug_WIDTH                1
#define D0F0xBC_xE03002FC_SmuLds0P2PsoDaug_MASK                 0x8
#define D0F0xBC_xE03002FC_SmuTcp0P2PsoDaug_OFFSET               4
#define D0F0xBC_xE03002FC_SmuTcp0P2PsoDaug_WIDTH                1
#define D0F0xBC_xE03002FC_SmuTcp0P2PsoDaug_MASK                 0x10
#define D0F0xBC_xE03002FC_SmuTatd1P2PsoDaug_OFFSET              5
#define D0F0xBC_xE03002FC_SmuTatd1P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuTatd1P2PsoDaug_MASK                0x20
#define D0F0xBC_xE03002FC_SmuSp010P2PsoDaug_OFFSET              6
#define D0F0xBC_xE03002FC_SmuSp010P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuSp010P2PsoDaug_MASK                0x40
#define D0F0xBC_xE03002FC_SmuSp012P2PsoDaug_OFFSET              7
#define D0F0xBC_xE03002FC_SmuSp012P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuSp012P2PsoDaug_MASK                0x80
#define D0F0xBC_xE03002FC_SmuLds1P2PsoDaug_OFFSET               8
#define D0F0xBC_xE03002FC_SmuLds1P2PsoDaug_WIDTH                1
#define D0F0xBC_xE03002FC_SmuLds1P2PsoDaug_MASK                 0x100
#define D0F0xBC_xE03002FC_SmuTcp1P2PsoDaug_OFFSET               9
#define D0F0xBC_xE03002FC_SmuTcp1P2PsoDaug_WIDTH                1
#define D0F0xBC_xE03002FC_SmuTcp1P2PsoDaug_MASK                 0x200
#define D0F0xBC_xE03002FC_SmuTatd2P2PsoDaug_OFFSET              10
#define D0F0xBC_xE03002FC_SmuTatd2P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuTatd2P2PsoDaug_MASK                0x400
#define D0F0xBC_xE03002FC_SmuSp020P2PsoDaug_OFFSET              11
#define D0F0xBC_xE03002FC_SmuSp020P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuSp020P2PsoDaug_MASK                0x800
#define D0F0xBC_xE03002FC_SmuSp022P2PsoDaug_OFFSET              12
#define D0F0xBC_xE03002FC_SmuSp022P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuSp022P2PsoDaug_MASK                0x1000
#define D0F0xBC_xE03002FC_SmuLds2P2PsoDaug_OFFSET               13
#define D0F0xBC_xE03002FC_SmuLds2P2PsoDaug_WIDTH                1
#define D0F0xBC_xE03002FC_SmuLds2P2PsoDaug_MASK                 0x2000
#define D0F0xBC_xE03002FC_SmuTcp2P2PsoDaug_OFFSET               14
#define D0F0xBC_xE03002FC_SmuTcp2P2PsoDaug_WIDTH                1
#define D0F0xBC_xE03002FC_SmuTcp2P2PsoDaug_MASK                 0x4000
#define D0F0xBC_xE03002FC_SmuTatd3P2PsoDaug_OFFSET              15
#define D0F0xBC_xE03002FC_SmuTatd3P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuTatd3P2PsoDaug_MASK                0x8000
#define D0F0xBC_xE03002FC_SmuSp030P2PsoDaug_OFFSET              16
#define D0F0xBC_xE03002FC_SmuSp030P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuSp030P2PsoDaug_MASK                0x10000
#define D0F0xBC_xE03002FC_SmuSp032P2PsoDaug_OFFSET              17
#define D0F0xBC_xE03002FC_SmuSp032P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuSp032P2PsoDaug_MASK                0x20000
#define D0F0xBC_xE03002FC_SmuLds3P2PsoDaug_OFFSET               18
#define D0F0xBC_xE03002FC_SmuLds3P2PsoDaug_WIDTH                1
#define D0F0xBC_xE03002FC_SmuLds3P2PsoDaug_MASK                 0x40000
#define D0F0xBC_xE03002FC_SmuTcp3P2PsoDaug_OFFSET               19
#define D0F0xBC_xE03002FC_SmuTcp3P2PsoDaug_WIDTH                1
#define D0F0xBC_xE03002FC_SmuTcp3P2PsoDaug_MASK                 0x80000
#define D0F0xBC_xE03002FC_SmuTatd4P2PsoDaug_OFFSET              20
#define D0F0xBC_xE03002FC_SmuTatd4P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuTatd4P2PsoDaug_MASK                0x100000
#define D0F0xBC_xE03002FC_SmuSp040P2PsoDaug_OFFSET              21
#define D0F0xBC_xE03002FC_SmuSp040P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuSp040P2PsoDaug_MASK                0x200000
#define D0F0xBC_xE03002FC_SmuSp042P2PsoDaug_OFFSET              22
#define D0F0xBC_xE03002FC_SmuSp042P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuSp042P2PsoDaug_MASK                0x400000
#define D0F0xBC_xE03002FC_SmuLds4P2PsoDaug_OFFSET               23
#define D0F0xBC_xE03002FC_SmuLds4P2PsoDaug_WIDTH                1
#define D0F0xBC_xE03002FC_SmuLds4P2PsoDaug_MASK                 0x800000
#define D0F0xBC_xE03002FC_SmuTcp4P2PsoDaug_OFFSET               24
#define D0F0xBC_xE03002FC_SmuTcp4P2PsoDaug_WIDTH                1
#define D0F0xBC_xE03002FC_SmuTcp4P2PsoDaug_MASK                 0x1000000
#define D0F0xBC_xE03002FC_SmuTatd5P2PsoDaug_OFFSET              25
#define D0F0xBC_xE03002FC_SmuTatd5P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuTatd5P2PsoDaug_MASK                0x2000000
#define D0F0xBC_xE03002FC_SmuSp050P2PsoDaug_OFFSET              26
#define D0F0xBC_xE03002FC_SmuSp050P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuSp050P2PsoDaug_MASK                0x4000000
#define D0F0xBC_xE03002FC_SmuSp052P2PsoDaug_OFFSET              27
#define D0F0xBC_xE03002FC_SmuSp052P2PsoDaug_WIDTH               1
#define D0F0xBC_xE03002FC_SmuSp052P2PsoDaug_MASK                0x8000000
#define D0F0xBC_xE03002FC_SmuLds5P2PsoDaug_OFFSET               28
#define D0F0xBC_xE03002FC_SmuLds5P2PsoDaug_WIDTH                1
#define D0F0xBC_xE03002FC_SmuLds5P2PsoDaug_MASK                 0x10000000
#define D0F0xBC_xE03002FC_SmuTcp5P2PsoDaug_OFFSET               29
#define D0F0xBC_xE03002FC_SmuTcp5P2PsoDaug_WIDTH                1
#define D0F0xBC_xE03002FC_SmuTcp5P2PsoDaug_MASK                 0x20000000
#define D0F0xBC_xE03002FC_Reserved_31_30_OFFSET                 30
#define D0F0xBC_xE03002FC_Reserved_31_30_WIDTH                  2
#define D0F0xBC_xE03002FC_Reserved_31_30_MASK                   0xc0000000

/// D0F0xBC_xE03002FC
typedef union {
  struct {                                                              ///<
    UINT32                                        SmuTatd0P2PsoDaug:1 ; ///<
    UINT32                                        SmuSp000P2PsoDaug:1 ; ///<
    UINT32                                        SmuSp002P2PsoDaug:1 ; ///<
    UINT32                                         SmuLds0P2PsoDaug:1 ; ///<
    UINT32                                         SmuTcp0P2PsoDaug:1 ; ///<
    UINT32                                        SmuTatd1P2PsoDaug:1 ; ///<
    UINT32                                        SmuSp010P2PsoDaug:1 ; ///<
    UINT32                                        SmuSp012P2PsoDaug:1 ; ///<
    UINT32                                         SmuLds1P2PsoDaug:1 ; ///<
    UINT32                                         SmuTcp1P2PsoDaug:1 ; ///<
    UINT32                                        SmuTatd2P2PsoDaug:1 ; ///<
    UINT32                                        SmuSp020P2PsoDaug:1 ; ///<
    UINT32                                        SmuSp022P2PsoDaug:1 ; ///<
    UINT32                                         SmuLds2P2PsoDaug:1 ; ///<
    UINT32                                         SmuTcp2P2PsoDaug:1 ; ///<
    UINT32                                        SmuTatd3P2PsoDaug:1 ; ///<
    UINT32                                        SmuSp030P2PsoDaug:1 ; ///<
    UINT32                                        SmuSp032P2PsoDaug:1 ; ///<
    UINT32                                         SmuLds3P2PsoDaug:1 ; ///<
    UINT32                                         SmuTcp3P2PsoDaug:1 ; ///<
    UINT32                                        SmuTatd4P2PsoDaug:1 ; ///<
    UINT32                                        SmuSp040P2PsoDaug:1 ; ///<
    UINT32                                        SmuSp042P2PsoDaug:1 ; ///<
    UINT32                                         SmuLds4P2PsoDaug:1 ; ///<
    UINT32                                         SmuTcp4P2PsoDaug:1 ; ///<
    UINT32                                        SmuTatd5P2PsoDaug:1 ; ///<
    UINT32                                        SmuSp050P2PsoDaug:1 ; ///<
    UINT32                                        SmuSp052P2PsoDaug:1 ; ///<
    UINT32                                         SmuLds5P2PsoDaug:1 ; ///<
    UINT32                                         SmuTcp5P2PsoDaug:1 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE03002FC_STRUCT;

// **** D0F0xBC_xE0300320 Register Definition ****
// Address
#define D0F0xBC_xE0300320_ADDRESS                               0xe0300320

// Type
#define D0F0xBC_xE0300320_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300320_PgdPgfsmClockEn_OFFSET                0
#define D0F0xBC_xE0300320_PgdPgfsmClockEn_WIDTH                 1
#define D0F0xBC_xE0300320_PgdPgfsmClockEn_MASK                  0x1
#define D0F0xBC_xE0300320_IommuPgfsmClockEn_OFFSET              1
#define D0F0xBC_xE0300320_IommuPgfsmClockEn_WIDTH               1
#define D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK                0x2
#define D0F0xBC_xE0300320_Reserved_31_2_OFFSET                  2
#define D0F0xBC_xE0300320_Reserved_31_2_WIDTH                   30
#define D0F0xBC_xE0300320_Reserved_31_2_MASK                    0xfffffffc

/// D0F0xBC_xE0300320
typedef union {
  struct {                                                              ///<
    UINT32                                          PgdPgfsmClockEn:1 ; ///<
    UINT32                                        IommuPgfsmClockEn:1 ; ///<
    UINT32                                            Reserved_31_2:30; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300320_STRUCT;

// **** D0F0xBC_xE0300324 Register Definition ****
// Address
#define D0F0xBC_xE0300324_ADDRESS                               0xe0300324

// Type
#define D0F0xBC_xE0300324_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE0300324_VcePgfsmClockEn_OFFSET                0
#define D0F0xBC_xE0300324_VcePgfsmClockEn_WIDTH                 1
#define D0F0xBC_xE0300324_VcePgfsmClockEn_MASK                  0x1
#define D0F0xBC_xE0300324_UvdPgfsmClockEn_OFFSET                1
#define D0F0xBC_xE0300324_UvdPgfsmClockEn_WIDTH                 1
#define D0F0xBC_xE0300324_UvdPgfsmClockEn_MASK                  0x2
#define D0F0xBC_xE0300324_Dc2PgfsmClockEn_OFFSET                2
#define D0F0xBC_xE0300324_Dc2PgfsmClockEn_WIDTH                 1
#define D0F0xBC_xE0300324_Dc2PgfsmClockEn_MASK                  0x4
#define D0F0xBC_xE0300324_Reserved_31_3_OFFSET                  3
#define D0F0xBC_xE0300324_Reserved_31_3_WIDTH                   29
#define D0F0xBC_xE0300324_Reserved_31_3_MASK                    0xfffffff8

/// D0F0xBC_xE0300324
typedef union {
  struct {                                                              ///<
    UINT32                                          VcePgfsmClockEn:1 ; ///<
    UINT32                                          UvdPgfsmClockEn:1 ; ///<
    UINT32                                          Dc2PgfsmClockEn:1 ; ///<
    UINT32                                            Reserved_31_3:29; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0300324_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32                                        Simd0PgfsmClockEn:1 ; ///<
    UINT32                                        Simd1PgfsmClockEn:1 ; ///<
    UINT32                                        Simd2PgfsmClockEn:1 ; ///<
    UINT32                                        Simd3PgfsmClockEn:1 ; ///<
    UINT32                                        Simd4PgfsmClockEn:1 ; ///<
    UINT32        ex1009_0:1;
    UINT32        ex1009_1:1;
    UINT32                                            Reserved_31_7:25; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1009_STRUCT;

// **** D0F0xBC_xFF000000 Register Definition ****
// Address
#define D0F0xBC_xFF000000_ADDRESS                               0xff000000

// Type
#define D0F0xBC_xFF000000_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xFF000000_GckFuseProg_OFFSET                    0
#define D0F0xBC_xFF000000_GckFuseProg_WIDTH                     1
#define D0F0xBC_xFF000000_GckFuseProg_MASK                      0x1
#define D0F0xBC_xFF000000_MainPllOpFreqIdStartup_OFFSET         1
#define D0F0xBC_xFF000000_MainPllOpFreqIdStartup_WIDTH          6
#define D0F0xBC_xFF000000_MainPllOpFreqIdStartup_MASK           0x7e
#define D0F0xBC_xFF000000_MainPllOpFreqIdMax_OFFSET             7
#define D0F0xBC_xFF000000_MainPllOpFreqIdMax_WIDTH              6
#define D0F0xBC_xFF000000_MainPllOpFreqIdMax_MASK               0x1f80
#define D0F0xBC_xFF000000_MainPllRefAdj_OFFSET                  13
#define D0F0xBC_xFF000000_MainPllRefAdj_WIDTH                   5
#define D0F0xBC_xFF000000_MainPllRefAdj_MASK                    0x3e000
#define D0F0xBC_xFF000000_PllMiscFuseCtl_OFFSET                 18
#define D0F0xBC_xFF000000_PllMiscFuseCtl_WIDTH                  4
#define D0F0xBC_xFF000000_PllMiscFuseCtl_MASK                   0x3c0000
#define D0F0xBC_xFF000000_Reserved_31_22_OFFSET                 22
#define D0F0xBC_xFF000000_Reserved_31_22_WIDTH                  10
#define D0F0xBC_xFF000000_Reserved_31_22_MASK                   0xffc00000

/// D0F0xBC_xFF000000
typedef union {
  struct {                                                              ///<
    UINT32                                              GckFuseProg:1 ; ///<
    UINT32                                   MainPllOpFreqIdStartup:6 ; ///<
    UINT32                                       MainPllOpFreqIdMax:6 ; ///<
    UINT32                                            MainPllRefAdj:5 ; ///<
    UINT32                                           PllMiscFuseCtl:4 ; ///<
    UINT32                                           Reserved_31_22:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xFF000000_STRUCT;

// **** D0F0xE4_WRAP_0046 Register Definition ****
// Address
#define D0F0xE4_WRAP_0046_ADDRESS                               0x46

// Type
#define D0F0xE4_WRAP_0046_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_0046_SubsystemVendorID_OFFSET              0
#define D0F0xE4_WRAP_0046_SubsystemVendorID_WIDTH               16
#define D0F0xE4_WRAP_0046_SubsystemVendorID_MASK                0xffff
#define D0F0xE4_WRAP_0046_SubsystemID_OFFSET                    16
#define D0F0xE4_WRAP_0046_SubsystemID_WIDTH                     16
#define D0F0xE4_WRAP_0046_SubsystemID_MASK                      0xffff0000

/// D0F0xE4_WRAP_0046
typedef union {
  struct {                                                              ///<
    UINT32                                        SubsystemVendorID:16; ///<
    UINT32                                              SubsystemID:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_0046_STRUCT;

// **** D0F0xE4_WRAP_0080 Register Definition ****
// Address
#define D0F0xE4_WRAP_0080_ADDRESS                               0x80

// Type
#define D0F0xE4_WRAP_0080_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET             0
#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH              4
#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_MASK               0xf
#define D0F0xE4_WRAP_0080_Reserved_31_4_OFFSET                  4
#define D0F0xE4_WRAP_0080_Reserved_31_4_WIDTH                   28
#define D0F0xE4_WRAP_0080_Reserved_31_4_MASK                    0xfffffff0

/// D0F0xE4_WRAP_0080
typedef union {
  struct {                                                              ///<
    UINT32                                       StrapBifLinkConfig:4 ; ///<
    UINT32                                            Reserved_31_4:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_0080_STRUCT;

// **** D0F0xE4_WRAP_0800 Register Definition ****
// Address
#define D0F0xE4_WRAP_0800_ADDRESS                               0x800

// Type
#define D0F0xE4_WRAP_0800_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_0800_HoldTraining_OFFSET                   0
#define D0F0xE4_WRAP_0800_HoldTraining_WIDTH                    1
#define D0F0xE4_WRAP_0800_HoldTraining_MASK                     0x1
#define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET                  1
#define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH                   31
#define D0F0xE4_WRAP_0800_Reserved_31_1_MASK                    0xfffffffe

/// D0F0xE4_WRAP_0800
typedef union {
  struct {                                                              ///<
    UINT32                                             HoldTraining:1 ; ///<
    UINT32                                            Reserved_31_1:31; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_0800_STRUCT;

// **** D0F0xE4_WRAP_0803 Register Definition ****
// Address
#define D0F0xE4_WRAP_0803_ADDRESS                               0x803

// Type
#define D0F0xE4_WRAP_0803_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_0803_Reserved_4_0_OFFSET                   0
#define D0F0xE4_WRAP_0803_Reserved_4_0_WIDTH                    5
#define D0F0xE4_WRAP_0803_Reserved_4_0_MASK                     0x1f
#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET          5
#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH           1
#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_MASK            0x20
#define D0F0xE4_WRAP_0803_Reserved_31_6_OFFSET                  6
#define D0F0xE4_WRAP_0803_Reserved_31_6_WIDTH                   26
#define D0F0xE4_WRAP_0803_Reserved_31_6_MASK                    0xffffffc0

/// D0F0xE4_WRAP_0803
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_4_0:5 ; ///<
    UINT32                                    StrapBifDeemphasisSel:1 ; ///<
    UINT32                                            Reserved_31_6:26; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_0803_STRUCT;

// **** D0F0xE4_WRAP_0903 Register Definition ****
// Address
#define D0F0xE4_WRAP_0903_ADDRESS                               0x903

// Type
#define D0F0xE4_WRAP_0903_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_0903_Reserved_4_0_OFFSET                   0
#define D0F0xE4_WRAP_0903_Reserved_4_0_WIDTH                    5
#define D0F0xE4_WRAP_0903_Reserved_4_0_MASK                     0x1f
#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET          5
#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_WIDTH           1
#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK            0x20
#define D0F0xE4_WRAP_0903_Reserved_31_6_OFFSET                  6
#define D0F0xE4_WRAP_0903_Reserved_31_6_WIDTH                   26
#define D0F0xE4_WRAP_0903_Reserved_31_6_MASK                    0xffffffc0

/// D0F0xE4_WRAP_0903
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_4_0:5 ; ///<
    UINT32                                    StrapBifDeemphasisSel:1 ; ///<
    UINT32                                            Reserved_31_6:26; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_0903_STRUCT;


// **** D0F0xE4_WRAP_8011 Register Definition ****
// Address
#define D0F0xE4_WRAP_8011_ADDRESS                               0x8011

// Type
#define D0F0xE4_WRAP_8011_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET            0
#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH             6
#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK              0x3f
#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET              6
#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH               1
#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK                0x40
#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET             7
#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH              1
#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK               0x80
#define D0F0xE4_WRAP_8011_TxclkPermStop_OFFSET                  8
#define D0F0xE4_WRAP_8011_TxclkPermStop_WIDTH                   1
#define D0F0xE4_WRAP_8011_TxclkPermStop_MASK                    0x100
#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET            9
#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH             1
#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK              0x200
#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET           10
#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH            6
#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK             0xfc00
#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET               16
#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH                1
#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_MASK                 0x10000
#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET           17
#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH            6
#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK             0x7e0000
#define D0F0xE4_WRAP_8011_DebugBusClkEnable_OFFSET              23
#define D0F0xE4_WRAP_8011_DebugBusClkEnable_WIDTH               1
#define D0F0xE4_WRAP_8011_DebugBusClkEnable_MASK                0x800000
#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET            24
#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH             1
#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK              0x1000000
#define D0F0xE4_WRAP_8011_DdiDualLinkOverride_OFFSET            25
#define D0F0xE4_WRAP_8011_DdiDualLinkOverride_WIDTH             1
#define D0F0xE4_WRAP_8011_DdiDualLinkOverride_MASK              0x2000000
#define D0F0xE4_WRAP_8011_Reserved_30_26_OFFSET                 26
#define D0F0xE4_WRAP_8011_Reserved_30_26_WIDTH                  5
#define D0F0xE4_WRAP_8011_Reserved_30_26_MASK                   0x7c000000
#define D0F0xE4_WRAP_8011_StrapBifValid_OFFSET                  31
#define D0F0xE4_WRAP_8011_StrapBifValid_WIDTH                   1
#define D0F0xE4_WRAP_8011_StrapBifValid_MASK                    0x80000000

/// D0F0xE4_WRAP_8011
typedef union {
  struct {                                                              ///<
    UINT32                                      TxclkDynGateLatency:6 ; ///<
    UINT32                                        TxclkPermGateEven:1 ; ///<
    UINT32                                       TxclkDynGateEnable:1 ; ///<
    UINT32                                            TxclkPermStop:1 ; ///<
    UINT32                                      TxclkRegsGateEnable:1 ; ///<
    UINT32                                     TxclkRegsGateLatency:6 ; ///<
    UINT32                                         RcvrDetClkEnable:1 ; ///<
    UINT32                                     TxclkPermGateLatency:6 ; ///<
    UINT32                                        DebugBusClkEnable:1 ; ///<
    UINT32                                      TxclkLcntGateEnable:1 ; ///<
    UINT32                                      DdiDualLinkOverride:1 ; ///<
    UINT32                                           Reserved_30_26:5 ; ///<
    UINT32                                            StrapBifValid:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_8011_STRUCT;

// **** D0F0xE4_WRAP_8016 Register Definition ****
// Address
#define D0F0xE4_WRAP_8016_ADDRESS                               0x8016

// Type
#define D0F0xE4_WRAP_8016_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET                0
#define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH                 6
#define D0F0xE4_WRAP_8016_CalibAckLatency_MASK                  0x3f
#define D0F0xE4_WRAP_8016_Reserved_15_6_OFFSET                  6
#define D0F0xE4_WRAP_8016_Reserved_15_6_WIDTH                   10
#define D0F0xE4_WRAP_8016_Reserved_15_6_MASK                    0xffc0
#define D0F0xE4_WRAP_8016_LclkDynGateLatency_OFFSET             16
#define D0F0xE4_WRAP_8016_LclkDynGateLatency_WIDTH              6
#define D0F0xE4_WRAP_8016_LclkDynGateLatency_MASK               0x3f0000
#define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET                   22
#define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH                    1
#define D0F0xE4_WRAP_8016_LclkGateFree_MASK                     0x400000
#define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET              23
#define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH               1
#define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK                0x800000
#define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET                 24
#define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH                  8
#define D0F0xE4_WRAP_8016_Reserved_31_24_MASK                   0xff000000

/// D0F0xE4_WRAP_8016
typedef union {
  struct {                                                              ///<
    UINT32                                          CalibAckLatency:6 ; ///<
    UINT32                                            Reserved_15_6:10; ///<
    UINT32                                       LclkDynGateLatency:6 ; ///<
    UINT32                                             LclkGateFree:1 ; ///<
    UINT32                                        LclkDynGateEnable:1 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_8016_STRUCT;

// **** D0F0xE4_WRAP_8021 Register Definition ****
// Address
#define D0F0xE4_WRAP_8021_ADDRESS                               0x8021

// Type
#define D0F0xE4_WRAP_8021_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8021_Lanes10_OFFSET                        0
#define D0F0xE4_WRAP_8021_Lanes10_WIDTH                         4
#define D0F0xE4_WRAP_8021_Lanes10_MASK                          0xf
#define D0F0xE4_WRAP_8021_Lanes32_OFFSET                        4
#define D0F0xE4_WRAP_8021_Lanes32_WIDTH                         4
#define D0F0xE4_WRAP_8021_Lanes32_MASK                          0xf0
#define D0F0xE4_WRAP_8021_Lanes54_OFFSET                        8
#define D0F0xE4_WRAP_8021_Lanes54_WIDTH                         4
#define D0F0xE4_WRAP_8021_Lanes54_MASK                          0xf00
#define D0F0xE4_WRAP_8021_Lanes76_OFFSET                        12
#define D0F0xE4_WRAP_8021_Lanes76_WIDTH                         4
#define D0F0xE4_WRAP_8021_Lanes76_MASK                          0xf000
#define D0F0xE4_WRAP_8021_Lanes98_OFFSET                        16
#define D0F0xE4_WRAP_8021_Lanes98_WIDTH                         4
#define D0F0xE4_WRAP_8021_Lanes98_MASK                          0xf0000
#define D0F0xE4_WRAP_8021_Lanes1110_OFFSET                      20
#define D0F0xE4_WRAP_8021_Lanes1110_WIDTH                       4
#define D0F0xE4_WRAP_8021_Lanes1110_MASK                        0xf00000
#define D0F0xE4_WRAP_8021_Lanes1312_OFFSET                      24
#define D0F0xE4_WRAP_8021_Lanes1312_WIDTH                       4
#define D0F0xE4_WRAP_8021_Lanes1312_MASK                        0xf000000
#define D0F0xE4_WRAP_8021_Lanes1514_OFFSET                      28
#define D0F0xE4_WRAP_8021_Lanes1514_WIDTH                       4
#define D0F0xE4_WRAP_8021_Lanes1514_MASK                        0xf0000000

/// D0F0xE4_WRAP_8021
typedef union {
  struct {                                                              ///<
    UINT32                                                  Lanes10:4 ; ///<
    UINT32                                                  Lanes32:4 ; ///<
    UINT32                                                  Lanes54:4 ; ///<
    UINT32                                                  Lanes76:4 ; ///<
    UINT32                                                  Lanes98:4 ; ///<
    UINT32                                                Lanes1110:4 ; ///<
    UINT32                                                Lanes1312:4 ; ///<
    UINT32                                                Lanes1514:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_8021_STRUCT;

// **** D0F0xE4_WRAP_8022 Register Definition ****
// Address
#define D0F0xE4_WRAP_8022_ADDRESS                               0x8022

// Type
#define D0F0xE4_WRAP_8022_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8022_Lanes10_OFFSET                        0
#define D0F0xE4_WRAP_8022_Lanes10_WIDTH                         4
#define D0F0xE4_WRAP_8022_Lanes10_MASK                          0xf
#define D0F0xE4_WRAP_8022_Lanes32_OFFSET                        4
#define D0F0xE4_WRAP_8022_Lanes32_WIDTH                         4
#define D0F0xE4_WRAP_8022_Lanes32_MASK                          0xf0
#define D0F0xE4_WRAP_8022_Lanes54_OFFSET                        8
#define D0F0xE4_WRAP_8022_Lanes54_WIDTH                         4
#define D0F0xE4_WRAP_8022_Lanes54_MASK                          0xf00
#define D0F0xE4_WRAP_8022_Lanes76_OFFSET                        12
#define D0F0xE4_WRAP_8022_Lanes76_WIDTH                         4
#define D0F0xE4_WRAP_8022_Lanes76_MASK                          0xf000
#define D0F0xE4_WRAP_8022_Lanes98_OFFSET                        16
#define D0F0xE4_WRAP_8022_Lanes98_WIDTH                         4
#define D0F0xE4_WRAP_8022_Lanes98_MASK                          0xf0000
#define D0F0xE4_WRAP_8022_Lanes1110_OFFSET                      20
#define D0F0xE4_WRAP_8022_Lanes1110_WIDTH                       4
#define D0F0xE4_WRAP_8022_Lanes1110_MASK                        0xf00000
#define D0F0xE4_WRAP_8022_Lanes1312_OFFSET                      24
#define D0F0xE4_WRAP_8022_Lanes1312_WIDTH                       4
#define D0F0xE4_WRAP_8022_Lanes1312_MASK                        0xf000000
#define D0F0xE4_WRAP_8022_Lanes1514_OFFSET                      28
#define D0F0xE4_WRAP_8022_Lanes1514_WIDTH                       4
#define D0F0xE4_WRAP_8022_Lanes1514_MASK                        0xf0000000

/// D0F0xE4_WRAP_8022
typedef union {
  struct {                                                              ///<
    UINT32                                                  Lanes10:4 ; ///<
    UINT32                                                  Lanes32:4 ; ///<
    UINT32                                                  Lanes54:4 ; ///<
    UINT32                                                  Lanes76:4 ; ///<
    UINT32                                                  Lanes98:4 ; ///<
    UINT32                                                Lanes1110:4 ; ///<
    UINT32                                                Lanes1312:4 ; ///<
    UINT32                                                Lanes1514:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_8022_STRUCT;

// **** D0F0xE4_WRAP_8023 Register Definition ****
// Address
#define D0F0xE4_WRAP_8023_ADDRESS                               0x8023

// Type
#define D0F0xE4_WRAP_8023_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8023_LaneEnable_OFFSET                     0
#define D0F0xE4_WRAP_8023_LaneEnable_WIDTH                      16
#define D0F0xE4_WRAP_8023_LaneEnable_MASK                       0xffff
#define D0F0xE4_WRAP_8023_Reserved_31_16_OFFSET                 16
#define D0F0xE4_WRAP_8023_Reserved_31_16_WIDTH                  16
#define D0F0xE4_WRAP_8023_Reserved_31_16_MASK                   0xffff0000

/// D0F0xE4_WRAP_8023
typedef union {
  struct {                                                              ///<
    UINT32                                               LaneEnable:16; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_8023_STRUCT;

// **** D0F0xE4_WRAP_8031 Register Definition ****
// Address
#define D0F0xE4_WRAP_8031_ADDRESS                               0x8031

// Type
#define D0F0xE4_WRAP_8031_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8031_LnCntBandwidth_OFFSET                 0
#define D0F0xE4_WRAP_8031_LnCntBandwidth_WIDTH                  10
#define D0F0xE4_WRAP_8031_LnCntBandwidth_MASK                   0x3ff
#define D0F0xE4_WRAP_8031_Reserved_15_10_OFFSET                 10
#define D0F0xE4_WRAP_8031_Reserved_15_10_WIDTH                  6
#define D0F0xE4_WRAP_8031_Reserved_15_10_MASK                   0xfc00
#define D0F0xE4_WRAP_8031_LnCntValid_OFFSET                     16
#define D0F0xE4_WRAP_8031_LnCntValid_WIDTH                      1
#define D0F0xE4_WRAP_8031_LnCntValid_MASK                       0x10000
#define D0F0xE4_WRAP_8031_Reserved_31_17_OFFSET                 17
#define D0F0xE4_WRAP_8031_Reserved_31_17_WIDTH                  15
#define D0F0xE4_WRAP_8031_Reserved_31_17_MASK                   0xfffe0000

/// D0F0xE4_WRAP_8031
typedef union {
  struct {                                                              ///<
    UINT32                                           LnCntBandwidth:10; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                               LnCntValid:1 ; ///<
    UINT32                                           Reserved_31_17:15; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_8031_STRUCT;

// **** D0F0xE4_WRAP_8040 Register Definition ****
// Address
#define D0F0xE4_WRAP_8040_ADDRESS                               0x8040

// Type
#define D0F0xE4_WRAP_8040_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8040_OwnSlice_OFFSET                       0
#define D0F0xE4_WRAP_8040_OwnSlice_WIDTH                        1
#define D0F0xE4_WRAP_8040_OwnSlice_MASK                         0x1
#define D0F0xE4_WRAP_8040_Reserved_31_1_OFFSET                  1
#define D0F0xE4_WRAP_8040_Reserved_31_1_WIDTH                   31
#define D0F0xE4_WRAP_8040_Reserved_31_1_MASK                    0xfffffffe

/// D0F0xE4_WRAP_8040
typedef union {
  struct {                                                              ///<
    UINT32                                                 OwnSlice:1 ; ///<
    UINT32                                            Reserved_31_1:31; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_8040_STRUCT;











// **** D0F0xE4_WRAP_8060 Register Definition ****
// Address
#define D0F0xE4_WRAP_8060_ADDRESS                               0x8060

// Type
#define D0F0xE4_WRAP_8060_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8060_Reconfigure_OFFSET                    0
#define D0F0xE4_WRAP_8060_Reconfigure_WIDTH                     1
#define D0F0xE4_WRAP_8060_Reconfigure_MASK                      0x1
#define D0F0xE4_WRAP_8060_Reserved_1_1_OFFSET                   1
#define D0F0xE4_WRAP_8060_Reserved_1_1_WIDTH                    1
#define D0F0xE4_WRAP_8060_Reserved_1_1_MASK                     0x2
#define D0F0xE4_WRAP_8060_ResetComplete_OFFSET                  2
#define D0F0xE4_WRAP_8060_ResetComplete_WIDTH                   1
#define D0F0xE4_WRAP_8060_ResetComplete_MASK                    0x4
#define D0F0xE4_WRAP_8060_Reserved_15_3_OFFSET                  3
#define D0F0xE4_WRAP_8060_Reserved_15_3_WIDTH                   13
#define D0F0xE4_WRAP_8060_Reserved_15_3_MASK                    0xfff8
#define D0F0xE4_WRAP_8060_Bif0GlobalReset_OFFSET                16
#define D0F0xE4_WRAP_8060_Bif0GlobalReset_WIDTH                 1
#define D0F0xE4_WRAP_8060_Bif0GlobalReset_MASK                  0x10000
#define D0F0xE4_WRAP_8060_Bif0CalibrationReset_OFFSET           17
#define D0F0xE4_WRAP_8060_Bif0CalibrationReset_WIDTH            1
#define D0F0xE4_WRAP_8060_Bif0CalibrationReset_MASK             0x20000
#define D0F0xE4_WRAP_8060_Reserved_31_18_OFFSET                 18
#define D0F0xE4_WRAP_8060_Reserved_31_18_WIDTH                  14
#define D0F0xE4_WRAP_8060_Reserved_31_18_MASK                   0xfffc0000

/// D0F0xE4_WRAP_8060
typedef union {
  struct {                                                              ///<
    UINT32                                              Reconfigure:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                            ResetComplete:1 ; ///<
    UINT32                                            Reserved_15_3:13; ///<
    UINT32                                          Bif0GlobalReset:1 ; ///<
    UINT32                                     Bif0CalibrationReset:1 ; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_8060_STRUCT;

// **** D0F0xE4_WRAP_8062 Register Definition ****
// Address
#define D0F0xE4_WRAP_8062_ADDRESS                               0x8062

// Type
#define D0F0xE4_WRAP_8062_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8062_ReconfigureEn_OFFSET                  0
#define D0F0xE4_WRAP_8062_ReconfigureEn_WIDTH                   1
#define D0F0xE4_WRAP_8062_ReconfigureEn_MASK                    0x1
#define D0F0xE4_WRAP_8062_Reserved_1_1_OFFSET                   1
#define D0F0xE4_WRAP_8062_Reserved_1_1_WIDTH                    1
#define D0F0xE4_WRAP_8062_Reserved_1_1_MASK                     0x2
#define D0F0xE4_WRAP_8062_ResetPeriod_OFFSET                    2
#define D0F0xE4_WRAP_8062_ResetPeriod_WIDTH                     3
#define D0F0xE4_WRAP_8062_ResetPeriod_MASK                      0x1c
#define D0F0xE4_WRAP_8062_Reserved_9_5_OFFSET                   5
#define D0F0xE4_WRAP_8062_Reserved_9_5_WIDTH                    5
#define D0F0xE4_WRAP_8062_Reserved_9_5_MASK                     0x3e0
#define D0F0xE4_WRAP_8062_BlockOnIdle_OFFSET                    10
#define D0F0xE4_WRAP_8062_BlockOnIdle_WIDTH                     1
#define D0F0xE4_WRAP_8062_BlockOnIdle_MASK                      0x400
#define D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET                 11
#define D0F0xE4_WRAP_8062_ConfigXferMode_WIDTH                  1
#define D0F0xE4_WRAP_8062_ConfigXferMode_MASK                   0x800
#define D0F0xE4_WRAP_8062_Reserved_31_12_OFFSET                 12
#define D0F0xE4_WRAP_8062_Reserved_31_12_WIDTH                  20
#define D0F0xE4_WRAP_8062_Reserved_31_12_MASK                   0xfffff000

/// D0F0xE4_WRAP_8062
typedef union {
  struct {                                                              ///<
    UINT32                                            ReconfigureEn:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                              ResetPeriod:3 ; ///<
    UINT32                                             Reserved_9_5:5 ; ///<
    UINT32                                              BlockOnIdle:1 ; ///<
    UINT32                                           ConfigXferMode:1 ; ///<
    UINT32                                           Reserved_31_12:20; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_8062_STRUCT;

// **** D0F0xE4_WRAP_80F0 Register Definition ****
// Address
#define D0F0xE4_WRAP_80F0_ADDRESS                               0x80f0

// Type
#define D0F0xE4_WRAP_80F0_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET                   0
#define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH                    32
#define D0F0xE4_WRAP_80F0_MicroSeconds_MASK                     0xffffffff

/// D0F0xE4_WRAP_80F0
typedef union {
  struct {                                                              ///<
    UINT32                                             MicroSeconds:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_80F0_STRUCT;

// **** D0F0xE4_WRAP_80F1 Register Definition ****
// Address
#define D0F0xE4_WRAP_80F1_ADDRESS                               0x80f1

// Type
#define D0F0xE4_WRAP_80F1_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_80F1_ClockRate_OFFSET                      0
#define D0F0xE4_WRAP_80F1_ClockRate_WIDTH                       8
#define D0F0xE4_WRAP_80F1_ClockRate_MASK                        0xff
#define D0F0xE4_WRAP_80F1_Reserved_31_8_OFFSET                  8
#define D0F0xE4_WRAP_80F1_Reserved_31_8_WIDTH                   24
#define D0F0xE4_WRAP_80F1_Reserved_31_8_MASK                    0xffffff00

/// D0F0xE4_WRAP_80F1
typedef union {
  struct {                                                              ///<
    UINT32                                                ClockRate:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_80F1_STRUCT;

// **** D0F0xE4_WRAP_FFF1 Register Definition ****
// Address
#define D0F0xE4_WRAP_FFF1_ADDRESS                               0xfff1

// Type
#define D0F0xE4_WRAP_FFF1_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_FFF1_Reserved_0_0_OFFSET                   0
#define D0F0xE4_WRAP_FFF1_Reserved_0_0_WIDTH                    1
#define D0F0xE4_WRAP_FFF1_Reserved_0_0_MASK                     0x1
#define D0F0xE4_WRAP_FFF1_PcieSpareGppFch2_OFFSET               1
#define D0F0xE4_WRAP_FFF1_PcieSpareGppFch2_WIDTH                4
#define D0F0xE4_WRAP_FFF1_PcieSpareGppFch2_MASK                 0x1e
#define D0F0xE4_WRAP_FFF1_CoreBphyRstPwrSnifferDis_OFFSET       5
#define D0F0xE4_WRAP_FFF1_CoreBphyRstPwrSnifferDis_WIDTH        1
#define D0F0xE4_WRAP_FFF1_CoreBphyRstPwrSnifferDis_MASK         0x20
#define D0F0xE4_WRAP_FFF1_LcSupportGen2_OFFSET                  6
#define D0F0xE4_WRAP_FFF1_LcSupportGen2_WIDTH                   1
#define D0F0xE4_WRAP_FFF1_LcSupportGen2_MASK                    0x40
#define D0F0xE4_WRAP_FFF1_ROSupportGen2_OFFSET                  7
#define D0F0xE4_WRAP_FFF1_ROSupportGen2_WIDTH                   1
#define D0F0xE4_WRAP_FFF1_ROSupportGen2_MASK                    0x80
#define D0F0xE4_WRAP_FFF1_Reserved_31_8_OFFSET                  8
#define D0F0xE4_WRAP_FFF1_Reserved_31_8_WIDTH                   24
#define D0F0xE4_WRAP_FFF1_Reserved_31_8_MASK                    0xffffff00

/// D0F0xE4_WRAP_FFF1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                         PcieSpareGppFch2:4 ; ///<
    UINT32                                 CoreBphyRstPwrSnifferDis:1 ; ///<
    UINT32                                            LcSupportGen2:1 ; ///<
    UINT32                                            ROSupportGen2:1 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_FFF1_STRUCT;

// **** D0F0xE4_PIF_0010 Register Definition ****
// Address
#define D0F0xE4_PIF_0010_ADDRESS                                0x10

// Type
#define D0F0xE4_PIF_0010_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PIF_0010_Reserved_3_0_OFFSET                    0
#define D0F0xE4_PIF_0010_Reserved_3_0_WIDTH                     4
#define D0F0xE4_PIF_0010_Reserved_3_0_MASK                      0xf
#define D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET                  4
#define D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH                   1
#define D0F0xE4_PIF_0010_EiDetCycleMode_MASK                    0x10
#define D0F0xE4_PIF_0010_Reserved_5_5_OFFSET                    5
#define D0F0xE4_PIF_0010_Reserved_5_5_WIDTH                     1
#define D0F0xE4_PIF_0010_Reserved_5_5_MASK                      0x20
#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET           6
#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH            1
#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_MASK             0x40
#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET               7
#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH                1
#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_MASK                 0x80
#define D0F0xE4_PIF_0010_Reserved_16_8_OFFSET                   8
#define D0F0xE4_PIF_0010_Reserved_16_8_WIDTH                    9
#define D0F0xE4_PIF_0010_Reserved_16_8_MASK                     0x1ff00
#define D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET                     17
#define D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH                      3
#define D0F0xE4_PIF_0010_Ls2ExitTime_MASK                       0xe0000
#define D0F0xE4_PIF_0010_Reserved_31_20_OFFSET                  20
#define D0F0xE4_PIF_0010_Reserved_31_20_WIDTH                   12
#define D0F0xE4_PIF_0010_Reserved_31_20_MASK                    0xfff00000

/// D0F0xE4_PIF_0010
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_3_0:4 ; ///<
    UINT32                                           EiDetCycleMode:1 ; ///<
    UINT32                                             Reserved_5_5:1 ; ///<
    UINT32                                    RxDetectFifoResetMode:1 ; ///<
    UINT32                                        RxDetectTxPwrMode:1 ; ///<
    UINT32                                            Reserved_16_8:9 ; ///<
    UINT32                                              Ls2ExitTime:3 ; ///<
    UINT32                                           Reserved_31_20:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PIF_0010_STRUCT;

// **** D0F0xE4_PIF_0011 Register Definition ****
// Address
#define D0F0xE4_PIF_0011_ADDRESS                                0x11

// Type
#define D0F0xE4_PIF_0011_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PIF_0011_X2Lane10_OFFSET                        0
#define D0F0xE4_PIF_0011_X2Lane10_WIDTH                         1
#define D0F0xE4_PIF_0011_X2Lane10_MASK                          0x1
#define D0F0xE4_PIF_0011_X2Lane32_OFFSET                        1
#define D0F0xE4_PIF_0011_X2Lane32_WIDTH                         1
#define D0F0xE4_PIF_0011_X2Lane32_MASK                          0x2
#define D0F0xE4_PIF_0011_X2Lane54_OFFSET                        2
#define D0F0xE4_PIF_0011_X2Lane54_WIDTH                         1
#define D0F0xE4_PIF_0011_X2Lane54_MASK                          0x4
#define D0F0xE4_PIF_0011_X2Lane76_OFFSET                        3
#define D0F0xE4_PIF_0011_X2Lane76_WIDTH                         1
#define D0F0xE4_PIF_0011_X2Lane76_MASK                          0x8
#define D0F0xE4_PIF_0011_Reserved_7_4_OFFSET                    4
#define D0F0xE4_PIF_0011_Reserved_7_4_WIDTH                     4
#define D0F0xE4_PIF_0011_Reserved_7_4_MASK                      0xf0
#define D0F0xE4_PIF_0011_X4Lane30_OFFSET                        8
#define D0F0xE4_PIF_0011_X4Lane30_WIDTH                         1
#define D0F0xE4_PIF_0011_X4Lane30_MASK                          0x100
#define D0F0xE4_PIF_0011_X4Lane74_OFFSET                        9
#define D0F0xE4_PIF_0011_X4Lane74_WIDTH                         1
#define D0F0xE4_PIF_0011_X4Lane74_MASK                          0x200
#define D0F0xE4_PIF_0011_Reserved_11_10_OFFSET                  10
#define D0F0xE4_PIF_0011_Reserved_11_10_WIDTH                   2
#define D0F0xE4_PIF_0011_Reserved_11_10_MASK                    0xc00
#define D0F0xE4_PIF_0011_X4Lane52_OFFSET                        12
#define D0F0xE4_PIF_0011_X4Lane52_WIDTH                         1
#define D0F0xE4_PIF_0011_X4Lane52_MASK                          0x1000
#define D0F0xE4_PIF_0011_Reserved_15_13_OFFSET                  13
#define D0F0xE4_PIF_0011_Reserved_15_13_WIDTH                   3
#define D0F0xE4_PIF_0011_Reserved_15_13_MASK                    0xe000
#define D0F0xE4_PIF_0011_X8Lane70_OFFSET                        16
#define D0F0xE4_PIF_0011_X8Lane70_WIDTH                         1
#define D0F0xE4_PIF_0011_X8Lane70_MASK                          0x10000
#define D0F0xE4_PIF_0011_Reserved_24_17_OFFSET                  17
#define D0F0xE4_PIF_0011_Reserved_24_17_WIDTH                   8
#define D0F0xE4_PIF_0011_Reserved_24_17_MASK                    0x1fe0000
#define D0F0xE4_PIF_0011_MultiPif_OFFSET                        25
#define D0F0xE4_PIF_0011_MultiPif_WIDTH                         1
#define D0F0xE4_PIF_0011_MultiPif_MASK                          0x2000000
#define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET                  26
#define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH                   6
#define D0F0xE4_PIF_0011_Reserved_31_26_MASK                    0xfc000000

/// D0F0xE4_PIF_0011
typedef union {
  struct {                                                              ///<
    UINT32                                                 X2Lane10:1 ; ///<
    UINT32                                                 X2Lane32:1 ; ///<
    UINT32                                                 X2Lane54:1 ; ///<
    UINT32                                                 X2Lane76:1 ; ///<
    UINT32                                             Reserved_7_4:4 ; ///<
    UINT32                                                 X4Lane30:1 ; ///<
    UINT32                                                 X4Lane74:1 ; ///<
    UINT32                                           Reserved_11_10:2 ; ///<
    UINT32                                                 X4Lane52:1 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                                 X8Lane70:1 ; ///<
    UINT32                                           Reserved_24_17:8 ; ///<
    UINT32                                                 MultiPif:1 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PIF_0011_STRUCT;

// **** D0F0xE4_PIF_0012 Register Definition ****
// Address
#define D0F0xE4_PIF_0012_ADDRESS                                0x12

// Type
#define D0F0xE4_PIF_0012_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET              0
#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH               3
#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK                0x7
#define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET                  3
#define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH                   1
#define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK                    0x8
#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET              4
#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH               3
#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK                0x70
#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET             7
#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH              3
#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK               0x380
#define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET              10
#define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH               3
#define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK                0x1c00
#define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET                  13
#define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH                   3
#define D0F0xE4_PIF_0012_Reserved_15_13_MASK                    0xe000
#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET           16
#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH            1
#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK             0x10000
#define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET                  17
#define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH                   7
#define D0F0xE4_PIF_0012_Reserved_23_17_MASK                    0xfe0000
#define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET                   24
#define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH                    3
#define D0F0xE4_PIF_0012_PllRampUpTime_MASK                     0x7000000
#define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET                  27
#define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH                   1
#define D0F0xE4_PIF_0012_Reserved_27_27_MASK                    0x8000000
#define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET                28
#define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH                 1
#define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK                  0x10000000
#define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET               29
#define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH                3
#define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK                 0xe0000000

/// D0F0xE4_PIF_0012
typedef union {
  struct {                                                              ///<
    UINT32                                       TxPowerStateInTxs2:3 ; ///<
    UINT32                                           ForceRxEnInL0s:1 ; ///<
    UINT32                                       RxPowerStateInRxs2:3 ; ///<
    UINT32                                      PllPowerStateInTxs2:3 ; ///<
    UINT32                                       PllPowerStateInOff:3 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                    Tx2p5clkClockGatingEn:1 ; ///<
    UINT32                                           Reserved_23_17:7 ; ///<
    UINT32                                            PllRampUpTime:3 ; ///<
    UINT32                                           Reserved_27_27:1 ; ///<
    UINT32                                         PllPwrOverrideEn:1 ; ///<
    UINT32                                        PllPwrOverrideVal:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PIF_0012_STRUCT;

// **** D0F0xE4_PIF_0013 Register Definition ****
// Address
#define D0F0xE4_PIF_0013_ADDRESS                                0x13

// Type
#define D0F0xE4_PIF_0013_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_OFFSET              0
#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_WIDTH               3
#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_MASK                0x7
#define D0F0xE4_PIF_0013_ForceRxEnInL0s_OFFSET                  3
#define D0F0xE4_PIF_0013_ForceRxEnInL0s_WIDTH                   1
#define D0F0xE4_PIF_0013_ForceRxEnInL0s_MASK                    0x8
#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_OFFSET              4
#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_WIDTH               3
#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_MASK                0x70
#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_OFFSET             7
#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_WIDTH              3
#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_MASK               0x380
#define D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET              10
#define D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH               3
#define D0F0xE4_PIF_0013_PllPowerStateInOff_MASK                0x1c00
#define D0F0xE4_PIF_0013_Reserved_15_13_OFFSET                  13
#define D0F0xE4_PIF_0013_Reserved_15_13_WIDTH                   3
#define D0F0xE4_PIF_0013_Reserved_15_13_MASK                    0xe000
#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_OFFSET           16
#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_WIDTH            1
#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_MASK             0x10000
#define D0F0xE4_PIF_0013_Reserved_23_17_OFFSET                  17
#define D0F0xE4_PIF_0013_Reserved_23_17_WIDTH                   7
#define D0F0xE4_PIF_0013_Reserved_23_17_MASK                    0xfe0000
#define D0F0xE4_PIF_0013_PllRampUpTime_OFFSET                   24
#define D0F0xE4_PIF_0013_PllRampUpTime_WIDTH                    3
#define D0F0xE4_PIF_0013_PllRampUpTime_MASK                     0x7000000
#define D0F0xE4_PIF_0013_Reserved_27_27_OFFSET                  27
#define D0F0xE4_PIF_0013_Reserved_27_27_WIDTH                   1
#define D0F0xE4_PIF_0013_Reserved_27_27_MASK                    0x8000000
#define D0F0xE4_PIF_0013_PllPwrOverrideEn_OFFSET                28
#define D0F0xE4_PIF_0013_PllPwrOverrideEn_WIDTH                 1
#define D0F0xE4_PIF_0013_PllPwrOverrideEn_MASK                  0x10000000
#define D0F0xE4_PIF_0013_PllPwrOverrideVal_OFFSET               29
#define D0F0xE4_PIF_0013_PllPwrOverrideVal_WIDTH                3
#define D0F0xE4_PIF_0013_PllPwrOverrideVal_MASK                 0xe0000000

/// D0F0xE4_PIF_0013
typedef union {
  struct {                                                              ///<
    UINT32                                       TxPowerStateInTxs2:3 ; ///<
    UINT32                                           ForceRxEnInL0s:1 ; ///<
    UINT32                                       RxPowerStateInRxs2:3 ; ///<
    UINT32                                      PllPowerStateInTxs2:3 ; ///<
    UINT32                                       PllPowerStateInOff:3 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                    Tx2p5clkClockGatingEn:1 ; ///<
    UINT32                                           Reserved_23_17:7 ; ///<
    UINT32                                            PllRampUpTime:3 ; ///<
    UINT32                                           Reserved_27_27:1 ; ///<
    UINT32                                         PllPwrOverrideEn:1 ; ///<
    UINT32                                        PllPwrOverrideVal:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PIF_0013_STRUCT;

// **** D0F0xE4_PIF_0015 Register Definition ****
// Address
#define D0F0xE4_PIF_0015_ADDRESS                                0x15

// Type
#define D0F0xE4_PIF_0015_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PIF_0015_TxPhyStatus00_OFFSET                   0
#define D0F0xE4_PIF_0015_TxPhyStatus00_WIDTH                    1
#define D0F0xE4_PIF_0015_TxPhyStatus00_MASK                     0x1
#define D0F0xE4_PIF_0015_TxPhyStatus01_OFFSET                   1
#define D0F0xE4_PIF_0015_TxPhyStatus01_WIDTH                    1
#define D0F0xE4_PIF_0015_TxPhyStatus01_MASK                     0x2
#define D0F0xE4_PIF_0015_TxPhyStatus02_OFFSET                   2
#define D0F0xE4_PIF_0015_TxPhyStatus02_WIDTH                    1
#define D0F0xE4_PIF_0015_TxPhyStatus02_MASK                     0x4
#define D0F0xE4_PIF_0015_TxPhyStatus03_OFFSET                   3
#define D0F0xE4_PIF_0015_TxPhyStatus03_WIDTH                    1
#define D0F0xE4_PIF_0015_TxPhyStatus03_MASK                     0x8
#define D0F0xE4_PIF_0015_TxPhyStatus04_OFFSET                   4
#define D0F0xE4_PIF_0015_TxPhyStatus04_WIDTH                    1
#define D0F0xE4_PIF_0015_TxPhyStatus04_MASK                     0x10
#define D0F0xE4_PIF_0015_TxPhyStatus05_OFFSET                   5
#define D0F0xE4_PIF_0015_TxPhyStatus05_WIDTH                    1
#define D0F0xE4_PIF_0015_TxPhyStatus05_MASK                     0x20
#define D0F0xE4_PIF_0015_TxPhyStatus06_OFFSET                   6
#define D0F0xE4_PIF_0015_TxPhyStatus06_WIDTH                    1
#define D0F0xE4_PIF_0015_TxPhyStatus06_MASK                     0x40
#define D0F0xE4_PIF_0015_TxPhyStatus07_OFFSET                   7
#define D0F0xE4_PIF_0015_TxPhyStatus07_WIDTH                    1
#define D0F0xE4_PIF_0015_TxPhyStatus07_MASK                     0x80
#define D0F0xE4_PIF_0015_Reserved_31_8_OFFSET                   8
#define D0F0xE4_PIF_0015_Reserved_31_8_WIDTH                    24
#define D0F0xE4_PIF_0015_Reserved_31_8_MASK                     0xffffff00

/// D0F0xE4_PIF_0015
typedef union {
  struct {                                                              ///<
    UINT32                                            TxPhyStatus00:1 ; ///<
    UINT32                                            TxPhyStatus01:1 ; ///<
    UINT32                                            TxPhyStatus02:1 ; ///<
    UINT32                                            TxPhyStatus03:1 ; ///<
    UINT32                                            TxPhyStatus04:1 ; ///<
    UINT32                                            TxPhyStatus05:1 ; ///<
    UINT32                                            TxPhyStatus06:1 ; ///<
    UINT32                                            TxPhyStatus07:1 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PIF_0015_STRUCT;

// **** D0F0xE4_CORE_0002 Register Definition ****
// Address
#define D0F0xE4_CORE_0002_ADDRESS                               0x2

// Type
#define D0F0xE4_CORE_0002_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_CORE_0002_HwDebug_0__OFFSET                     0
#define D0F0xE4_CORE_0002_HwDebug_0__WIDTH                      1
#define D0F0xE4_CORE_0002_HwDebug_0__MASK                       0x1
#define D0F0xE4_CORE_0002_Reserved_31_1_OFFSET                  1
#define D0F0xE4_CORE_0002_Reserved_31_1_WIDTH                   31
#define D0F0xE4_CORE_0002_Reserved_31_1_MASK                    0xfffffffe

/// D0F0xE4_CORE_0002
typedef union {
  struct {                                                              ///<
    UINT32                                               HwDebug_0_:1 ; ///<
    UINT32                                            Reserved_31_1:31; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_CORE_0002_STRUCT;

// **** D0F0xE4_CORE_0010 Register Definition ****
// Address
#define D0F0xE4_CORE_0010_ADDRESS                               0x10

// Type
#define D0F0xE4_CORE_0010_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET                   0
#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH                    1
#define D0F0xE4_CORE_0010_HwInitWrLock_MASK                     0x1
#define D0F0xE4_CORE_0010_Reserved_8_1_OFFSET                   1
#define D0F0xE4_CORE_0010_Reserved_8_1_WIDTH                    8
#define D0F0xE4_CORE_0010_Reserved_8_1_MASK                     0x1fe
#define D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET                  9
#define D0F0xE4_CORE_0010_UmiNpMemWrite_WIDTH                   1
#define D0F0xE4_CORE_0010_UmiNpMemWrite_MASK                    0x200
#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET             10
#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_WIDTH              3
#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK               0x1c00
#define D0F0xE4_CORE_0010_Reserved_31_13_OFFSET                 13
#define D0F0xE4_CORE_0010_Reserved_31_13_WIDTH                  19
#define D0F0xE4_CORE_0010_Reserved_31_13_MASK                   0xffffe000

/// D0F0xE4_CORE_0010
typedef union {
  struct {                                                              ///<
    UINT32                                             HwInitWrLock:1 ; ///<
    UINT32                                             Reserved_8_1:8 ; ///<
    UINT32                                            UmiNpMemWrite:1 ; ///<
    UINT32                                       RxSbAdjPayloadSize:3 ; ///<
    UINT32                                           Reserved_31_13:19; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_CORE_0010_STRUCT;

// **** D0F0xE4_CORE_0011 Register Definition ****
// Address
#define D0F0xE4_CORE_0011_ADDRESS                               0x11

// Type
#define D0F0xE4_CORE_0011_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_CORE_0011_DynClkLatency_OFFSET                  0
#define D0F0xE4_CORE_0011_DynClkLatency_WIDTH                   4
#define D0F0xE4_CORE_0011_DynClkLatency_MASK                    0xf
#define D0F0xE4_CORE_0011_Reserved_15_4_OFFSET                  4
#define D0F0xE4_CORE_0011_Reserved_15_4_WIDTH                   12
#define D0F0xE4_CORE_0011_Reserved_15_4_MASK                    0xfff0
#define D0F0xE4_CORE_0011_CiMaxPayloadSizeMode_OFFSET           16
#define D0F0xE4_CORE_0011_CiMaxPayloadSizeMode_WIDTH            1
#define D0F0xE4_CORE_0011_CiMaxPayloadSizeMode_MASK             0x10000
#define D0F0xE4_CORE_0011_CiPrivMaxPayloadSize_OFFSET           17
#define D0F0xE4_CORE_0011_CiPrivMaxPayloadSize_WIDTH            3
#define D0F0xE4_CORE_0011_CiPrivMaxPayloadSize_MASK             0xe0000
#define D0F0xE4_CORE_0011_CiMaxReadRequestSizeMode_OFFSET       20
#define D0F0xE4_CORE_0011_CiMaxReadRequestSizeMode_WIDTH        1
#define D0F0xE4_CORE_0011_CiMaxReadRequestSizeMode_MASK         0x100000
#define D0F0xE4_CORE_0011_CiPrivMaxReadRequestSize_OFFSET       21
#define D0F0xE4_CORE_0011_CiPrivMaxReadRequestSize_WIDTH        3
#define D0F0xE4_CORE_0011_CiPrivMaxReadRequestSize_MASK         0xe00000
#define D0F0xE4_CORE_0011_CiMaxReadSafeMode_OFFSET              24
#define D0F0xE4_CORE_0011_CiMaxReadSafeMode_WIDTH               1
#define D0F0xE4_CORE_0011_CiMaxReadSafeMode_MASK                0x1000000
#define D0F0xE4_CORE_0011_CiExtendedTagEnOverride_OFFSET        25
#define D0F0xE4_CORE_0011_CiExtendedTagEnOverride_WIDTH         1
#define D0F0xE4_CORE_0011_CiExtendedTagEnOverride_MASK          0x2000000
#define D0F0xE4_CORE_0011_CiMaxCplPayloadSizeMode_OFFSET        26
#define D0F0xE4_CORE_0011_CiMaxCplPayloadSizeMode_WIDTH         1
#define D0F0xE4_CORE_0011_CiMaxCplPayloadSizeMode_MASK          0x4000000
#define D0F0xE4_CORE_0011_CiPrivMaxCplPayloadSize_OFFSET        27
#define D0F0xE4_CORE_0011_CiPrivMaxCplPayloadSize_WIDTH         3
#define D0F0xE4_CORE_0011_CiPrivMaxCplPayloadSize_MASK          0x38000000
#define D0F0xE4_CORE_0011_Reserved_31_30_OFFSET                 30
#define D0F0xE4_CORE_0011_Reserved_31_30_WIDTH                  2
#define D0F0xE4_CORE_0011_Reserved_31_30_MASK                   0xc0000000

/// D0F0xE4_CORE_0011
typedef union {
  struct {                                                              ///<
    UINT32                                            DynClkLatency:4 ; ///<
    UINT32                                            Reserved_15_4:12; ///<
    UINT32                                     CiMaxPayloadSizeMode:1 ; ///<
    UINT32                                     CiPrivMaxPayloadSize:3 ; ///<
    UINT32                                 CiMaxReadRequestSizeMode:1 ; ///<
    UINT32                                 CiPrivMaxReadRequestSize:3 ; ///<
    UINT32                                        CiMaxReadSafeMode:1 ; ///<
    UINT32                                  CiExtendedTagEnOverride:1 ; ///<
    UINT32                                  CiMaxCplPayloadSizeMode:1 ; ///<
    UINT32                                  CiPrivMaxCplPayloadSize:3 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_CORE_0011_STRUCT;

// **** D0F0xE4_CORE_001C Register Definition ****
// Address
#define D0F0xE4_CORE_001C_ADDRESS                               0x1c

// Type
#define D0F0xE4_CORE_001C_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET              0
#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_WIDTH               1
#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK                0x1
#define D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET                  1
#define D0F0xE4_CORE_001C_TxArbSlvLimit_WIDTH                   5
#define D0F0xE4_CORE_001C_TxArbSlvLimit_MASK                    0x3e
#define D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET                  6
#define D0F0xE4_CORE_001C_TxArbMstLimit_WIDTH                   5
#define D0F0xE4_CORE_001C_TxArbMstLimit_MASK                    0x7c0
#define D0F0xE4_CORE_001C_Reserved_31_11_OFFSET                 11
#define D0F0xE4_CORE_001C_Reserved_31_11_WIDTH                  21
#define D0F0xE4_CORE_001C_Reserved_31_11_MASK                   0xfffff800

/// D0F0xE4_CORE_001C
typedef union {
  struct {                                                              ///<
    UINT32                                        TxArbRoundRobinEn:1 ; ///<
    UINT32                                            TxArbSlvLimit:5 ; ///<
    UINT32                                            TxArbMstLimit:5 ; ///<
    UINT32                                           Reserved_31_11:21; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_CORE_001C_STRUCT;

// **** D0F0xE4_CORE_0020 Register Definition ****
// Address
#define D0F0xE4_CORE_0020_ADDRESS                               0x20

// Type
#define D0F0xE4_CORE_0020_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_CORE_0020_Reserved_7_0_OFFSET                   0
#define D0F0xE4_CORE_0020_Reserved_7_0_WIDTH                    8
#define D0F0xE4_CORE_0020_Reserved_7_0_MASK                     0xff
#define D0F0xE4_CORE_0020_CiSlvOrderingDis_OFFSET               8
#define D0F0xE4_CORE_0020_CiSlvOrderingDis_WIDTH                1
#define D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK                 0x100
#define D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET                9
#define D0F0xE4_CORE_0020_CiRcOrderingDis_WIDTH                 1
#define D0F0xE4_CORE_0020_CiRcOrderingDis_MASK                  0x200
#define D0F0xE4_CORE_0020_Reserved_31_10_OFFSET                 10
#define D0F0xE4_CORE_0020_Reserved_31_10_WIDTH                  22
#define D0F0xE4_CORE_0020_Reserved_31_10_MASK                   0xfffffc00

/// D0F0xE4_CORE_0020
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_7_0:8 ; ///<
    UINT32                                         CiSlvOrderingDis:1 ; ///<
    UINT32                                          CiRcOrderingDis:1 ; ///<
    UINT32                                           Reserved_31_10:22; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_CORE_0020_STRUCT;

// **** D0F0xE4_CORE_0040 Register Definition ****
// Address
#define D0F0xE4_CORE_0040_ADDRESS                               0x40

// Type
#define D0F0xE4_CORE_0040_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_CORE_0040_Reserved_13_0_OFFSET                  0
#define D0F0xE4_CORE_0040_Reserved_13_0_WIDTH                   14
#define D0F0xE4_CORE_0040_Reserved_13_0_MASK                    0x3fff
#define D0F0xE4_CORE_0040_PElecIdleMode_OFFSET                  14
#define D0F0xE4_CORE_0040_PElecIdleMode_WIDTH                   2
#define D0F0xE4_CORE_0040_PElecIdleMode_MASK                    0xc000
#define D0F0xE4_CORE_0040_Reserved_31_16_OFFSET                 16
#define D0F0xE4_CORE_0040_Reserved_31_16_WIDTH                  16
#define D0F0xE4_CORE_0040_Reserved_31_16_MASK                   0xffff0000

/// D0F0xE4_CORE_0040
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_13_0:14; ///<
    UINT32                                            PElecIdleMode:2 ; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_CORE_0040_STRUCT;

// **** D0F0xE4_CORE_00B0 Register Definition ****
// Address
#define D0F0xE4_CORE_00B0_ADDRESS                               0xb0

// Type
#define D0F0xE4_CORE_00B0_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET                   0
#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH                    2
#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK                     0x3
#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET                   2
#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH                    1
#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK                     0x4
#define D0F0xE4_CORE_00B0_Reserved_4_3_OFFSET                   3
#define D0F0xE4_CORE_00B0_Reserved_4_3_WIDTH                    2
#define D0F0xE4_CORE_00B0_Reserved_4_3_MASK                     0x18
#define D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET                   5
#define D0F0xE4_CORE_00B0_StrapF0AerEn_WIDTH                    1
#define D0F0xE4_CORE_00B0_StrapF0AerEn_MASK                     0x20
#define D0F0xE4_CORE_00B0_Reserved_31_6_OFFSET                  6
#define D0F0xE4_CORE_00B0_Reserved_31_6_WIDTH                   26
#define D0F0xE4_CORE_00B0_Reserved_31_6_MASK                    0xffffffc0

/// D0F0xE4_CORE_00B0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_1_0:2 ; ///<
    UINT32                                             StrapF0MsiEn:1 ; ///<
    UINT32                                             Reserved_4_3:2 ; ///<
    UINT32                                             StrapF0AerEn:1 ; ///<
    UINT32                                            Reserved_31_6:26; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_CORE_00B0_STRUCT;

// **** D0F0xE4_CORE_00C0 Register Definition ****
// Address
#define D0F0xE4_CORE_00C0_ADDRESS                               0xc0

// Type
#define D0F0xE4_CORE_00C0_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_CORE_00C0_Reserved_27_0_OFFSET                  0
#define D0F0xE4_CORE_00C0_Reserved_27_0_WIDTH                   28
#define D0F0xE4_CORE_00C0_Reserved_27_0_MASK                    0xfffffff
#define D0F0xE4_CORE_00C0_StrapReverseAll_OFFSET                28
#define D0F0xE4_CORE_00C0_StrapReverseAll_WIDTH                 1
#define D0F0xE4_CORE_00C0_StrapReverseAll_MASK                  0x10000000
#define D0F0xE4_CORE_00C0_StrapMstAdr64En_OFFSET                29
#define D0F0xE4_CORE_00C0_StrapMstAdr64En_WIDTH                 1
#define D0F0xE4_CORE_00C0_StrapMstAdr64En_MASK                  0x20000000
#define D0F0xE4_CORE_00C0_StrapFlrEn_OFFSET                     30
#define D0F0xE4_CORE_00C0_StrapFlrEn_WIDTH                      1
#define D0F0xE4_CORE_00C0_StrapFlrEn_MASK                       0x40000000
#define D0F0xE4_CORE_00C0_Reserved_31_31_OFFSET                 31
#define D0F0xE4_CORE_00C0_Reserved_31_31_WIDTH                  1
#define D0F0xE4_CORE_00C0_Reserved_31_31_MASK                   0x80000000

/// D0F0xE4_CORE_00C0
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_27_0:28; ///<
    UINT32                                          StrapReverseAll:1 ; ///<
    UINT32                                          StrapMstAdr64En:1 ; ///<
    UINT32                                               StrapFlrEn:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_CORE_00C0_STRUCT;

// **** D0F0xE4_CORE_00C1 Register Definition ****
// Address
#define D0F0xE4_CORE_00C1_ADDRESS                               0xc1

// Type
#define D0F0xE4_CORE_00C1_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET   0
#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_WIDTH    1
#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK     0x1
#define D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET            1
#define D0F0xE4_CORE_00C1_StrapGen2Compliance_WIDTH             1
#define D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK              0x2
#define D0F0xE4_CORE_00C1_Reserved_31_2_OFFSET                  2
#define D0F0xE4_CORE_00C1_Reserved_31_2_WIDTH                   30
#define D0F0xE4_CORE_00C1_Reserved_31_2_MASK                    0xfffffffc

/// D0F0xE4_CORE_00C1
typedef union {
  struct {                                                              ///<
    UINT32                             StrapLinkBwNotificationCapEn:1 ; ///<
    UINT32                                      StrapGen2Compliance:1 ; ///<
    UINT32                                            Reserved_31_2:30; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_CORE_00C1_STRUCT;

// **** D0F0xE4_PHY_0009 Register Definition ****
// Address
#define D0F0xE4_PHY_0009_ADDRESS                                0x9

// Type
#define D0F0xE4_PHY_0009_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PHY_0009_Reserved_23_0_OFFSET                   0
#define D0F0xE4_PHY_0009_Reserved_23_0_WIDTH                    24
#define D0F0xE4_PHY_0009_Reserved_23_0_MASK                     0xffffff
#define D0F0xE4_PHY_0009_ClkOff_OFFSET                          24
#define D0F0xE4_PHY_0009_ClkOff_WIDTH                           1
#define D0F0xE4_PHY_0009_ClkOff_MASK                            0x1000000
#define D0F0xE4_PHY_0009_DisplayStream_OFFSET                   25
#define D0F0xE4_PHY_0009_DisplayStream_WIDTH                    1
#define D0F0xE4_PHY_0009_DisplayStream_MASK                     0x2000000
#define D0F0xE4_PHY_0009_Reserved_27_26_OFFSET                  26
#define D0F0xE4_PHY_0009_Reserved_27_26_WIDTH                   2
#define D0F0xE4_PHY_0009_Reserved_27_26_MASK                    0xc000000
#define D0F0xE4_PHY_0009_CascadedPllSel_OFFSET                  28
#define D0F0xE4_PHY_0009_CascadedPllSel_WIDTH                   1
#define D0F0xE4_PHY_0009_CascadedPllSel_MASK                    0x10000000
#define D0F0xE4_PHY_0009_Reserved_30_29_OFFSET                  29
#define D0F0xE4_PHY_0009_Reserved_30_29_WIDTH                   2
#define D0F0xE4_PHY_0009_Reserved_30_29_MASK                    0x60000000
#define D0F0xE4_PHY_0009_PCIePllSel_OFFSET                      31
#define D0F0xE4_PHY_0009_PCIePllSel_WIDTH                       1
#define D0F0xE4_PHY_0009_PCIePllSel_MASK                        0x80000000

/// D0F0xE4_PHY_0009
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_23_0:24; ///<
    UINT32                                                   ClkOff:1 ; ///<
    UINT32                                            DisplayStream:1 ; ///<
    UINT32                                           Reserved_27_26:2 ; ///<
    UINT32                                           CascadedPllSel:1 ; ///<
    UINT32                                           Reserved_30_29:2 ; ///<
    UINT32                                               PCIePllSel:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PHY_0009_STRUCT;

// **** D0F0xE4_PHY_000A Register Definition ****
// Address
#define D0F0xE4_PHY_000A_ADDRESS                                0xa

// Type
#define D0F0xE4_PHY_000A_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PHY_000A_Reserved_23_0_OFFSET                   0
#define D0F0xE4_PHY_000A_Reserved_23_0_WIDTH                    24
#define D0F0xE4_PHY_000A_Reserved_23_0_MASK                     0xffffff
#define D0F0xE4_PHY_000A_ClkOff_OFFSET                          24
#define D0F0xE4_PHY_000A_ClkOff_WIDTH                           1
#define D0F0xE4_PHY_000A_ClkOff_MASK                            0x1000000
#define D0F0xE4_PHY_000A_DisplayStream_OFFSET                   25
#define D0F0xE4_PHY_000A_DisplayStream_WIDTH                    1
#define D0F0xE4_PHY_000A_DisplayStream_MASK                     0x2000000
#define D0F0xE4_PHY_000A_Reserved_27_26_OFFSET                  26
#define D0F0xE4_PHY_000A_Reserved_27_26_WIDTH                   2
#define D0F0xE4_PHY_000A_Reserved_27_26_MASK                    0xc000000
#define D0F0xE4_PHY_000A_CascadedPllSel_OFFSET                  28
#define D0F0xE4_PHY_000A_CascadedPllSel_WIDTH                   1
#define D0F0xE4_PHY_000A_CascadedPllSel_MASK                    0x10000000
#define D0F0xE4_PHY_000A_Reserved_30_29_OFFSET                  29
#define D0F0xE4_PHY_000A_Reserved_30_29_WIDTH                   2
#define D0F0xE4_PHY_000A_Reserved_30_29_MASK                    0x60000000
#define D0F0xE4_PHY_000A_PCIePllSel_OFFSET                      31
#define D0F0xE4_PHY_000A_PCIePllSel_WIDTH                       1
#define D0F0xE4_PHY_000A_PCIePllSel_MASK                        0x80000000

/// D0F0xE4_PHY_000A
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_23_0:24; ///<
    UINT32                                                   ClkOff:1 ; ///<
    UINT32                                            DisplayStream:1 ; ///<
    UINT32                                           Reserved_27_26:2 ; ///<
    UINT32                                           CascadedPllSel:1 ; ///<
    UINT32                                           Reserved_30_29:2 ; ///<
    UINT32                                               PCIePllSel:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PHY_000A_STRUCT;

// **** D0F0xE4_PHY_000B Register Definition ****
// Address
#define D0F0xE4_PHY_000B_ADDRESS                                0xb

// Type
#define D0F0xE4_PHY_000B_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PHY_000B_TxPwrSbiEn_OFFSET                      0
#define D0F0xE4_PHY_000B_TxPwrSbiEn_WIDTH                       1
#define D0F0xE4_PHY_000B_TxPwrSbiEn_MASK                        0x1
#define D0F0xE4_PHY_000B_RxPwrSbiEn_OFFSET                      1
#define D0F0xE4_PHY_000B_RxPwrSbiEn_WIDTH                       1
#define D0F0xE4_PHY_000B_RxPwrSbiEn_MASK                        0x2
#define D0F0xE4_PHY_000B_PcieModeSbiEn_OFFSET                   2
#define D0F0xE4_PHY_000B_PcieModeSbiEn_WIDTH                    1
#define D0F0xE4_PHY_000B_PcieModeSbiEn_MASK                     0x4
#define D0F0xE4_PHY_000B_FreqDivSbiEn_OFFSET                    3
#define D0F0xE4_PHY_000B_FreqDivSbiEn_WIDTH                     1
#define D0F0xE4_PHY_000B_FreqDivSbiEn_MASK                      0x8
#define D0F0xE4_PHY_000B_DllLockSbiEn_OFFSET                    4
#define D0F0xE4_PHY_000B_DllLockSbiEn_WIDTH                     1
#define D0F0xE4_PHY_000B_DllLockSbiEn_MASK                      0x10
#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_OFFSET               5
#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_WIDTH                1
#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_MASK                 0x20
#define D0F0xE4_PHY_000B_SkipBitSbiEn_OFFSET                    6
#define D0F0xE4_PHY_000B_SkipBitSbiEn_WIDTH                     1
#define D0F0xE4_PHY_000B_SkipBitSbiEn_MASK                      0x40
#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_OFFSET              7
#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_WIDTH               1
#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_MASK                0x80
#define D0F0xE4_PHY_000B_EiDetSbiEn_OFFSET                      8
#define D0F0xE4_PHY_000B_EiDetSbiEn_WIDTH                       1
#define D0F0xE4_PHY_000B_EiDetSbiEn_MASK                        0x100
#define D0F0xE4_PHY_000B_Reserved_13_9_OFFSET                   9
#define D0F0xE4_PHY_000B_Reserved_13_9_WIDTH                    5
#define D0F0xE4_PHY_000B_Reserved_13_9_MASK                     0x3e00
#define D0F0xE4_PHY_000B_MargPktSbiEn_OFFSET                    14
#define D0F0xE4_PHY_000B_MargPktSbiEn_WIDTH                     1
#define D0F0xE4_PHY_000B_MargPktSbiEn_MASK                      0x4000
#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_OFFSET                  15
#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_WIDTH                   1
#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_MASK                    0x8000
#define D0F0xE4_PHY_000B_Reserved_31_16_OFFSET                  16
#define D0F0xE4_PHY_000B_Reserved_31_16_WIDTH                   16
#define D0F0xE4_PHY_000B_Reserved_31_16_MASK                    0xffff0000

/// D0F0xE4_PHY_000B
typedef union {
  struct {                                                              ///<
    UINT32                                               TxPwrSbiEn:1 ; ///<
    UINT32                                               RxPwrSbiEn:1 ; ///<
    UINT32                                            PcieModeSbiEn:1 ; ///<
    UINT32                                             FreqDivSbiEn:1 ; ///<
    UINT32                                             DllLockSbiEn:1 ; ///<
    UINT32                                        OffsetCancelSbiEn:1 ; ///<
    UINT32                                             SkipBitSbiEn:1 ; ///<
    UINT32                                       IncoherentClkSbiEn:1 ; ///<
    UINT32                                               EiDetSbiEn:1 ; ///<
    UINT32                                            Reserved_13_9:5 ; ///<
    UINT32                                             MargPktSbiEn:1 ; ///<
    UINT32                                           PllCmpPktSbiEn:1 ; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PHY_000B_STRUCT;

// **** D0F0xE4_PHY_2000 Register Definition ****
// Address
#define D0F0xE4_PHY_2000_ADDRESS                                0x2000

// Type
#define D0F0xE4_PHY_2000_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PHY_2000_PllPowerDownEn_OFFSET                  0
#define D0F0xE4_PHY_2000_PllPowerDownEn_WIDTH                   3
#define D0F0xE4_PHY_2000_PllPowerDownEn_MASK                    0x7
#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_OFFSET               3
#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_WIDTH                1
#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_MASK                 0x8
#define D0F0xE4_PHY_2000_Reserved_31_4_OFFSET                   4
#define D0F0xE4_PHY_2000_Reserved_31_4_WIDTH                    28
#define D0F0xE4_PHY_2000_Reserved_31_4_MASK                     0xfffffff0

/// D0F0xE4_PHY_2000
typedef union {
  struct {                                                              ///<
    UINT32                                           PllPowerDownEn:3 ; ///<
    UINT32                                        PllAutoPwrDownDis:1 ; ///<
    UINT32                                            Reserved_31_4:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PHY_2000_STRUCT;

// **** D0F0xE4_PHY_2002 Register Definition ****
// Address
#define D0F0xE4_PHY_2002_ADDRESS                                0x2002

// Type
#define D0F0xE4_PHY_2002_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PHY_2002_Reserved_26_0_OFFSET                   0
#define D0F0xE4_PHY_2002_Reserved_26_0_WIDTH                    27
#define D0F0xE4_PHY_2002_Reserved_26_0_MASK                     0x7ffffff
#define D0F0xE4_PHY_2002_RoCalEn_OFFSET                         27
#define D0F0xE4_PHY_2002_RoCalEn_WIDTH                          1
#define D0F0xE4_PHY_2002_RoCalEn_MASK                           0x8000000
#define D0F0xE4_PHY_2002_Reserved_30_28_OFFSET                  28
#define D0F0xE4_PHY_2002_Reserved_30_28_WIDTH                   3
#define D0F0xE4_PHY_2002_Reserved_30_28_MASK                    0x70000000
#define D0F0xE4_PHY_2002_IsLc_OFFSET                            31
#define D0F0xE4_PHY_2002_IsLc_WIDTH                             1
#define D0F0xE4_PHY_2002_IsLc_MASK                              0x80000000

/// D0F0xE4_PHY_2002
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_26_0:27; ///<
    UINT32                                                  RoCalEn:1 ; ///<
    UINT32                                           Reserved_30_28:3 ; ///<
    UINT32                                                     IsLc:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PHY_2002_STRUCT;

// **** D0F0xE4_PHY_2005 Register Definition ****
// Address
#define D0F0xE4_PHY_2005_ADDRESS                                0x2005

// Type
#define D0F0xE4_PHY_2005_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PHY_2005_PllClkFreq_OFFSET                      0
#define D0F0xE4_PHY_2005_PllClkFreq_WIDTH                       4
#define D0F0xE4_PHY_2005_PllClkFreq_MASK                        0xf
#define D0F0xE4_PHY_2005_Reserved_8_4_OFFSET                    4
#define D0F0xE4_PHY_2005_Reserved_8_4_WIDTH                     5
#define D0F0xE4_PHY_2005_Reserved_8_4_MASK                      0x1f0
#define D0F0xE4_PHY_2005_PllClkFreqExt_OFFSET                   9
#define D0F0xE4_PHY_2005_PllClkFreqExt_WIDTH                    2
#define D0F0xE4_PHY_2005_PllClkFreqExt_MASK                     0x600
#define D0F0xE4_PHY_2005_Reserved_12_11_OFFSET                  11
#define D0F0xE4_PHY_2005_Reserved_12_11_WIDTH                   2
#define D0F0xE4_PHY_2005_Reserved_12_11_MASK                    0x1800
#define D0F0xE4_PHY_2005_PllMode_OFFSET                         13
#define D0F0xE4_PHY_2005_PllMode_WIDTH                          2
#define D0F0xE4_PHY_2005_PllMode_MASK                           0x6000
#define D0F0xE4_PHY_2005_Reserved_31_15_OFFSET                  15
#define D0F0xE4_PHY_2005_Reserved_31_15_WIDTH                   17
#define D0F0xE4_PHY_2005_Reserved_31_15_MASK                    0xffff8000

/// D0F0xE4_PHY_2005
typedef union {
  struct {                                                              ///<
    UINT32                                               PllClkFreq:4 ; ///<
    UINT32                                             Reserved_8_4:5 ; ///<
    UINT32                                            PllClkFreqExt:2 ; ///<
    UINT32                                           Reserved_12_11:2 ; ///<
    UINT32                                                  PllMode:2 ; ///<
    UINT32                                           Reserved_31_15:17; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PHY_2005_STRUCT;

// **** D0F0xE4_PHY_2008 Register Definition ****
// Address
#define D0F0xE4_PHY_2008_ADDRESS                                0x2008

// Type
#define D0F0xE4_PHY_2008_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PHY_2008_PllControlUpdate_OFFSET                0
#define D0F0xE4_PHY_2008_PllControlUpdate_WIDTH                 1
#define D0F0xE4_PHY_2008_PllControlUpdate_MASK                  0x1
#define D0F0xE4_PHY_2008_Reserved_22_1_OFFSET                   1
#define D0F0xE4_PHY_2008_Reserved_22_1_WIDTH                    22
#define D0F0xE4_PHY_2008_Reserved_22_1_MASK                     0x7ffffe
#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__OFFSET              23
#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__WIDTH               3
#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__MASK                0x3800000
#define D0F0xE4_PHY_2008_Reserved_28_26_OFFSET                  26
#define D0F0xE4_PHY_2008_Reserved_28_26_WIDTH                   3
#define D0F0xE4_PHY_2008_Reserved_28_26_MASK                    0x1c000000
#define D0F0xE4_PHY_2008_VdDetectEn_OFFSET                      29
#define D0F0xE4_PHY_2008_VdDetectEn_WIDTH                       1
#define D0F0xE4_PHY_2008_VdDetectEn_MASK                        0x20000000
#define D0F0xE4_PHY_2008_Reserved_31_30_OFFSET                  30
#define D0F0xE4_PHY_2008_Reserved_31_30_WIDTH                   2
#define D0F0xE4_PHY_2008_Reserved_31_30_MASK                    0xc0000000

/// D0F0xE4_PHY_2008
typedef union {
  struct {                                                              ///<
    UINT32                                         PllControlUpdate:1 ; ///<
    UINT32                                            Reserved_22_1:22; ///<
    UINT32                                       MeasCycCntVal_2_0_:3 ; ///<
    UINT32                                           Reserved_28_26:3 ; ///<
    UINT32                                               VdDetectEn:1 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PHY_2008_STRUCT;

// **** D0F0xE4_PHY_4001 Register Definition ****
// Address
#define D0F0xE4_PHY_4001_ADDRESS                                0x4001

// Type
#define D0F0xE4_PHY_4001_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PHY_4001_Reserved_14_0_OFFSET                   0
#define D0F0xE4_PHY_4001_Reserved_14_0_WIDTH                    15
#define D0F0xE4_PHY_4001_Reserved_14_0_MASK                     0x7fff
#define D0F0xE4_PHY_4001_ForceDccRecalc_OFFSET                  15
#define D0F0xE4_PHY_4001_ForceDccRecalc_WIDTH                   1
#define D0F0xE4_PHY_4001_ForceDccRecalc_MASK                    0x8000
#define D0F0xE4_PHY_4001_Reserved_31_16_OFFSET                  16
#define D0F0xE4_PHY_4001_Reserved_31_16_WIDTH                   16
#define D0F0xE4_PHY_4001_Reserved_31_16_MASK                    0xffff0000

/// D0F0xE4_PHY_4001
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_14_0:15; ///<
    UINT32                                           ForceDccRecalc:1 ; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PHY_4001_STRUCT;

// **** D0F0xE4_PHY_4002 Register Definition ****
// Address
#define D0F0xE4_PHY_4002_ADDRESS                                0x4002

// Type
#define D0F0xE4_PHY_4002_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PHY_4002_Reserved_2_0_OFFSET                    0
#define D0F0xE4_PHY_4002_Reserved_2_0_WIDTH                     3
#define D0F0xE4_PHY_4002_Reserved_2_0_MASK                      0x7
#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_OFFSET              3
#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_WIDTH               1
#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_MASK                0x8
#define D0F0xE4_PHY_4002_SamClkPiOffset_OFFSET                  4
#define D0F0xE4_PHY_4002_SamClkPiOffset_WIDTH                   3
#define D0F0xE4_PHY_4002_SamClkPiOffset_MASK                    0x70
#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_OFFSET                7
#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_WIDTH                 1
#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_MASK                  0x80
#define D0F0xE4_PHY_4002_Reserved_13_8_OFFSET                   8
#define D0F0xE4_PHY_4002_Reserved_13_8_WIDTH                    6
#define D0F0xE4_PHY_4002_Reserved_13_8_MASK                     0x3f00
#define D0F0xE4_PHY_4002_LfcMin_OFFSET                          14
#define D0F0xE4_PHY_4002_LfcMin_WIDTH                           8
#define D0F0xE4_PHY_4002_LfcMin_MASK                            0x3fc000
#define D0F0xE4_PHY_4002_LfcMax_OFFSET                          22
#define D0F0xE4_PHY_4002_LfcMax_WIDTH                           8
#define D0F0xE4_PHY_4002_LfcMax_MASK                            0x3fc00000
#define D0F0xE4_PHY_4002_Reserved_31_30_OFFSET                  30
#define D0F0xE4_PHY_4002_Reserved_31_30_WIDTH                   2
#define D0F0xE4_PHY_4002_Reserved_31_30_MASK                    0xc0000000

/// D0F0xE4_PHY_4002
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_2_0:3 ; ///<
    UINT32                                       SamClkPiOffsetSign:1 ; ///<
    UINT32                                           SamClkPiOffset:3 ; ///<
    UINT32                                         SamClkPiOffsetEn:1 ; ///<
    UINT32                                            Reserved_13_8:6 ; ///<
    UINT32                                                   LfcMin:8 ; ///<
    UINT32                                                   LfcMax:8 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PHY_4002_STRUCT;

// **** D0F0xE4_PHY_4005 Register Definition ****
// Address
#define D0F0xE4_PHY_4005_ADDRESS                                0x4005

// Type
#define D0F0xE4_PHY_4005_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PHY_4005_Reserved_8_0_OFFSET                    0
#define D0F0xE4_PHY_4005_Reserved_8_0_WIDTH                     9
#define D0F0xE4_PHY_4005_Reserved_8_0_MASK                      0x1ff
#define D0F0xE4_PHY_4005_JitterInjHold_OFFSET                   9
#define D0F0xE4_PHY_4005_JitterInjHold_WIDTH                    1
#define D0F0xE4_PHY_4005_JitterInjHold_MASK                     0x200
#define D0F0xE4_PHY_4005_JitterInjOffCnt_OFFSET                 10
#define D0F0xE4_PHY_4005_JitterInjOffCnt_WIDTH                  6
#define D0F0xE4_PHY_4005_JitterInjOffCnt_MASK                   0xfc00
#define D0F0xE4_PHY_4005_Reserved_22_16_OFFSET                  16
#define D0F0xE4_PHY_4005_Reserved_22_16_WIDTH                   7
#define D0F0xE4_PHY_4005_Reserved_22_16_MASK                    0x7f0000
#define D0F0xE4_PHY_4005_JitterInjOnCnt_OFFSET                  23
#define D0F0xE4_PHY_4005_JitterInjOnCnt_WIDTH                   6
#define D0F0xE4_PHY_4005_JitterInjOnCnt_MASK                    0x1f800000
#define D0F0xE4_PHY_4005_JitterInjDir_OFFSET                    29
#define D0F0xE4_PHY_4005_JitterInjDir_WIDTH                     1
#define D0F0xE4_PHY_4005_JitterInjDir_MASK                      0x20000000
#define D0F0xE4_PHY_4005_JitterInjEn_OFFSET                     30
#define D0F0xE4_PHY_4005_JitterInjEn_WIDTH                      1
#define D0F0xE4_PHY_4005_JitterInjEn_MASK                       0x40000000
#define D0F0xE4_PHY_4005_Reserved_31_31_OFFSET                  31
#define D0F0xE4_PHY_4005_Reserved_31_31_WIDTH                   1
#define D0F0xE4_PHY_4005_Reserved_31_31_MASK                    0x80000000

/// D0F0xE4_PHY_4005
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_8_0:9 ; ///<
    UINT32                                            JitterInjHold:1 ; ///<
    UINT32                                          JitterInjOffCnt:6 ; ///<
    UINT32                                           Reserved_22_16:7 ; ///<
    UINT32                                           JitterInjOnCnt:6 ; ///<
    UINT32                                             JitterInjDir:1 ; ///<
    UINT32                                              JitterInjEn:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PHY_4005_STRUCT;

// **** D0F0xE4_PHY_4006 Register Definition ****
// Address
#define D0F0xE4_PHY_4006_ADDRESS                                0x4006

// Type
#define D0F0xE4_PHY_4006_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PHY_4006_Reserved_4_0_OFFSET                    0
#define D0F0xE4_PHY_4006_Reserved_4_0_WIDTH                     5
#define D0F0xE4_PHY_4006_Reserved_4_0_MASK                      0x1f
#define D0F0xE4_PHY_4006_DfeVoltage_OFFSET                      5
#define D0F0xE4_PHY_4006_DfeVoltage_WIDTH                       2
#define D0F0xE4_PHY_4006_DfeVoltage_MASK                        0x60
#define D0F0xE4_PHY_4006_DfeEn_OFFSET                           7
#define D0F0xE4_PHY_4006_DfeEn_WIDTH                            1
#define D0F0xE4_PHY_4006_DfeEn_MASK                             0x80
#define D0F0xE4_PHY_4006_Reserved_31_8_OFFSET                   8
#define D0F0xE4_PHY_4006_Reserved_31_8_WIDTH                    24
#define D0F0xE4_PHY_4006_Reserved_31_8_MASK                     0xffffff00

/// D0F0xE4_PHY_4006
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_4_0:5 ; ///<
    UINT32                                               DfeVoltage:2 ; ///<
    UINT32                                                    DfeEn:1 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PHY_4006_STRUCT;

// **** D0F0xE4_PHY_400A Register Definition ****
// Address
#define D0F0xE4_PHY_400A_ADDRESS                                0x400a

// Type
#define D0F0xE4_PHY_400A_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PHY_400A_EnCoreLoopFirst_OFFSET                 0
#define D0F0xE4_PHY_400A_EnCoreLoopFirst_WIDTH                  1
#define D0F0xE4_PHY_400A_EnCoreLoopFirst_MASK                   0x1
#define D0F0xE4_PHY_400A_Reserved_3_1_OFFSET                    1
#define D0F0xE4_PHY_400A_Reserved_3_1_WIDTH                     3
#define D0F0xE4_PHY_400A_Reserved_3_1_MASK                      0xe
#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_OFFSET                4
#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_WIDTH                 1
#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_MASK                  0x10
#define D0F0xE4_PHY_400A_Reserved_6_5_OFFSET                    5
#define D0F0xE4_PHY_400A_Reserved_6_5_WIDTH                     2
#define D0F0xE4_PHY_400A_Reserved_6_5_MASK                      0x60
#define D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET                    7
#define D0F0xE4_PHY_400A_BiasDisInLs2_WIDTH                     1
#define D0F0xE4_PHY_400A_BiasDisInLs2_MASK                      0x80
#define D0F0xE4_PHY_400A_Reserved_12_8_OFFSET                   8
#define D0F0xE4_PHY_400A_Reserved_12_8_WIDTH                    5
#define D0F0xE4_PHY_400A_Reserved_12_8_MASK                     0x1f00
#define D0F0xE4_PHY_400A_AnalogWaitTime_OFFSET                  13
#define D0F0xE4_PHY_400A_AnalogWaitTime_WIDTH                   2
#define D0F0xE4_PHY_400A_AnalogWaitTime_MASK                    0x6000
#define D0F0xE4_PHY_400A_Reserved_16_15_OFFSET                  15
#define D0F0xE4_PHY_400A_Reserved_16_15_WIDTH                   2
#define D0F0xE4_PHY_400A_Reserved_16_15_MASK                    0x18000
#define D0F0xE4_PHY_400A_DllLockFastModeEn_OFFSET               17
#define D0F0xE4_PHY_400A_DllLockFastModeEn_WIDTH                1
#define D0F0xE4_PHY_400A_DllLockFastModeEn_MASK                 0x20000
#define D0F0xE4_PHY_400A_Reserved_28_18_OFFSET                  18
#define D0F0xE4_PHY_400A_Reserved_28_18_WIDTH                   11
#define D0F0xE4_PHY_400A_Reserved_28_18_MASK                    0x1ffc0000
#define D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET                     29
#define D0F0xE4_PHY_400A_Ls2ExitTime_WIDTH                      3
#define D0F0xE4_PHY_400A_Ls2ExitTime_MASK                       0xe0000000

/// D0F0xE4_PHY_400A
typedef union {
  struct {                                                              ///<
    UINT32                                          EnCoreLoopFirst:1 ; ///<
    UINT32                                             Reserved_3_1:3 ; ///<
    UINT32                                         LockDetOnLs2Exit:1 ; ///<
    UINT32                                             Reserved_6_5:2 ; ///<
    UINT32                                             BiasDisInLs2:1 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           AnalogWaitTime:2 ; ///<
    UINT32                                           Reserved_16_15:2 ; ///<
    UINT32                                        DllLockFastModeEn:1 ; ///<
    UINT32                                           Reserved_28_18:11; ///<
    UINT32                                              Ls2ExitTime:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PHY_400A_STRUCT;

// **** D0F0xE4_PHY_4010 Register Definition ****
// Address
#define D0F0xE4_PHY_4010_ADDRESS                               0x4010

// Type
#define D0F0xE4_PHY_4010_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PHY_4010_PhyFuseValid_OFFSET                   0
#define D0F0xE4_PHY_4010_PhyFuseValid_WIDTH                    1
#define D0F0xE4_PHY_4010_PhyFuseValid_MASK                     0x1
#define D0F0xE4_PHY_4010_FuseFuncDllRCFilterOverride_OFFSET    1
#define D0F0xE4_PHY_4010_FuseFuncDllRCFilterOverride_WIDTH     1
#define D0F0xE4_PHY_4010_FuseFuncDllRCFilterOverride_MASK      0x2
#define D0F0xE4_PHY_4010_Reserved_2_2_OFFSET                   2
#define D0F0xE4_PHY_4010_Reserved_2_2_WIDTH                    1
#define D0F0xE4_PHY_4010_Reserved_2_2_MASK                     0x4
#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStepSize_OFFSET    3
#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStepSize_WIDTH     1
#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStepSize_MASK      0x8
#define D0F0xE4_PHY_4010_Reserved_4_4_OFFSET                   4
#define D0F0xE4_PHY_4010_Reserved_4_4_WIDTH                    1
#define D0F0xE4_PHY_4010_Reserved_4_4_MASK                     0x10
#define D0F0xE4_PHY_4010_FuseFuncDllMidLockStepSize_OFFSET     5
#define D0F0xE4_PHY_4010_FuseFuncDllMidLockStepSize_WIDTH      1
#define D0F0xE4_PHY_4010_FuseFuncDllMidLockStepSize_MASK       0x20
#define D0F0xE4_PHY_4010_Reserved_6_6_OFFSET                   6
#define D0F0xE4_PHY_4010_Reserved_6_6_WIDTH                    1
#define D0F0xE4_PHY_4010_Reserved_6_6_MASK                     0x40
#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStop_OFFSET        7
#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStop_WIDTH         4
#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStop_MASK          0x780
#define D0F0xE4_PHY_4010_Reserved_12_11_OFFSET                 11
#define D0F0xE4_PHY_4010_Reserved_12_11_WIDTH                  2
#define D0F0xE4_PHY_4010_Reserved_12_11_MASK                   0x1800
#define D0F0xE4_PHY_4010_FuseFuncDllInputDccDis_OFFSET         13
#define D0F0xE4_PHY_4010_FuseFuncDllInputDccDis_WIDTH          1
#define D0F0xE4_PHY_4010_FuseFuncDllInputDccDis_MASK           0x2000
#define D0F0xE4_PHY_4010_Reserved_14_14_OFFSET                 14
#define D0F0xE4_PHY_4010_Reserved_14_14_WIDTH                  1
#define D0F0xE4_PHY_4010_Reserved_14_14_MASK                   0x4000
#define D0F0xE4_PHY_4010_FuseFuncDllProcessCompCtl_OFFSET      15
#define D0F0xE4_PHY_4010_FuseFuncDllProcessCompCtl_WIDTH       2
#define D0F0xE4_PHY_4010_FuseFuncDllProcessCompCtl_MASK        0x18000
#define D0F0xE4_PHY_4010_Reserved_19_17_OFFSET                 17
#define D0F0xE4_PHY_4010_Reserved_19_17_WIDTH                  3
#define D0F0xE4_PHY_4010_Reserved_19_17_MASK                   0xe0000
#define D0F0xE4_PHY_4010_FuseFuncDllRdacSupSel_OFFSET          20
#define D0F0xE4_PHY_4010_FuseFuncDllRdacSupSel_WIDTH           1
#define D0F0xE4_PHY_4010_FuseFuncDllRdacSupSel_MASK            0x100000
#define D0F0xE4_PHY_4010_FuseFuncRxSpare_OFFSET                21
#define D0F0xE4_PHY_4010_FuseFuncRxSpare_WIDTH                 1
#define D0F0xE4_PHY_4010_FuseFuncRxSpare_MASK                  0x200000
#define D0F0xE4_PHY_4010_Reserved_31_22_OFFSET                 22
#define D0F0xE4_PHY_4010_Reserved_31_22_WIDTH                  10
#define D0F0xE4_PHY_4010_Reserved_31_22_MASK                   0xffc00000

/// D0F0xE4_PHY_4010
typedef union {
  struct {                                                              ///<
    UINT32                                             PhyFuseValid:1 ; ///<
    UINT32                              FuseFuncDllRCFilterOverride:1 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                              FuseFuncDllFastLockStepSize:1 ; ///<
    UINT32                                             Reserved_4_4:1 ; ///<
    UINT32                               FuseFuncDllMidLockStepSize:1 ; ///<
    UINT32                                             Reserved_6_6:1 ; ///<
    UINT32                                  FuseFuncDllFastLockStop:4 ; ///<
    UINT32                                           Reserved_12_11:2 ; ///<
    UINT32                                   FuseFuncDllInputDccDis:1 ; ///<
    UINT32                                           Reserved_14_14:1 ; ///<
    UINT32                                FuseFuncDllProcessCompCtl:2 ; ///<
    UINT32                                           Reserved_19_17:3 ; ///<
    UINT32                                    FuseFuncDllRdacSupSel:1 ; ///<
    UINT32                                          FuseFuncRxSpare:1 ; ///<
    UINT32                                           Reserved_31_22:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PHY_4010_STRUCT;

// **** D0F0xE4_PHY_4011 Register Definition ****
// Address
#define D0F0xE4_PHY_4011_ADDRESS                               0x4011

// Type
#define D0F0xE4_PHY_4011_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PHY_4011_PhyFuseValid_OFFSET                   0
#define D0F0xE4_PHY_4011_PhyFuseValid_WIDTH                    1
#define D0F0xE4_PHY_4011_PhyFuseValid_MASK                     0x1
#define D0F0xE4_PHY_4011_FuseProcDllVrefAdj_OFFSET             1
#define D0F0xE4_PHY_4011_FuseProcDllVrefAdj_WIDTH              3
#define D0F0xE4_PHY_4011_FuseProcDllVrefAdj_MASK               0xe
#define D0F0xE4_PHY_4011_Reserved_5_4_OFFSET                   4
#define D0F0xE4_PHY_4011_Reserved_5_4_WIDTH                    2
#define D0F0xE4_PHY_4011_Reserved_5_4_MASK                     0x30
#define D0F0xE4_PHY_4011_FuseProcDllIrefAdj_OFFSET             6
#define D0F0xE4_PHY_4011_FuseProcDllIrefAdj_WIDTH              3
#define D0F0xE4_PHY_4011_FuseProcDllIrefAdj_MASK               0x1c0
#define D0F0xE4_PHY_4011_Reserved_10_9_OFFSET                  9
#define D0F0xE4_PHY_4011_Reserved_10_9_WIDTH                   2
#define D0F0xE4_PHY_4011_Reserved_10_9_MASK                    0x600
#define D0F0xE4_PHY_4011_FuseProcDllProcessComp_OFFSET         11
#define D0F0xE4_PHY_4011_FuseProcDllProcessComp_WIDTH          3
#define D0F0xE4_PHY_4011_FuseProcDllProcessComp_MASK           0x3800
#define D0F0xE4_PHY_4011_Reserved_15_14_OFFSET                 14
#define D0F0xE4_PHY_4011_Reserved_15_14_WIDTH                  2
#define D0F0xE4_PHY_4011_Reserved_15_14_MASK                   0xc000
#define D0F0xE4_PHY_4011_FuseProcDllRCFilterCtl_OFFSET         16
#define D0F0xE4_PHY_4011_FuseProcDllRCFilterCtl_WIDTH          1
#define D0F0xE4_PHY_4011_FuseProcDllRCFilterCtl_MASK           0x10000
#define D0F0xE4_PHY_4011_Reserved_18_17_OFFSET                 17
#define D0F0xE4_PHY_4011_Reserved_18_17_WIDTH                  2
#define D0F0xE4_PHY_4011_Reserved_18_17_MASK                   0x60000
#define D0F0xE4_PHY_4011_FuseProcEiDetThresh_OFFSET            19
#define D0F0xE4_PHY_4011_FuseProcEiDetThresh_WIDTH             2
#define D0F0xE4_PHY_4011_FuseProcEiDetThresh_MASK              0x180000
#define D0F0xE4_PHY_4011_Reserved_22_21_OFFSET                 21
#define D0F0xE4_PHY_4011_Reserved_22_21_WIDTH                  2
#define D0F0xE4_PHY_4011_Reserved_22_21_MASK                   0x600000
#define D0F0xE4_PHY_4011_FuseProcRxSpare_OFFSET                23
#define D0F0xE4_PHY_4011_FuseProcRxSpare_WIDTH                 1
#define D0F0xE4_PHY_4011_FuseProcRxSpare_MASK                  0x800000
#define D0F0xE4_PHY_4011_Reserved_31_24_OFFSET                 24
#define D0F0xE4_PHY_4011_Reserved_31_24_WIDTH                  8
#define D0F0xE4_PHY_4011_Reserved_31_24_MASK                   0xff000000

/// D0F0xE4_PHY_4011
typedef union {
  struct {                                                              ///<
    UINT32                                             PhyFuseValid:1 ; ///<
    UINT32                                       FuseProcDllVrefAdj:3 ; ///<
    UINT32                                             Reserved_5_4:2 ; ///<
    UINT32                                       FuseProcDllIrefAdj:3 ; ///<
    UINT32                                            Reserved_10_9:2 ; ///<
    UINT32                                   FuseProcDllProcessComp:3 ; ///<
    UINT32                                           Reserved_15_14:1 ; ///<
    UINT32                                   FuseProcDllRCFilterCtl:1 ; ///<
    UINT32                                           Reserved_18_17:2 ; ///<
    UINT32                                      FuseProcEiDetThresh:2 ; ///<
    UINT32                                           Reserved_22_21:2 ; ///<
    UINT32                                          FuseProcRxSpare:1 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PHY_4011_STRUCT;

// **** D0F0xE4_PHY_500F Register Definition ****
// Address
#define D0F0xE4_PHY_500F_ADDRESS                               0x500F

// Type
#define D0F0xE4_PHY_500F_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex1_OFFSET        0
#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex1_WIDTH         4
#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex1_MASK          0xf
#define D0F0xE4_PHY_500F_Reserved_6_4_OFFSET                   4
#define D0F0xE4_PHY_500F_Reserved_6_4_WIDTH                    3
#define D0F0xE4_PHY_500F_Reserved_6_4_MASK                     0x70
#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex2_OFFSET        7
#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex2_WIDTH         4
#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex2_MASK          0x780
#define D0F0xE4_PHY_500F_Reserved_11_11_OFFSET                 11
#define D0F0xE4_PHY_500F_Reserved_11_11_WIDTH                  1
#define D0F0xE4_PHY_500F_Reserved_11_11_MASK                   0x800
#define D0F0xE4_PHY_500F_DllProcessFreqCtlOverride_OFFSET      12
#define D0F0xE4_PHY_500F_DllProcessFreqCtlOverride_WIDTH       1
#define D0F0xE4_PHY_500F_DllProcessFreqCtlOverride_MASK        0x1000
#define D0F0xE4_PHY_500F_Reserved_13_13_OFFSET                 13
#define D0F0xE4_PHY_500F_Reserved_13_13_WIDTH                  1
#define D0F0xE4_PHY_500F_Reserved_13_13_MASK                   0x2000

/// D0F0xE4_PHY_500F
typedef union {
  struct {                                                              ///<
    UINT32                                  DllProcessFreqCtlIndex1:4 ; ///<
    UINT32                                             Reserved_6_4:3 ; ///<
    UINT32                                  DllProcessFreqCtlIndex2:4 ; ///<
    UINT32                                           Reserved_11_11:1 ; ///<
    UINT32                                DllProcessFreqCtlOverride:1 ; ///<
    UINT32                                           Reserved_13_13:1 ; ///<
    UINT32  :4 ; ///<
    UINT32  :2 ; ///<
    UINT32  :1 ; ///<
    UINT32  :2 ; ///<
    UINT32  :1 ; ///<
    UINT32  :1 ; ///<
    UINT32  :1 ; ///<
    UINT32  :1 ; ///<
    UINT32  :1 ; ///<
    UINT32  :2 ; ///<
    UINT32  :1 ; ///<
    UINT32  :1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PHY_500F_STRUCT;

// **** D0F0xE4_PHY_6005 Register Definition ****
// Address
#define D0F0xE4_PHY_6005_ADDRESS                                0x6005

// Type
#define D0F0xE4_PHY_6005_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PHY_6005_Reserved_28_0_OFFSET                   0
#define D0F0xE4_PHY_6005_Reserved_28_0_WIDTH                    29
#define D0F0xE4_PHY_6005_Reserved_28_0_MASK                     0x1fffffff
#define D0F0xE4_PHY_6005_IsOwnMstr_OFFSET                       29
#define D0F0xE4_PHY_6005_IsOwnMstr_WIDTH                        1
#define D0F0xE4_PHY_6005_IsOwnMstr_MASK                         0x20000000
#define D0F0xE4_PHY_6005_Reserved_30_30_OFFSET                  30
#define D0F0xE4_PHY_6005_Reserved_30_30_WIDTH                   1
#define D0F0xE4_PHY_6005_Reserved_30_30_MASK                    0x40000000
#define D0F0xE4_PHY_6005_GangedModeEn_OFFSET                    31
#define D0F0xE4_PHY_6005_GangedModeEn_WIDTH                     1
#define D0F0xE4_PHY_6005_GangedModeEn_MASK                      0x80000000

/// D0F0xE4_PHY_6005
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_28_0:29; ///<
    UINT32                                                IsOwnMstr:1 ; ///<
    UINT32                                           Reserved_30_30:1 ; ///<
    UINT32                                             GangedModeEn:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PHY_6005_STRUCT;

// **** D0F0xE4_PHY_6006 Register Definition ****
// Address
#define D0F0xE4_PHY_6006_ADDRESS                                0x6006

// Type
#define D0F0xE4_PHY_6006_TYPE                                   TYPE_D0F0xE4
// Field Data
#define D0F0xE4_PHY_6006_TxMarginNom_OFFSET                     0
#define D0F0xE4_PHY_6006_TxMarginNom_WIDTH                      8
#define D0F0xE4_PHY_6006_TxMarginNom_MASK                       0xff
#define D0F0xE4_PHY_6006_DeemphGen1Nom_OFFSET                   8
#define D0F0xE4_PHY_6006_DeemphGen1Nom_WIDTH                    8
#define D0F0xE4_PHY_6006_DeemphGen1Nom_MASK                     0xff00
#define D0F0xE4_PHY_6006_Reserved_31_16_OFFSET                  16
#define D0F0xE4_PHY_6006_Reserved_31_16_WIDTH                   16
#define D0F0xE4_PHY_6006_Reserved_31_16_MASK                    0xffff0000

/// D0F0xE4_PHY_6006
typedef union {
  struct {                                                              ///<
    UINT32                                              TxMarginNom:8 ; ///<
    UINT32                                            DeemphGen1Nom:8 ; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_PHY_6006_STRUCT;

// **** D0F2xF4_x00 Register Definition ****
// Address
#define D0F2xF4_x00_ADDRESS                                     0x0

// Type
#define D0F2xF4_x00_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x00_L2PerfEvent0_OFFSET                         0
#define D0F2xF4_x00_L2PerfEvent0_WIDTH                          8
#define D0F2xF4_x00_L2PerfEvent0_MASK                           0xff
#define D0F2xF4_x00_L2PerfEvent1_OFFSET                         8
#define D0F2xF4_x00_L2PerfEvent1_WIDTH                          8
#define D0F2xF4_x00_L2PerfEvent1_MASK                           0xff00
#define D0F2xF4_x00_L2PerfCountUpper0_OFFSET                    16
#define D0F2xF4_x00_L2PerfCountUpper0_WIDTH                     8
#define D0F2xF4_x00_L2PerfCountUpper0_MASK                      0xff0000
#define D0F2xF4_x00_L2PerfCountUpper1_OFFSET                    24
#define D0F2xF4_x00_L2PerfCountUpper1_WIDTH                     8
#define D0F2xF4_x00_L2PerfCountUpper1_MASK                      0xff000000

/// D0F2xF4_x00
typedef union {
  struct {                                                              ///<
    UINT32                                             L2PerfEvent0:8 ; ///<
    UINT32                                             L2PerfEvent1:8 ; ///<
    UINT32                                        L2PerfCountUpper0:8 ; ///<
    UINT32                                        L2PerfCountUpper1:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x00_STRUCT;

// **** D0F2xF4_x01 Register Definition ****
// Address
#define D0F2xF4_x01_ADDRESS                                     0x1

// Type
#define D0F2xF4_x01_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x01_L2PerfCount0_OFFSET                         0
#define D0F2xF4_x01_L2PerfCount0_WIDTH                          32
#define D0F2xF4_x01_L2PerfCount0_MASK                           0xffffffff

/// D0F2xF4_x01
typedef union {
  struct {                                                              ///<
    UINT32                                             L2PerfCount0:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x01_STRUCT;

// **** D0F2xF4_x02 Register Definition ****
// Address
#define D0F2xF4_x02_ADDRESS                                     0x2

// Type
#define D0F2xF4_x02_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x02_L2PerfCount1_OFFSET                         0
#define D0F2xF4_x02_L2PerfCount1_WIDTH                          32
#define D0F2xF4_x02_L2PerfCount1_MASK                           0xffffffff

/// D0F2xF4_x02
typedef union {
  struct {                                                              ///<
    UINT32                                             L2PerfCount1:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x02_STRUCT;

// **** D0F2xF4_x03 Register Definition ****
// Address
#define D0F2xF4_x03_ADDRESS                                     0x3

// Type
#define D0F2xF4_x03_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x03_L2PerfEvent2_OFFSET                         0
#define D0F2xF4_x03_L2PerfEvent2_WIDTH                          8
#define D0F2xF4_x03_L2PerfEvent2_MASK                           0xff
#define D0F2xF4_x03_L2PerfEvent3_OFFSET                         8
#define D0F2xF4_x03_L2PerfEvent3_WIDTH                          8
#define D0F2xF4_x03_L2PerfEvent3_MASK                           0xff00
#define D0F2xF4_x03_L2PerfCountUpper2_OFFSET                    16
#define D0F2xF4_x03_L2PerfCountUpper2_WIDTH                     8
#define D0F2xF4_x03_L2PerfCountUpper2_MASK                      0xff0000
#define D0F2xF4_x03_L2PerfCountUpper3_OFFSET                    24
#define D0F2xF4_x03_L2PerfCountUpper3_WIDTH                     8
#define D0F2xF4_x03_L2PerfCountUpper3_MASK                      0xff000000

/// D0F2xF4_x03
typedef union {
  struct {                                                              ///<
    UINT32                                             L2PerfEvent2:8 ; ///<
    UINT32                                             L2PerfEvent3:8 ; ///<
    UINT32                                        L2PerfCountUpper2:8 ; ///<
    UINT32                                        L2PerfCountUpper3:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x03_STRUCT;

// **** D0F2xF4_x04 Register Definition ****
// Address
#define D0F2xF4_x04_ADDRESS                                     0x4

// Type
#define D0F2xF4_x04_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x04_L2PerfCount2_OFFSET                         0
#define D0F2xF4_x04_L2PerfCount2_WIDTH                          32
#define D0F2xF4_x04_L2PerfCount2_MASK                           0xffffffff

/// D0F2xF4_x04
typedef union {
  struct {                                                              ///<
    UINT32                                             L2PerfCount2:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x04_STRUCT;

// **** D0F2xF4_x05 Register Definition ****
// Address
#define D0F2xF4_x05_ADDRESS                                     0x5

// Type
#define D0F2xF4_x05_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x05_L2PerfCount3_OFFSET                         0
#define D0F2xF4_x05_L2PerfCount3_WIDTH                          32
#define D0F2xF4_x05_L2PerfCount3_MASK                           0xffffffff

/// D0F2xF4_x05
typedef union {
  struct {                                                              ///<
    UINT32                                             L2PerfCount3:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x05_STRUCT;

// **** D0F2xF4_x06 Register Definition ****
// Address
#define D0F2xF4_x06_ADDRESS                                     0x6

// Type
#define D0F2xF4_x06_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x06_L2DEBUG0_OFFSET                             0
#define D0F2xF4_x06_L2DEBUG0_WIDTH                              32
#define D0F2xF4_x06_L2DEBUG0_MASK                               0xffffffff

/// D0F2xF4_x06
typedef union {
  struct {                                                              ///<
    UINT32                                                 L2DEBUG0:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x06_STRUCT;

// **** D0F2xF4_x07 Register Definition ****
// Address
#define D0F2xF4_x07_ADDRESS                                     0x7

// Type
#define D0F2xF4_x07_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x07_L2DEBUG1_OFFSET                             0
#define D0F2xF4_x07_L2DEBUG1_WIDTH                              32
#define D0F2xF4_x07_L2DEBUG1_MASK                               0xffffffff

/// D0F2xF4_x07
typedef union {
  struct {                                                              ///<
    UINT32                                                 L2DEBUG1:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x07_STRUCT;

// **** D0F2xF4_x08 Register Definition ****
// Address
#define D0F2xF4_x08_ADDRESS                                     0x8

// Type
#define D0F2xF4_x08_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x08_L2STATUS0_OFFSET                            0
#define D0F2xF4_x08_L2STATUS0_WIDTH                             32
#define D0F2xF4_x08_L2STATUS0_MASK                              0xffffffff

/// D0F2xF4_x08
typedef union {
  struct {                                                              ///<
    UINT32                                                L2STATUS0:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x08_STRUCT;

// **** D0F2xF4_x0C Register Definition ****
// Address
#define D0F2xF4_x0C_ADDRESS                                     0xc

// Type
#define D0F2xF4_x0C_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x0C_PTCAddrTransReqCheck_OFFSET                 0
#define D0F2xF4_x0C_PTCAddrTransReqCheck_WIDTH                  1
#define D0F2xF4_x0C_PTCAddrTransReqCheck_MASK                   0x1
#define D0F2xF4_x0C_AllowL1CacheVZero_OFFSET                    1
#define D0F2xF4_x0C_AllowL1CacheVZero_WIDTH                     1
#define D0F2xF4_x0C_AllowL1CacheVZero_MASK                      0x2
#define D0F2xF4_x0C_AllowL1CacheATSRsp_OFFSET                   2
#define D0F2xF4_x0C_AllowL1CacheATSRsp_WIDTH                    1
#define D0F2xF4_x0C_AllowL1CacheATSRsp_MASK                     0x4
#define D0F2xF4_x0C_DTCHitVZeroOrIVZero_OFFSET                  3
#define D0F2xF4_x0C_DTCHitVZeroOrIVZero_WIDTH                   1
#define D0F2xF4_x0C_DTCHitVZeroOrIVZero_MASK                    0x8
#define D0F2xF4_x0C_IFifoTWCredits_OFFSET                       4
#define D0F2xF4_x0C_IFifoTWCredits_WIDTH                        6
#define D0F2xF4_x0C_IFifoTWCredits_MASK                         0x3f0
#define D0F2xF4_x0C_SIDEPTEOnUntransExcl_OFFSET                 10
#define D0F2xF4_x0C_SIDEPTEOnUntransExcl_WIDTH                  1
#define D0F2xF4_x0C_SIDEPTEOnUntransExcl_MASK                   0x400
#define D0F2xF4_x0C_SIDEPTEOnAddrTransExcl_OFFSET               11
#define D0F2xF4_x0C_SIDEPTEOnAddrTransExcl_WIDTH                1
#define D0F2xF4_x0C_SIDEPTEOnAddrTransExcl_MASK                 0x800
#define D0F2xF4_x0C_IFifoCMBCredits_OFFSET                      12
#define D0F2xF4_x0C_IFifoCMBCredits_WIDTH                       6
#define D0F2xF4_x0C_IFifoCMBCredits_MASK                        0x3f000
#define D0F2xF4_x0C_FLTCMBPriority_OFFSET                       18
#define D0F2xF4_x0C_FLTCMBPriority_WIDTH                        1
#define D0F2xF4_x0C_FLTCMBPriority_MASK                         0x40000
#define D0F2xF4_x0C_Reserved_19_19_OFFSET                       19
#define D0F2xF4_x0C_Reserved_19_19_WIDTH                        1
#define D0F2xF4_x0C_Reserved_19_19_MASK                         0x80000
#define D0F2xF4_x0C_IFifoBurstLength_OFFSET                     20
#define D0F2xF4_x0C_IFifoBurstLength_WIDTH                      4
#define D0F2xF4_x0C_IFifoBurstLength_MASK                       0xf00000
#define D0F2xF4_x0C_IFifoClientPriority_OFFSET                  24
#define D0F2xF4_x0C_IFifoClientPriority_WIDTH                   8
#define D0F2xF4_x0C_IFifoClientPriority_MASK                    0xff000000

/// D0F2xF4_x0C
typedef union {
  struct {                                                              ///<
    UINT32                                     PTCAddrTransReqCheck:1 ; ///<
    UINT32                                        AllowL1CacheVZero:1 ; ///<
    UINT32                                       AllowL1CacheATSRsp:1 ; ///<
    UINT32                                      DTCHitVZeroOrIVZero:1 ; ///<
    UINT32                                           IFifoTWCredits:6 ; ///<
    UINT32                                     SIDEPTEOnUntransExcl:1 ; ///<
    UINT32                                   SIDEPTEOnAddrTransExcl:1 ; ///<
    UINT32                                          IFifoCMBCredits:6 ; ///<
    UINT32                                           FLTCMBPriority:1 ; ///<
    UINT32                                           Reserved_19_19:1 ; ///<
    UINT32                                         IFifoBurstLength:4 ; ///<
    UINT32                                      IFifoClientPriority:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x0C_STRUCT;

// **** D0F2xF4_x0D Register Definition ****
// Address
#define D0F2xF4_x0D_ADDRESS                                     0xd

// Type
#define D0F2xF4_x0D_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x0D_SeqInvBurstLimitInv_OFFSET                  0
#define D0F2xF4_x0D_SeqInvBurstLimitInv_WIDTH                   8
#define D0F2xF4_x0D_SeqInvBurstLimitInv_MASK                    0xff
#define D0F2xF4_x0D_SeqInvBurstLimitL2Req_OFFSET                8
#define D0F2xF4_x0D_SeqInvBurstLimitL2Req_WIDTH                 8
#define D0F2xF4_x0D_SeqInvBurstLimitL2Req_MASK                  0xff00
#define D0F2xF4_x0D_SeqInvBurstLimitEn_OFFSET                   16
#define D0F2xF4_x0D_SeqInvBurstLimitEn_WIDTH                    1
#define D0F2xF4_x0D_SeqInvBurstLimitEn_MASK                     0x10000
#define D0F2xF4_x0D_Reserved_23_17_OFFSET                       17
#define D0F2xF4_x0D_Reserved_23_17_WIDTH                        7
#define D0F2xF4_x0D_Reserved_23_17_MASK                         0xfe0000
#define D0F2xF4_x0D_PerfThreshold_OFFSET                        24
#define D0F2xF4_x0D_PerfThreshold_WIDTH                         8
#define D0F2xF4_x0D_PerfThreshold_MASK                          0xff000000

/// D0F2xF4_x0D
typedef union {
  struct {                                                              ///<
    UINT32                                      SeqInvBurstLimitInv:8 ; ///<
    UINT32                                    SeqInvBurstLimitL2Req:8 ; ///<
    UINT32                                       SeqInvBurstLimitEn:1 ; ///<
    UINT32                                           Reserved_23_17:7 ; ///<
    UINT32                                            PerfThreshold:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x0D_STRUCT;

// **** D0F2xF4_x10 Register Definition ****
// Address
#define D0F2xF4_x10_ADDRESS                                     0x10

// Type
#define D0F2xF4_x10_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x10_DTCReplacementSel_OFFSET                    0
#define D0F2xF4_x10_DTCReplacementSel_WIDTH                     2
#define D0F2xF4_x10_DTCReplacementSel_MASK                      0x3
#define D0F2xF4_x10_Reserved_2_2_OFFSET                         2
#define D0F2xF4_x10_Reserved_2_2_WIDTH                          1
#define D0F2xF4_x10_Reserved_2_2_MASK                           0x4
#define D0F2xF4_x10_DTCLRUUpdatePri_OFFSET                      3
#define D0F2xF4_x10_DTCLRUUpdatePri_WIDTH                       1
#define D0F2xF4_x10_DTCLRUUpdatePri_MASK                        0x8
#define D0F2xF4_x10_DTCParityEn_OFFSET                          4
#define D0F2xF4_x10_DTCParityEn_WIDTH                           1
#define D0F2xF4_x10_DTCParityEn_MASK                            0x10
#define D0F2xF4_x10_Reserved_7_5_OFFSET                         5
#define D0F2xF4_x10_Reserved_7_5_WIDTH                          3
#define D0F2xF4_x10_Reserved_7_5_MASK                           0xe0
#define D0F2xF4_x10_DTCInvalidationSel_OFFSET                   8
#define D0F2xF4_x10_DTCInvalidationSel_WIDTH                    2
#define D0F2xF4_x10_DTCInvalidationSel_MASK                     0x300
#define D0F2xF4_x10_DTCSoftInvalidate_OFFSET                    10
#define D0F2xF4_x10_DTCSoftInvalidate_WIDTH                     1
#define D0F2xF4_x10_DTCSoftInvalidate_MASK                      0x400
#define D0F2xF4_x10_Reserved_12_11_OFFSET                       11
#define D0F2xF4_x10_Reserved_12_11_WIDTH                        2
#define D0F2xF4_x10_Reserved_12_11_MASK                         0x1800
#define D0F2xF4_x10_DTCBypass_OFFSET                            13
#define D0F2xF4_x10_DTCBypass_WIDTH                             1
#define D0F2xF4_x10_DTCBypass_MASK                              0x2000
#define D0F2xF4_x10_Reserved_14_14_OFFSET                       14
#define D0F2xF4_x10_Reserved_14_14_WIDTH                        1
#define D0F2xF4_x10_Reserved_14_14_MASK                         0x4000
#define D0F2xF4_x10_DTCParitySupport_OFFSET                     15
#define D0F2xF4_x10_DTCParitySupport_WIDTH                      1
#define D0F2xF4_x10_DTCParitySupport_MASK                       0x8000
#define D0F2xF4_x10_DTCWays_OFFSET                              16
#define D0F2xF4_x10_DTCWays_WIDTH                               8
#define D0F2xF4_x10_DTCWays_MASK                                0xff0000
#define D0F2xF4_x10_Reserved_27_24_OFFSET                       24
#define D0F2xF4_x10_Reserved_27_24_WIDTH                        4
#define D0F2xF4_x10_Reserved_27_24_MASK                         0xf000000
#define D0F2xF4_x10_DTCEntries_OFFSET                           28
#define D0F2xF4_x10_DTCEntries_WIDTH                            4
#define D0F2xF4_x10_DTCEntries_MASK                             0xf0000000

/// D0F2xF4_x10
typedef union {
  struct {                                                              ///<
    UINT32                                        DTCReplacementSel:2 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                          DTCLRUUpdatePri:1 ; ///<
    UINT32                                              DTCParityEn:1 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                       DTCInvalidationSel:2 ; ///<
    UINT32                                        DTCSoftInvalidate:1 ; ///<
    UINT32                                           Reserved_12_11:2 ; ///<
    UINT32                                                DTCBypass:1 ; ///<
    UINT32                                           Reserved_14_14:1 ; ///<
    UINT32                                         DTCParitySupport:1 ; ///<
    UINT32                                                  DTCWays:8 ; ///<
    UINT32                                           Reserved_27_24:4 ; ///<
    UINT32                                               DTCEntries:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x10_STRUCT;

// **** D0F2xF4_x11 Register Definition ****
// Address
#define D0F2xF4_x11_ADDRESS                                     0x11

// Type
#define D0F2xF4_x11_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x11_DTCFuncBits_OFFSET                          0
#define D0F2xF4_x11_DTCFuncBits_WIDTH                           2
#define D0F2xF4_x11_DTCFuncBits_MASK                            0x3
#define D0F2xF4_x11_DTCDevBits_OFFSET                           2
#define D0F2xF4_x11_DTCDevBits_WIDTH                            3
#define D0F2xF4_x11_DTCDevBits_MASK                             0x1c
#define D0F2xF4_x11_DTCBusBits_OFFSET                           5
#define D0F2xF4_x11_DTCBusBits_WIDTH                            4
#define D0F2xF4_x11_DTCBusBits_MASK                             0x1e0
#define D0F2xF4_x11_Reserved_9_9_OFFSET                         9
#define D0F2xF4_x11_Reserved_9_9_WIDTH                          1
#define D0F2xF4_x11_Reserved_9_9_MASK                           0x200
#define D0F2xF4_x11_DtcAltHashEn_OFFSET                         10
#define D0F2xF4_x11_DtcAltHashEn_WIDTH                          1
#define D0F2xF4_x11_DtcAltHashEn_MASK                           0x400
#define D0F2xF4_x11_Reserved_15_11_OFFSET                       11
#define D0F2xF4_x11_Reserved_15_11_WIDTH                        5
#define D0F2xF4_x11_Reserved_15_11_MASK                         0xf800
#define D0F2xF4_x11_DtcAddressMask_OFFSET                       16
#define D0F2xF4_x11_DtcAddressMask_WIDTH                        16
#define D0F2xF4_x11_DtcAddressMask_MASK                         0xffff0000

/// D0F2xF4_x11
typedef union {
  struct {                                                              ///<
    UINT32                                              DTCFuncBits:2 ; ///<
    UINT32                                               DTCDevBits:3 ; ///<
    UINT32                                               DTCBusBits:4 ; ///<
    UINT32                                             Reserved_9_9:1 ; ///<
    UINT32                                             DtcAltHashEn:1 ; ///<
    UINT32                                           Reserved_15_11:5 ; ///<
    UINT32                                           DtcAddressMask:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x11_STRUCT;

// **** D0F2xF4_x12 Register Definition ****
// Address
#define D0F2xF4_x12_ADDRESS                                     0x12

// Type
#define D0F2xF4_x12_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x12_DTCWayDisable_OFFSET                        0
#define D0F2xF4_x12_DTCWayDisable_WIDTH                         16
#define D0F2xF4_x12_DTCWayDisable_MASK                          0xffff
#define D0F2xF4_x12_DTCWayAccessDisable_OFFSET                  16
#define D0F2xF4_x12_DTCWayAccessDisable_WIDTH                   16
#define D0F2xF4_x12_DTCWayAccessDisable_MASK                    0xffff0000

/// D0F2xF4_x12
typedef union {
  struct {                                                              ///<
    UINT32                                            DTCWayDisable:16; ///<
    UINT32                                      DTCWayAccessDisable:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x12_STRUCT;

// **** D0F2xF4_x14 Register Definition ****
// Address
#define D0F2xF4_x14_ADDRESS                                     0x14

// Type
#define D0F2xF4_x14_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x14_ITCReplacementSel_OFFSET                    0
#define D0F2xF4_x14_ITCReplacementSel_WIDTH                     2
#define D0F2xF4_x14_ITCReplacementSel_MASK                      0x3
#define D0F2xF4_x14_Reserved_2_2_OFFSET                         2
#define D0F2xF4_x14_Reserved_2_2_WIDTH                          1
#define D0F2xF4_x14_Reserved_2_2_MASK                           0x4
#define D0F2xF4_x14_ITCLRUUpdatePri_OFFSET                      3
#define D0F2xF4_x14_ITCLRUUpdatePri_WIDTH                       1
#define D0F2xF4_x14_ITCLRUUpdatePri_MASK                        0x8
#define D0F2xF4_x14_ITCParityEn_OFFSET                          4
#define D0F2xF4_x14_ITCParityEn_WIDTH                           1
#define D0F2xF4_x14_ITCParityEn_MASK                            0x10
#define D0F2xF4_x14_Reserved_7_5_OFFSET                         5
#define D0F2xF4_x14_Reserved_7_5_WIDTH                          3
#define D0F2xF4_x14_Reserved_7_5_MASK                           0xe0
#define D0F2xF4_x14_ITCInvalidationSel_OFFSET                   8
#define D0F2xF4_x14_ITCInvalidationSel_WIDTH                    2
#define D0F2xF4_x14_ITCInvalidationSel_MASK                     0x300
#define D0F2xF4_x14_ITCSoftInvalidate_OFFSET                    10
#define D0F2xF4_x14_ITCSoftInvalidate_WIDTH                     1
#define D0F2xF4_x14_ITCSoftInvalidate_MASK                      0x400
#define D0F2xF4_x14_Reserved_12_11_OFFSET                       11
#define D0F2xF4_x14_Reserved_12_11_WIDTH                        2
#define D0F2xF4_x14_Reserved_12_11_MASK                         0x1800
#define D0F2xF4_x14_ITCBypass_OFFSET                            13
#define D0F2xF4_x14_ITCBypass_WIDTH                             1
#define D0F2xF4_x14_ITCBypass_MASK                              0x2000
#define D0F2xF4_x14_Reserved_14_14_OFFSET                       14
#define D0F2xF4_x14_Reserved_14_14_WIDTH                        1
#define D0F2xF4_x14_Reserved_14_14_MASK                         0x4000
#define D0F2xF4_x14_ITCParitySupport_OFFSET                     15
#define D0F2xF4_x14_ITCParitySupport_WIDTH                      1
#define D0F2xF4_x14_ITCParitySupport_MASK                       0x8000
#define D0F2xF4_x14_ITCWays_OFFSET                              16
#define D0F2xF4_x14_ITCWays_WIDTH                               8
#define D0F2xF4_x14_ITCWays_MASK                                0xff0000
#define D0F2xF4_x14_Reserved_27_24_OFFSET                       24
#define D0F2xF4_x14_Reserved_27_24_WIDTH                        4
#define D0F2xF4_x14_Reserved_27_24_MASK                         0xf000000
#define D0F2xF4_x14_ITCEntries_OFFSET                           28
#define D0F2xF4_x14_ITCEntries_WIDTH                            4
#define D0F2xF4_x14_ITCEntries_MASK                             0xf0000000

/// D0F2xF4_x14
typedef union {
  struct {                                                              ///<
    UINT32                                        ITCReplacementSel:2 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                          ITCLRUUpdatePri:1 ; ///<
    UINT32                                              ITCParityEn:1 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                       ITCInvalidationSel:2 ; ///<
    UINT32                                        ITCSoftInvalidate:1 ; ///<
    UINT32                                           Reserved_12_11:2 ; ///<
    UINT32                                                ITCBypass:1 ; ///<
    UINT32                                           Reserved_14_14:1 ; ///<
    UINT32                                         ITCParitySupport:1 ; ///<
    UINT32                                                  ITCWays:8 ; ///<
    UINT32                                           Reserved_27_24:4 ; ///<
    UINT32                                               ITCEntries:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x14_STRUCT;

// **** D0F2xF4_x15 Register Definition ****
// Address
#define D0F2xF4_x15_ADDRESS                                     0x15

// Type
#define D0F2xF4_x15_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x15_ITCFuncBits_OFFSET                          0
#define D0F2xF4_x15_ITCFuncBits_WIDTH                           2
#define D0F2xF4_x15_ITCFuncBits_MASK                            0x3
#define D0F2xF4_x15_ITCDevBits_OFFSET                           2
#define D0F2xF4_x15_ITCDevBits_WIDTH                            3
#define D0F2xF4_x15_ITCDevBits_MASK                             0x1c
#define D0F2xF4_x15_ITCBusBits_OFFSET                           5
#define D0F2xF4_x15_ITCBusBits_WIDTH                            4
#define D0F2xF4_x15_ITCBusBits_MASK                             0x1e0
#define D0F2xF4_x15_Reserved_9_9_OFFSET                         9
#define D0F2xF4_x15_Reserved_9_9_WIDTH                          1
#define D0F2xF4_x15_Reserved_9_9_MASK                           0x200
#define D0F2xF4_x15_ItcAltHashEn_OFFSET                         10
#define D0F2xF4_x15_ItcAltHashEn_WIDTH                          1
#define D0F2xF4_x15_ItcAltHashEn_MASK                           0x400
#define D0F2xF4_x15_Reserved_15_11_OFFSET                       11
#define D0F2xF4_x15_Reserved_15_11_WIDTH                        5
#define D0F2xF4_x15_Reserved_15_11_MASK                         0xf800
#define D0F2xF4_x15_ITCAddressMask_OFFSET                       16
#define D0F2xF4_x15_ITCAddressMask_WIDTH                        16
#define D0F2xF4_x15_ITCAddressMask_MASK                         0xffff0000

/// D0F2xF4_x15
typedef union {
  struct {                                                              ///<
    UINT32                                              ITCFuncBits:2 ; ///<
    UINT32                                               ITCDevBits:3 ; ///<
    UINT32                                               ITCBusBits:4 ; ///<
    UINT32                                             Reserved_9_9:1 ; ///<
    UINT32                                             ItcAltHashEn:1 ; ///<
    UINT32                                           Reserved_15_11:5 ; ///<
    UINT32                                           ITCAddressMask:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x15_STRUCT;

// **** D0F2xF4_x16 Register Definition ****
// Address
#define D0F2xF4_x16_ADDRESS                                     0x16

// Type
#define D0F2xF4_x16_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x16_ITCWayDisable_OFFSET                        0
#define D0F2xF4_x16_ITCWayDisable_WIDTH                         16
#define D0F2xF4_x16_ITCWayDisable_MASK                          0xffff
#define D0F2xF4_x16_ITCWayAccessDisable_OFFSET                  16
#define D0F2xF4_x16_ITCWayAccessDisable_WIDTH                   16
#define D0F2xF4_x16_ITCWayAccessDisable_MASK                    0xffff0000

/// D0F2xF4_x16
typedef union {
  struct {                                                              ///<
    UINT32                                            ITCWayDisable:16; ///<
    UINT32                                      ITCWayAccessDisable:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x16_STRUCT;

// **** D0F2xF4_x18 Register Definition ****
// Address
#define D0F2xF4_x18_ADDRESS                                     0x18

// Type
#define D0F2xF4_x18_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x18_PTCAReplacementSel_OFFSET                   0
#define D0F2xF4_x18_PTCAReplacementSel_WIDTH                    2
#define D0F2xF4_x18_PTCAReplacementSel_MASK                     0x3
#define D0F2xF4_x18_Reserved_2_2_OFFSET                         2
#define D0F2xF4_x18_Reserved_2_2_WIDTH                          1
#define D0F2xF4_x18_Reserved_2_2_MASK                           0x4
#define D0F2xF4_x18_PTCALRUUpdatePri_OFFSET                     3
#define D0F2xF4_x18_PTCALRUUpdatePri_WIDTH                      1
#define D0F2xF4_x18_PTCALRUUpdatePri_MASK                       0x8
#define D0F2xF4_x18_PTCAParityEn_OFFSET                         4
#define D0F2xF4_x18_PTCAParityEn_WIDTH                          1
#define D0F2xF4_x18_PTCAParityEn_MASK                           0x10
#define D0F2xF4_x18_Reserved_7_5_OFFSET                         5
#define D0F2xF4_x18_Reserved_7_5_WIDTH                          3
#define D0F2xF4_x18_Reserved_7_5_MASK                           0xe0
#define D0F2xF4_x18_PTCAInvalidationSel_OFFSET                  8
#define D0F2xF4_x18_PTCAInvalidationSel_WIDTH                   2
#define D0F2xF4_x18_PTCAInvalidationSel_MASK                    0x300
#define D0F2xF4_x18_PTCASoftInvalidate_OFFSET                   10
#define D0F2xF4_x18_PTCASoftInvalidate_WIDTH                    1
#define D0F2xF4_x18_PTCASoftInvalidate_MASK                     0x400
#define D0F2xF4_x18_PTCA2MMode_OFFSET                           11
#define D0F2xF4_x18_PTCA2MMode_WIDTH                            1
#define D0F2xF4_x18_PTCA2MMode_MASK                             0x800
#define D0F2xF4_x18_Reserved_12_12_OFFSET                       12
#define D0F2xF4_x18_Reserved_12_12_WIDTH                        1
#define D0F2xF4_x18_Reserved_12_12_MASK                         0x1000
#define D0F2xF4_x18_PTCABypass_OFFSET                           13
#define D0F2xF4_x18_PTCABypass_WIDTH                            1
#define D0F2xF4_x18_PTCABypass_MASK                             0x2000
#define D0F2xF4_x18_Reserved_14_14_OFFSET                       14
#define D0F2xF4_x18_Reserved_14_14_WIDTH                        1
#define D0F2xF4_x18_Reserved_14_14_MASK                         0x4000
#define D0F2xF4_x18_PTCAParitySupport_OFFSET                    15
#define D0F2xF4_x18_PTCAParitySupport_WIDTH                     1
#define D0F2xF4_x18_PTCAParitySupport_MASK                      0x8000
#define D0F2xF4_x18_PTCAWays_OFFSET                             16
#define D0F2xF4_x18_PTCAWays_WIDTH                              8
#define D0F2xF4_x18_PTCAWays_MASK                               0xff0000
#define D0F2xF4_x18_Reserved_27_24_OFFSET                       24
#define D0F2xF4_x18_Reserved_27_24_WIDTH                        4
#define D0F2xF4_x18_Reserved_27_24_MASK                         0xf000000
#define D0F2xF4_x18_PTCAEntries_OFFSET                          28
#define D0F2xF4_x18_PTCAEntries_WIDTH                           4
#define D0F2xF4_x18_PTCAEntries_MASK                            0xf0000000

/// D0F2xF4_x18
typedef union {
  struct {                                                              ///<
    UINT32                                       PTCAReplacementSel:2 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                         PTCALRUUpdatePri:1 ; ///<
    UINT32                                             PTCAParityEn:1 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                      PTCAInvalidationSel:2 ; ///<
    UINT32                                       PTCASoftInvalidate:1 ; ///<
    UINT32                                               PTCA2MMode:1 ; ///<
    UINT32                                           Reserved_12_12:1 ; ///<
    UINT32                                               PTCABypass:1 ; ///<
    UINT32                                           Reserved_14_14:1 ; ///<
    UINT32                                        PTCAParitySupport:1 ; ///<
    UINT32                                                 PTCAWays:8 ; ///<
    UINT32                                           Reserved_27_24:4 ; ///<
    UINT32                                              PTCAEntries:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x18_STRUCT;

// **** D0F2xF4_x19 Register Definition ****
// Address
#define D0F2xF4_x19_ADDRESS                                     0x19

// Type
#define D0F2xF4_x19_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x19_PTCAFuncBits_OFFSET                         0
#define D0F2xF4_x19_PTCAFuncBits_WIDTH                          2
#define D0F2xF4_x19_PTCAFuncBits_MASK                           0x3
#define D0F2xF4_x19_PTCADevBits_OFFSET                          2
#define D0F2xF4_x19_PTCADevBits_WIDTH                           3
#define D0F2xF4_x19_PTCADevBits_MASK                            0x1c
#define D0F2xF4_x19_PTCABusBits_OFFSET                          5
#define D0F2xF4_x19_PTCABusBits_WIDTH                           4
#define D0F2xF4_x19_PTCABusBits_MASK                            0x1e0
#define D0F2xF4_x19_Reserved_9_9_OFFSET                         9
#define D0F2xF4_x19_Reserved_9_9_WIDTH                          1
#define D0F2xF4_x19_Reserved_9_9_MASK                           0x200
#define D0F2xF4_x19_PtcAltHashEn_OFFSET                         10
#define D0F2xF4_x19_PtcAltHashEn_WIDTH                          1
#define D0F2xF4_x19_PtcAltHashEn_MASK                           0x400
#define D0F2xF4_x19_Reserved_15_11_OFFSET                       11
#define D0F2xF4_x19_Reserved_15_11_WIDTH                        5
#define D0F2xF4_x19_Reserved_15_11_MASK                         0xf800
#define D0F2xF4_x19_PTCAAddressMask_OFFSET                      16
#define D0F2xF4_x19_PTCAAddressMask_WIDTH                       16
#define D0F2xF4_x19_PTCAAddressMask_MASK                        0xffff0000

/// D0F2xF4_x19
typedef union {
  struct {                                                              ///<
    UINT32                                             PTCAFuncBits:2 ; ///<
    UINT32                                              PTCADevBits:3 ; ///<
    UINT32                                              PTCABusBits:4 ; ///<
    UINT32                                             Reserved_9_9:1 ; ///<
    UINT32                                             PtcAltHashEn:1 ; ///<
    UINT32                                           Reserved_15_11:5 ; ///<
    UINT32                                          PTCAAddressMask:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x19_STRUCT;

// **** D0F2xF4_x1A Register Definition ****
// Address
#define D0F2xF4_x1A_ADDRESS                                     0x1a

// Type
#define D0F2xF4_x1A_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x1A_PTCAWayDisable_OFFSET                       0
#define D0F2xF4_x1A_PTCAWayDisable_WIDTH                        16
#define D0F2xF4_x1A_PTCAWayDisable_MASK                         0xffff
#define D0F2xF4_x1A_PTCAWayAccessDisable_OFFSET                 16
#define D0F2xF4_x1A_PTCAWayAccessDisable_WIDTH                  16
#define D0F2xF4_x1A_PTCAWayAccessDisable_MASK                   0xffff0000

/// D0F2xF4_x1A
typedef union {
  struct {                                                              ///<
    UINT32                                           PTCAWayDisable:16; ///<
    UINT32                                     PTCAWayAccessDisable:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x1A_STRUCT;

// **** D0F2xF4_x20 Register Definition ****
// Address
#define D0F2xF4_x20_ADDRESS                                     0x20

// Type
#define D0F2xF4_x20_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x20_QUEUECredits_OFFSET                         0
#define D0F2xF4_x20_QUEUECredits_WIDTH                          6
#define D0F2xF4_x20_QUEUECredits_MASK                           0x3f
#define D0F2xF4_x20_Reserved_6_6_OFFSET                         6
#define D0F2xF4_x20_Reserved_6_6_WIDTH                          1
#define D0F2xF4_x20_Reserved_6_6_MASK                           0x40
#define D0F2xF4_x20_QUEUEOverride_OFFSET                        7
#define D0F2xF4_x20_QUEUEOverride_WIDTH                         1
#define D0F2xF4_x20_QUEUEOverride_MASK                          0x80
#define D0F2xF4_x20_FLTCMBCredits_OFFSET                        8
#define D0F2xF4_x20_FLTCMBCredits_WIDTH                         6
#define D0F2xF4_x20_FLTCMBCredits_MASK                          0x3f00
#define D0F2xF4_x20_Reserved_14_14_OFFSET                       14
#define D0F2xF4_x20_Reserved_14_14_WIDTH                        1
#define D0F2xF4_x20_Reserved_14_14_MASK                         0x4000
#define D0F2xF4_x20_FLTCMBOverride_OFFSET                       15
#define D0F2xF4_x20_FLTCMBOverride_WIDTH                        1
#define D0F2xF4_x20_FLTCMBOverride_MASK                         0x8000
#define D0F2xF4_x20_FCELCredits_OFFSET                          16
#define D0F2xF4_x20_FCELCredits_WIDTH                           6
#define D0F2xF4_x20_FCELCredits_MASK                            0x3f0000
#define D0F2xF4_x20_Reserved_22_22_OFFSET                       22
#define D0F2xF4_x20_Reserved_22_22_WIDTH                        1
#define D0F2xF4_x20_Reserved_22_22_MASK                         0x400000
#define D0F2xF4_x20_FCELOverride_OFFSET                         23
#define D0F2xF4_x20_FCELOverride_WIDTH                          1
#define D0F2xF4_x20_FCELOverride_MASK                           0x800000
#define D0F2xF4_x20_PprLoggerCredits_OFFSET                     24
#define D0F2xF4_x20_PprLoggerCredits_WIDTH                      4
#define D0F2xF4_x20_PprLoggerCredits_MASK                       0xf000000
#define D0F2xF4_x20_Reserved_31_28_OFFSET                       28
#define D0F2xF4_x20_Reserved_31_28_WIDTH                        4
#define D0F2xF4_x20_Reserved_31_28_MASK                         0xf0000000

/// D0F2xF4_x20
typedef union {
  struct {                                                              ///<
    UINT32                                             QUEUECredits:6 ; ///<
    UINT32                                             Reserved_6_6:1 ; ///<
    UINT32                                            QUEUEOverride:1 ; ///<
    UINT32                                            FLTCMBCredits:6 ; ///<
    UINT32                                           Reserved_14_14:1 ; ///<
    UINT32                                           FLTCMBOverride:1 ; ///<
    UINT32                                              FCELCredits:6 ; ///<
    UINT32                                           Reserved_22_22:1 ; ///<
    UINT32                                             FCELOverride:1 ; ///<
    UINT32                                         PprLoggerCredits:4 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x20_STRUCT;

// **** D0F2xF4_x22 Register Definition ****
// Address
#define D0F2xF4_x22_ADDRESS                                     0x22

// Type
#define D0F2xF4_x22_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x22_L2aUpdateFilterBypass_OFFSET                0
#define D0F2xF4_x22_L2aUpdateFilterBypass_WIDTH                 1
#define D0F2xF4_x22_L2aUpdateFilterBypass_MASK                  0x1
#define D0F2xF4_x22_L2aUpdateFilterRdlatency_OFFSET             1
#define D0F2xF4_x22_L2aUpdateFilterRdlatency_WIDTH              4
#define D0F2xF4_x22_L2aUpdateFilterRdlatency_MASK               0x1e
#define D0F2xF4_x22_Reserved_31_5_OFFSET                        5
#define D0F2xF4_x22_Reserved_31_5_WIDTH                         27
#define D0F2xF4_x22_Reserved_31_5_MASK                          0xffffffe0

/// D0F2xF4_x22
typedef union {
  struct {                                                              ///<
    UINT32                                    L2aUpdateFilterBypass:1 ; ///<
    UINT32                                 L2aUpdateFilterRdlatency:4 ; ///<
    UINT32                                            Reserved_31_5:27; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x22_STRUCT;







// **** D0F2xF4_x30 Register Definition ****
// Address
#define D0F2xF4_x30_ADDRESS                                     0x30

// Type
#define D0F2xF4_x30_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x30_ERRRuleLock1_OFFSET                         0
#define D0F2xF4_x30_ERRRuleLock1_WIDTH                          1
#define D0F2xF4_x30_ERRRuleLock1_MASK                           0x1
#define D0F2xF4_x30_Reserved_3_1_OFFSET                         1
#define D0F2xF4_x30_Reserved_3_1_WIDTH                          3
#define D0F2xF4_x30_Reserved_3_1_MASK                           0xe
#define D0F2xF4_x30_ERRRuleDisable3_OFFSET                      4
#define D0F2xF4_x30_ERRRuleDisable3_WIDTH                       28
#define D0F2xF4_x30_ERRRuleDisable3_MASK                        0xfffffff0

/// D0F2xF4_x30
typedef union {
  struct {                                                              ///<
    UINT32                                             ERRRuleLock1:1 ; ///<
    UINT32                                             Reserved_3_1:3 ; ///<
    UINT32                                          ERRRuleDisable3:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x30_STRUCT;

// **** D0F2xF4_x31 Register Definition ****
// Address
#define D0F2xF4_x31_ADDRESS                                     0x31

// Type
#define D0F2xF4_x31_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x31_ERRRuleDisable4_OFFSET                      0
#define D0F2xF4_x31_ERRRuleDisable4_WIDTH                       32
#define D0F2xF4_x31_ERRRuleDisable4_MASK                        0xffffffff

/// D0F2xF4_x31
typedef union {
  struct {                                                              ///<
    UINT32                                          ERRRuleDisable4:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x31_STRUCT;

// **** D0F2xF4_x32 Register Definition ****
// Address
#define D0F2xF4_x32_ADDRESS                                     0x32

// Type
#define D0F2xF4_x32_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x32_ERRRuleDisable5_OFFSET                      0
#define D0F2xF4_x32_ERRRuleDisable5_WIDTH                       32
#define D0F2xF4_x32_ERRRuleDisable5_MASK                        0xffffffff

/// D0F2xF4_x32
typedef union {
  struct {                                                              ///<
    UINT32                                          ERRRuleDisable5:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x32_STRUCT;

// **** D0F2xF4_x33 Register Definition ****
// Address
#define D0F2xF4_x33_ADDRESS                                     0x33

// Type
#define D0F2xF4_x33_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x33_CKGateL2ARegsDisable_OFFSET                 0
#define D0F2xF4_x33_CKGateL2ARegsDisable_WIDTH                  1
#define D0F2xF4_x33_CKGateL2ARegsDisable_MASK                   0x1
#define D0F2xF4_x33_CKGateL2ADynamicDisable_OFFSET              1
#define D0F2xF4_x33_CKGateL2ADynamicDisable_WIDTH               1
#define D0F2xF4_x33_CKGateL2ADynamicDisable_MASK                0x2
#define D0F2xF4_x33_CKGateL2ACacheDisable_OFFSET                2
#define D0F2xF4_x33_CKGateL2ACacheDisable_WIDTH                 1
#define D0F2xF4_x33_CKGateL2ACacheDisable_MASK                  0x4
#define D0F2xF4_x33_CKGateL2ASpare_OFFSET                       3
#define D0F2xF4_x33_CKGateL2ASpare_WIDTH                        1
#define D0F2xF4_x33_CKGateL2ASpare_MASK                         0x8
#define D0F2xF4_x33_CKGateL2ALength_OFFSET                      4
#define D0F2xF4_x33_CKGateL2ALength_WIDTH                       2
#define D0F2xF4_x33_CKGateL2ALength_MASK                        0x30
#define D0F2xF4_x33_CKGateL2AStop_OFFSET                        6
#define D0F2xF4_x33_CKGateL2AStop_WIDTH                         2
#define D0F2xF4_x33_CKGateL2AStop_MASK                          0xc0
#define D0F2xF4_x33_Reserved_31_8_OFFSET                        8
#define D0F2xF4_x33_Reserved_31_8_WIDTH                         24
#define D0F2xF4_x33_Reserved_31_8_MASK                          0xffffff00

/// D0F2xF4_x33
typedef union {
  struct {                                                              ///<
    UINT32                                     CKGateL2ARegsDisable:1 ; ///<
    UINT32                                  CKGateL2ADynamicDisable:1 ; ///<
    UINT32                                    CKGateL2ACacheDisable:1 ; ///<
    UINT32                                           CKGateL2ASpare:1 ; ///<
    UINT32                                          CKGateL2ALength:2 ; ///<
    UINT32                                            CKGateL2AStop:2 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x33_STRUCT;

// **** D0F2xF4_x34 Register Definition ****
// Address
#define D0F2xF4_x34_ADDRESS                                     0x34

// Type
#define D0F2xF4_x34_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x34_L2aregGstPgsize_OFFSET                      0
#define D0F2xF4_x34_L2aregGstPgsize_WIDTH                       2
#define D0F2xF4_x34_L2aregGstPgsize_MASK                        0x3
#define D0F2xF4_x34_L2aregHostPgsize_OFFSET                     2
#define D0F2xF4_x34_L2aregHostPgsize_WIDTH                      2
#define D0F2xF4_x34_L2aregHostPgsize_MASK                       0xc
#define D0F2xF4_x34_Reserved_31_4_OFFSET                        4
#define D0F2xF4_x34_Reserved_31_4_WIDTH                         28
#define D0F2xF4_x34_Reserved_31_4_MASK                          0xfffffff0

/// D0F2xF4_x34
typedef union {
  struct {                                                              ///<
    UINT32                                          L2aregGstPgsize:2 ; ///<
    UINT32                                         L2aregHostPgsize:2 ; ///<
    UINT32                                            Reserved_31_4:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x34_STRUCT;

// **** D0F2xF4_x40 Register Definition ****
// Address
#define D0F2xF4_x40_ADDRESS                                     0x40

// Type
#define D0F2xF4_x40_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x40_L2PerfEvent4_OFFSET                         0
#define D0F2xF4_x40_L2PerfEvent4_WIDTH                          8
#define D0F2xF4_x40_L2PerfEvent4_MASK                           0xff
#define D0F2xF4_x40_L2PerfEvent5_OFFSET                         8
#define D0F2xF4_x40_L2PerfEvent5_WIDTH                          8
#define D0F2xF4_x40_L2PerfEvent5_MASK                           0xff00
#define D0F2xF4_x40_L2PerfCountUpper4_OFFSET                    16
#define D0F2xF4_x40_L2PerfCountUpper4_WIDTH                     8
#define D0F2xF4_x40_L2PerfCountUpper4_MASK                      0xff0000
#define D0F2xF4_x40_L2PerfCountUpper5_OFFSET                    24
#define D0F2xF4_x40_L2PerfCountUpper5_WIDTH                     8
#define D0F2xF4_x40_L2PerfCountUpper5_MASK                      0xff000000

/// D0F2xF4_x40
typedef union {
  struct {                                                              ///<
    UINT32                                             L2PerfEvent4:8 ; ///<
    UINT32                                             L2PerfEvent5:8 ; ///<
    UINT32                                        L2PerfCountUpper4:8 ; ///<
    UINT32                                        L2PerfCountUpper5:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x40_STRUCT;

// **** D0F2xF4_x41 Register Definition ****
// Address
#define D0F2xF4_x41_ADDRESS                                     0x41

// Type
#define D0F2xF4_x41_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x41_L2PerfCount4_OFFSET                         0
#define D0F2xF4_x41_L2PerfCount4_WIDTH                          32
#define D0F2xF4_x41_L2PerfCount4_MASK                           0xffffffff

/// D0F2xF4_x41
typedef union {
  struct {                                                              ///<
    UINT32                                             L2PerfCount4:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x41_STRUCT;

// **** D0F2xF4_x42 Register Definition ****
// Address
#define D0F2xF4_x42_ADDRESS                                     0x42

// Type
#define D0F2xF4_x42_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x42_L2PerfCount5_OFFSET                         0
#define D0F2xF4_x42_L2PerfCount5_WIDTH                          32
#define D0F2xF4_x42_L2PerfCount5_MASK                           0xffffffff

/// D0F2xF4_x42
typedef union {
  struct {                                                              ///<
    UINT32                                             L2PerfCount5:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x42_STRUCT;

// **** D0F2xF4_x43 Register Definition ****
// Address
#define D0F2xF4_x43_ADDRESS                                     0x43

// Type
#define D0F2xF4_x43_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x43_L2PerfEvent6_OFFSET                         0
#define D0F2xF4_x43_L2PerfEvent6_WIDTH                          8
#define D0F2xF4_x43_L2PerfEvent6_MASK                           0xff
#define D0F2xF4_x43_L2PerfEvent7_OFFSET                         8
#define D0F2xF4_x43_L2PerfEvent7_WIDTH                          8
#define D0F2xF4_x43_L2PerfEvent7_MASK                           0xff00
#define D0F2xF4_x43_L2PerfCountUpper6_OFFSET                    16
#define D0F2xF4_x43_L2PerfCountUpper6_WIDTH                     8
#define D0F2xF4_x43_L2PerfCountUpper6_MASK                      0xff0000
#define D0F2xF4_x43_L2PerfCountUpper7_OFFSET                    24
#define D0F2xF4_x43_L2PerfCountUpper7_WIDTH                     8
#define D0F2xF4_x43_L2PerfCountUpper7_MASK                      0xff000000

/// D0F2xF4_x43
typedef union {
  struct {                                                              ///<
    UINT32                                             L2PerfEvent6:8 ; ///<
    UINT32                                             L2PerfEvent7:8 ; ///<
    UINT32                                        L2PerfCountUpper6:8 ; ///<
    UINT32                                        L2PerfCountUpper7:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x43_STRUCT;

// **** D0F2xF4_x44 Register Definition ****
// Address
#define D0F2xF4_x44_ADDRESS                                     0x44

// Type
#define D0F2xF4_x44_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x44_L2PerfCount6_OFFSET                         0
#define D0F2xF4_x44_L2PerfCount6_WIDTH                          32
#define D0F2xF4_x44_L2PerfCount6_MASK                           0xffffffff

/// D0F2xF4_x44
typedef union {
  struct {                                                              ///<
    UINT32                                             L2PerfCount6:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x44_STRUCT;

// **** D0F2xF4_x45 Register Definition ****
// Address
#define D0F2xF4_x45_ADDRESS                                     0x45

// Type
#define D0F2xF4_x45_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x45_L2PerfCount7_OFFSET                         0
#define D0F2xF4_x45_L2PerfCount7_WIDTH                          32
#define D0F2xF4_x45_L2PerfCount7_MASK                           0xffffffff

/// D0F2xF4_x45
typedef union {
  struct {                                                              ///<
    UINT32                                             L2PerfCount7:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x45_STRUCT;

// **** D0F2xF4_x46 Register Definition ****
// Address
#define D0F2xF4_x46_ADDRESS                                     0x46

// Type
#define D0F2xF4_x46_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x46_L2DEBUG2_OFFSET                             0
#define D0F2xF4_x46_L2DEBUG2_WIDTH                              32
#define D0F2xF4_x46_L2DEBUG2_MASK                               0xffffffff

/// D0F2xF4_x46
typedef union {
  struct {                                                              ///<
    UINT32                                                 L2DEBUG2:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x46_STRUCT;

// **** D0F2xF4_x47 Register Definition ****
// Address
#define D0F2xF4_x47_ADDRESS                                     0x47

// Type
#define D0F2xF4_x47_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x47_Reserved_0_0_OFFSET                         0
#define D0F2xF4_x47_Reserved_0_0_WIDTH                          1
#define D0F2xF4_x47_Reserved_0_0_MASK                           0x1
#define D0F2xF4_x47_TwNwEn_OFFSET                               1
#define D0F2xF4_x47_TwNwEn_WIDTH                                1
#define D0F2xF4_x47_TwNwEn_MASK                                 0x2
#define D0F2xF4_x47_TwAtomicFilterEn_OFFSET                     2
#define D0F2xF4_x47_TwAtomicFilterEn_WIDTH                      1
#define D0F2xF4_x47_TwAtomicFilterEn_MASK                       0x4
#define D0F2xF4_x47_Reserved_31_3_OFFSET                        3
#define D0F2xF4_x47_Reserved_31_3_WIDTH                         29
#define D0F2xF4_x47_Reserved_31_3_MASK                          0xfffffff8

/// D0F2xF4_x47
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                   TwNwEn:1 ; ///<
    UINT32                                         TwAtomicFilterEn:1 ; ///<
    UINT32                                            Reserved_31_3:29; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x47_STRUCT;

// **** D0F2xF4_x48 Register Definition ****
// Address
#define D0F2xF4_x48_ADDRESS                                     0x48

// Type
#define D0F2xF4_x48_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x48_L2STATUS1_OFFSET                            0
#define D0F2xF4_x48_L2STATUS1_WIDTH                             32
#define D0F2xF4_x48_L2STATUS1_MASK                              0xffffffff

/// D0F2xF4_x48
typedef union {
  struct {                                                              ///<
    UINT32                                                L2STATUS1:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x48_STRUCT;

// **** D0F2xF4_x4C Register Definition ****
// Address
#define D0F2xF4_x4C_ADDRESS                                     0x4c

// Type
#define D0F2xF4_x4C_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x4C_QueueArbFBPri_OFFSET                        0
#define D0F2xF4_x4C_QueueArbFBPri_WIDTH                         1
#define D0F2xF4_x4C_QueueArbFBPri_MASK                          0x1
#define D0F2xF4_x4C_PTCAddrTransReqUpdate_OFFSET                1
#define D0F2xF4_x4C_PTCAddrTransReqUpdate_WIDTH                 1
#define D0F2xF4_x4C_PTCAddrTransReqUpdate_MASK                  0x2
#define D0F2xF4_x4C_FC1Dis_OFFSET                               2
#define D0F2xF4_x4C_FC1Dis_WIDTH                                1
#define D0F2xF4_x4C_FC1Dis_MASK                                 0x4
#define D0F2xF4_x4C_DTCUpdateVOneIVZero_OFFSET                  3
#define D0F2xF4_x4C_DTCUpdateVOneIVZero_WIDTH                   1
#define D0F2xF4_x4C_DTCUpdateVOneIVZero_MASK                    0x8
#define D0F2xF4_x4C_DTCUpdateVZeroIVOne_OFFSET                  4
#define D0F2xF4_x4C_DTCUpdateVZeroIVOne_WIDTH                   1
#define D0F2xF4_x4C_DTCUpdateVZeroIVOne_MASK                    0x10
#define D0F2xF4_x4C_FC2Dis_OFFSET                               5
#define D0F2xF4_x4C_FC2Dis_WIDTH                                1
#define D0F2xF4_x4C_FC2Dis_MASK                                 0x20
#define D0F2xF4_x4C_FC3Dis_OFFSET                               6
#define D0F2xF4_x4C_FC3Dis_WIDTH                                1
#define D0F2xF4_x4C_FC3Dis_MASK                                 0x40
#define D0F2xF4_x4C_FC2AltMode_OFFSET                           7
#define D0F2xF4_x4C_FC2AltMode_WIDTH                            1
#define D0F2xF4_x4C_FC2AltMode_MASK                             0x80
#define D0F2xF4_x4C_GstPartialPtcCntrl_OFFSET                   8
#define D0F2xF4_x4C_GstPartialPtcCntrl_WIDTH                    2
#define D0F2xF4_x4C_GstPartialPtcCntrl_MASK                     0x300
#define D0F2xF4_x4C_Reserved_31_10_OFFSET                       10
#define D0F2xF4_x4C_Reserved_31_10_WIDTH                        22
#define D0F2xF4_x4C_Reserved_31_10_MASK                         0xfffffc00

/// D0F2xF4_x4C
typedef union {
  struct {                                                              ///<
    UINT32                                            QueueArbFBPri:1 ; ///<
    UINT32                                    PTCAddrTransReqUpdate:1 ; ///<
    UINT32                                                   FC1Dis:1 ; ///<
    UINT32                                      DTCUpdateVOneIVZero:1 ; ///<
    UINT32                                      DTCUpdateVZeroIVOne:1 ; ///<
    UINT32                                                   FC2Dis:1 ; ///<
    UINT32                                                   FC3Dis:1 ; ///<
    UINT32                                               FC2AltMode:1 ; ///<
    UINT32                                       GstPartialPtcCntrl:2 ; ///<
    UINT32                                           Reserved_31_10:22; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x4C_STRUCT;

// **** D0F2xF4_x4D Register Definition ****
// Address
#define D0F2xF4_x4D_ADDRESS                                     0x4d

// Type
#define D0F2xF4_x4D_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x4D_SeqInvBurstLimitInv_OFFSET                  0
#define D0F2xF4_x4D_SeqInvBurstLimitInv_WIDTH                   8
#define D0F2xF4_x4D_SeqInvBurstLimitInv_MASK                    0xff
#define D0F2xF4_x4D_SeqInvBurstLimitPDCReq_OFFSET               8
#define D0F2xF4_x4D_SeqInvBurstLimitPDCReq_WIDTH                8
#define D0F2xF4_x4D_SeqInvBurstLimitPDCReq_MASK                 0xff00
#define D0F2xF4_x4D_SeqInvBurstLimitEn_OFFSET                   16
#define D0F2xF4_x4D_SeqInvBurstLimitEn_WIDTH                    1
#define D0F2xF4_x4D_SeqInvBurstLimitEn_MASK                     0x10000
#define D0F2xF4_x4D_Reserved_23_17_OFFSET                       17
#define D0F2xF4_x4D_Reserved_23_17_WIDTH                        7
#define D0F2xF4_x4D_Reserved_23_17_MASK                         0xfe0000
#define D0F2xF4_x4D_Perf2Threshold_OFFSET                       24
#define D0F2xF4_x4D_Perf2Threshold_WIDTH                        8
#define D0F2xF4_x4D_Perf2Threshold_MASK                         0xff000000

/// D0F2xF4_x4D
typedef union {
  struct {                                                              ///<
    UINT32                                      SeqInvBurstLimitInv:8 ; ///<
    UINT32                                   SeqInvBurstLimitPDCReq:8 ; ///<
    UINT32                                       SeqInvBurstLimitEn:1 ; ///<
    UINT32                                           Reserved_23_17:7 ; ///<
    UINT32                                           Perf2Threshold:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x4D_STRUCT;

// **** D0F2xF4_x50 Register Definition ****
// Address
#define D0F2xF4_x50_ADDRESS                                     0x50

// Type
#define D0F2xF4_x50_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x50_PDCReplacementSel_OFFSET                    0
#define D0F2xF4_x50_PDCReplacementSel_WIDTH                     2
#define D0F2xF4_x50_PDCReplacementSel_MASK                      0x3
#define D0F2xF4_x50_Reserved_2_2_OFFSET                         2
#define D0F2xF4_x50_Reserved_2_2_WIDTH                          1
#define D0F2xF4_x50_Reserved_2_2_MASK                           0x4
#define D0F2xF4_x50_PDCLRUUpdatePri_OFFSET                      3
#define D0F2xF4_x50_PDCLRUUpdatePri_WIDTH                       1
#define D0F2xF4_x50_PDCLRUUpdatePri_MASK                        0x8
#define D0F2xF4_x50_PDCParityEn_OFFSET                          4
#define D0F2xF4_x50_PDCParityEn_WIDTH                           1
#define D0F2xF4_x50_PDCParityEn_MASK                            0x10
#define D0F2xF4_x50_Reserved_7_5_OFFSET                         5
#define D0F2xF4_x50_Reserved_7_5_WIDTH                          3
#define D0F2xF4_x50_Reserved_7_5_MASK                           0xe0
#define D0F2xF4_x50_PDCInvalidationSel_OFFSET                   8
#define D0F2xF4_x50_PDCInvalidationSel_WIDTH                    2
#define D0F2xF4_x50_PDCInvalidationSel_MASK                     0x300
#define D0F2xF4_x50_PDCSoftInvalidate_OFFSET                    10
#define D0F2xF4_x50_PDCSoftInvalidate_WIDTH                     1
#define D0F2xF4_x50_PDCSoftInvalidate_MASK                      0x400
#define D0F2xF4_x50_Reserved_11_11_OFFSET                       11
#define D0F2xF4_x50_Reserved_11_11_WIDTH                        1
#define D0F2xF4_x50_Reserved_11_11_MASK                         0x800
#define D0F2xF4_x50_PDCSearchDirection_OFFSET                   12
#define D0F2xF4_x50_PDCSearchDirection_WIDTH                    1
#define D0F2xF4_x50_PDCSearchDirection_MASK                     0x1000
#define D0F2xF4_x50_PDCBypass_OFFSET                            13
#define D0F2xF4_x50_PDCBypass_WIDTH                             1
#define D0F2xF4_x50_PDCBypass_MASK                              0x2000
#define D0F2xF4_x50_Reserved_14_14_OFFSET                       14
#define D0F2xF4_x50_Reserved_14_14_WIDTH                        1
#define D0F2xF4_x50_Reserved_14_14_MASK                         0x4000
#define D0F2xF4_x50_PDCParitySupport_OFFSET                     15
#define D0F2xF4_x50_PDCParitySupport_WIDTH                      1
#define D0F2xF4_x50_PDCParitySupport_MASK                       0x8000
#define D0F2xF4_x50_PDCWays_OFFSET                              16
#define D0F2xF4_x50_PDCWays_WIDTH                               8
#define D0F2xF4_x50_PDCWays_MASK                                0xff0000
#define D0F2xF4_x50_Reserved_27_24_OFFSET                       24
#define D0F2xF4_x50_Reserved_27_24_WIDTH                        4
#define D0F2xF4_x50_Reserved_27_24_MASK                         0xf000000
#define D0F2xF4_x50_PDCEntries_OFFSET                           28
#define D0F2xF4_x50_PDCEntries_WIDTH                            4
#define D0F2xF4_x50_PDCEntries_MASK                             0xf0000000

/// D0F2xF4_x50
typedef union {
  struct {                                                              ///<
    UINT32                                        PDCReplacementSel:2 ; ///<
    UINT32                                             Reserved_2_2:1 ; ///<
    UINT32                                          PDCLRUUpdatePri:1 ; ///<
    UINT32                                              PDCParityEn:1 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                       PDCInvalidationSel:2 ; ///<
    UINT32                                        PDCSoftInvalidate:1 ; ///<
    UINT32                                           Reserved_11_11:1 ; ///<
    UINT32                                       PDCSearchDirection:1 ; ///<
    UINT32                                                PDCBypass:1 ; ///<
    UINT32                                           Reserved_14_14:1 ; ///<
    UINT32                                         PDCParitySupport:1 ; ///<
    UINT32                                                  PDCWays:8 ; ///<
    UINT32                                           Reserved_27_24:4 ; ///<
    UINT32                                               PDCEntries:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x50_STRUCT;

// **** D0F2xF4_x51 Register Definition ****
// Address
#define D0F2xF4_x51_ADDRESS                                     0x51

// Type
#define D0F2xF4_x51_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x51_PDCDomainBits_OFFSET                        0
#define D0F2xF4_x51_PDCDomainBits_WIDTH                         6
#define D0F2xF4_x51_PDCDomainBits_MASK                          0x3f
#define D0F2xF4_x51_Reserved_7_6_OFFSET                         6
#define D0F2xF4_x51_Reserved_7_6_WIDTH                          2
#define D0F2xF4_x51_Reserved_7_6_MASK                           0xc0
#define D0F2xF4_x51_PDCLvlHash_OFFSET                           8
#define D0F2xF4_x51_PDCLvlHash_WIDTH                            1
#define D0F2xF4_x51_PDCLvlHash_MASK                             0x100
#define D0F2xF4_x51_PDCUpperLvlAddrHash_OFFSET                  9
#define D0F2xF4_x51_PDCUpperLvlAddrHash_WIDTH                   1
#define D0F2xF4_x51_PDCUpperLvlAddrHash_MASK                    0x200
#define D0F2xF4_x51_PdcAltHashEn_OFFSET                         10
#define D0F2xF4_x51_PdcAltHashEn_WIDTH                          1
#define D0F2xF4_x51_PdcAltHashEn_MASK                           0x400
#define D0F2xF4_x51_Reserved_15_11_OFFSET                       11
#define D0F2xF4_x51_Reserved_15_11_WIDTH                        5
#define D0F2xF4_x51_Reserved_15_11_MASK                         0xf800
#define D0F2xF4_x51_PDCAddressMask_OFFSET                       16
#define D0F2xF4_x51_PDCAddressMask_WIDTH                        16
#define D0F2xF4_x51_PDCAddressMask_MASK                         0xffff0000

/// D0F2xF4_x51
typedef union {
  struct {                                                              ///<
    UINT32                                            PDCDomainBits:6 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                               PDCLvlHash:1 ; ///<
    UINT32                                      PDCUpperLvlAddrHash:1 ; ///<
    UINT32                                             PdcAltHashEn:1 ; ///<
    UINT32                                           Reserved_15_11:5 ; ///<
    UINT32                                           PDCAddressMask:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x51_STRUCT;

// **** D0F2xF4_x52 Register Definition ****
// Address
#define D0F2xF4_x52_ADDRESS                                     0x52

// Type
#define D0F2xF4_x52_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x52_PDCWayDisable_OFFSET                        0
#define D0F2xF4_x52_PDCWayDisable_WIDTH                         16
#define D0F2xF4_x52_PDCWayDisable_MASK                          0xffff
#define D0F2xF4_x52_PDCWayAccessDisable_OFFSET                  16
#define D0F2xF4_x52_PDCWayAccessDisable_WIDTH                   16
#define D0F2xF4_x52_PDCWayAccessDisable_MASK                    0xffff0000

/// D0F2xF4_x52
typedef union {
  struct {                                                              ///<
    UINT32                                            PDCWayDisable:16; ///<
    UINT32                                      PDCWayAccessDisable:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x52_STRUCT;

// **** D0F2xF4_x53 Register Definition ****
// Address
#define D0F2xF4_x53_ADDRESS                                     0x53

// Type
#define D0F2xF4_x53_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x53_L2bUpdateFilterBypass_OFFSET                0
#define D0F2xF4_x53_L2bUpdateFilterBypass_WIDTH                 1
#define D0F2xF4_x53_L2bUpdateFilterBypass_MASK                  0x1
#define D0F2xF4_x53_L2bUpdateFilterRdlatency_OFFSET             1
#define D0F2xF4_x53_L2bUpdateFilterRdlatency_WIDTH              4
#define D0F2xF4_x53_L2bUpdateFilterRdlatency_MASK               0x1e
#define D0F2xF4_x53_Reserved_31_5_OFFSET                        5
#define D0F2xF4_x53_Reserved_31_5_WIDTH                         27
#define D0F2xF4_x53_Reserved_31_5_MASK                          0xffffffe0

/// D0F2xF4_x53
typedef union {
  struct {                                                              ///<
    UINT32                                    L2bUpdateFilterBypass:1 ; ///<
    UINT32                                 L2bUpdateFilterRdlatency:4 ; ///<
    UINT32                                            Reserved_31_5:27; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x53_STRUCT;

// **** D0F2xF4_x54 Register Definition ****
// Address
#define D0F2xF4_x54_ADDRESS                                     0x54

// Type
#define D0F2xF4_x54_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x54_TWQueueLimit_OFFSET                         0
#define D0F2xF4_x54_TWQueueLimit_WIDTH                          6
#define D0F2xF4_x54_TWQueueLimit_MASK                           0x3f
#define D0F2xF4_x54_TWForceCoherent_OFFSET                      6
#define D0F2xF4_x54_TWForceCoherent_WIDTH                       1
#define D0F2xF4_x54_TWForceCoherent_MASK                        0x40
#define D0F2xF4_x54_Reserved_7_7_OFFSET                         7
#define D0F2xF4_x54_Reserved_7_7_WIDTH                          1
#define D0F2xF4_x54_Reserved_7_7_MASK                           0x80
#define D0F2xF4_x54_TWPrefetchEn_OFFSET                         8
#define D0F2xF4_x54_TWPrefetchEn_WIDTH                          1
#define D0F2xF4_x54_TWPrefetchEn_MASK                           0x100
#define D0F2xF4_x54_TWPrefetchOnly4KDis_OFFSET                  9
#define D0F2xF4_x54_TWPrefetchOnly4KDis_WIDTH                   1
#define D0F2xF4_x54_TWPrefetchOnly4KDis_MASK                    0x200
#define D0F2xF4_x54_TWPTEOnUntransExcl_OFFSET                   10
#define D0F2xF4_x54_TWPTEOnUntransExcl_WIDTH                    1
#define D0F2xF4_x54_TWPTEOnUntransExcl_MASK                     0x400
#define D0F2xF4_x54_TWPTEOnAddrTransExcl_OFFSET                 11
#define D0F2xF4_x54_TWPTEOnAddrTransExcl_WIDTH                  1
#define D0F2xF4_x54_TWPTEOnAddrTransExcl_MASK                   0x800
#define D0F2xF4_x54_TWPrefetchRange_OFFSET                      12
#define D0F2xF4_x54_TWPrefetchRange_WIDTH                       3
#define D0F2xF4_x54_TWPrefetchRange_MASK                        0x7000
#define D0F2xF4_x54_Reserved_15_15_OFFSET                       15
#define D0F2xF4_x54_Reserved_15_15_WIDTH                        1
#define D0F2xF4_x54_Reserved_15_15_MASK                         0x8000
#define D0F2xF4_x54_TwfilterDis_OFFSET                          16
#define D0F2xF4_x54_TwfilterDis_WIDTH                           1
#define D0F2xF4_x54_TwfilterDis_MASK                            0x10000
#define D0F2xF4_x54_Twfilter64bDis_OFFSET                       17
#define D0F2xF4_x54_Twfilter64bDis_WIDTH                        1
#define D0F2xF4_x54_Twfilter64bDis_MASK                         0x20000
#define D0F2xF4_x54_Reserved_31_18_OFFSET                       18
#define D0F2xF4_x54_Reserved_31_18_WIDTH                        14
#define D0F2xF4_x54_Reserved_31_18_MASK                         0xfffc0000

/// D0F2xF4_x54
typedef union {
  struct {                                                              ///<
    UINT32                                             TWQueueLimit:6 ; ///<
    UINT32                                          TWForceCoherent:1 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                             TWPrefetchEn:1 ; ///<
    UINT32                                      TWPrefetchOnly4KDis:1 ; ///<
    UINT32                                       TWPTEOnUntransExcl:1 ; ///<
    UINT32                                     TWPTEOnAddrTransExcl:1 ; ///<
    UINT32                                          TWPrefetchRange:3 ; ///<
    UINT32                                           Reserved_15_15:1 ; ///<
    UINT32                                              TwfilterDis:1 ; ///<
    UINT32                                           Twfilter64bDis:1 ; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x54_STRUCT;

// **** D0F2xF4_x56 Register Definition ****
// Address
#define D0F2xF4_x56_ADDRESS                                     0x56

// Type
#define D0F2xF4_x56_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x56_CPPrefetchDis_OFFSET                        0
#define D0F2xF4_x56_CPPrefetchDis_WIDTH                         1
#define D0F2xF4_x56_CPPrefetchDis_MASK                          0x1
#define D0F2xF4_x56_CPFlushOnWait_OFFSET                        1
#define D0F2xF4_x56_CPFlushOnWait_WIDTH                         1
#define D0F2xF4_x56_CPFlushOnWait_MASK                          0x2
#define D0F2xF4_x56_CPFlushOnInv_OFFSET                         2
#define D0F2xF4_x56_CPFlushOnInv_WIDTH                          1
#define D0F2xF4_x56_CPFlushOnInv_MASK                           0x4
#define D0F2xF4_x56_Reserved_15_3_OFFSET                        3
#define D0F2xF4_x56_Reserved_15_3_WIDTH                         13
#define D0F2xF4_x56_Reserved_15_3_MASK                          0xfff8
#define D0F2xF4_x56_CPRdDelay_OFFSET                            16
#define D0F2xF4_x56_CPRdDelay_WIDTH                             16
#define D0F2xF4_x56_CPRdDelay_MASK                              0xffff0000

/// D0F2xF4_x56
typedef union {
  struct {                                                              ///<
    UINT32                                            CPPrefetchDis:1 ; ///<
    UINT32                                            CPFlushOnWait:1 ; ///<
    UINT32                                             CPFlushOnInv:1 ; ///<
    UINT32                                            Reserved_15_3:13; ///<
    UINT32                                                CPRdDelay:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x56_STRUCT;

// **** D0F2xF4_x57 Register Definition ****
// Address
#define D0F2xF4_x57_ADDRESS                                     0x57

// Type
#define D0F2xF4_x57_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x57_L1ImuPcieGfxDis_OFFSET                      0
#define D0F2xF4_x57_L1ImuPcieGfxDis_WIDTH                       1
#define D0F2xF4_x57_L1ImuPcieGfxDis_MASK                        0x1
#define D0F2xF4_x57_Reserved_1_1_OFFSET                         1
#define D0F2xF4_x57_Reserved_1_1_WIDTH                          1
#define D0F2xF4_x57_Reserved_1_1_MASK                           0x2
#define D0F2xF4_x57_L1ImuIntGfxDis_OFFSET                       2
#define D0F2xF4_x57_L1ImuIntGfxDis_WIDTH                        1
#define D0F2xF4_x57_L1ImuIntGfxDis_MASK                         0x4
#define D0F2xF4_x57_Reserved_31_3_OFFSET                        3
#define D0F2xF4_x57_Reserved_31_3_WIDTH                         29
#define D0F2xF4_x57_Reserved_31_3_MASK                          0xfffffff8

/// D0F2xF4_x57
typedef union {
  struct {                                                              ///<
    UINT32                                          L1ImuPcieGfxDis:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                           L1ImuIntGfxDis:1 ; ///<
    UINT32                                            Reserved_31_3:29; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x57_STRUCT;

// **** D0F2xF4_x58 Register Definition ****
// Address
#define D0F2xF4_x58_ADDRESS                                     0x58

// Type
#define D0F2xF4_x58_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x58_IommuL2GuestAddrMask_OFFSET                 0
#define D0F2xF4_x58_IommuL2GuestAddrMask_WIDTH                  24
#define D0F2xF4_x58_IommuL2GuestAddrMask_MASK                   0xffffff
#define D0F2xF4_x58_Reserved_31_24_OFFSET                       24
#define D0F2xF4_x58_Reserved_31_24_WIDTH                        8
#define D0F2xF4_x58_Reserved_31_24_MASK                         0xff000000

/// D0F2xF4_x58
typedef union {
  struct {                                                              ///<
    UINT32                                     IommuL2GuestAddrMask:24; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x58_STRUCT;

// **** D0F2xF4_x60 Register Definition ****
// Address
#define D0F2xF4_x60_ADDRESS                                     0x60

// Type
#define D0F2xF4_x60_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x60_TWDebugEn_OFFSET                            0
#define D0F2xF4_x60_TWDebugEn_WIDTH                             1
#define D0F2xF4_x60_TWDebugEn_MASK                              0x1
#define D0F2xF4_x60_TWDebugNoWrap_OFFSET                        1
#define D0F2xF4_x60_TWDebugNoWrap_WIDTH                         1
#define D0F2xF4_x60_TWDebugNoWrap_MASK                          0x2
#define D0F2xF4_x60_TWDebugForceDisable_OFFSET                  2
#define D0F2xF4_x60_TWDebugForceDisable_WIDTH                   1
#define D0F2xF4_x60_TWDebugForceDisable_MASK                    0x4
#define D0F2xF4_x60_Reserved_14_3_OFFSET                        3
#define D0F2xF4_x60_Reserved_14_3_WIDTH                         12
#define D0F2xF4_x60_Reserved_14_3_MASK                          0x7ff8
#define D0F2xF4_x60_TWDebugMask_OFFSET                          15
#define D0F2xF4_x60_TWDebugMask_WIDTH                           17
#define D0F2xF4_x60_TWDebugMask_MASK                            0xffff8000

/// D0F2xF4_x60
typedef union {
  struct {                                                              ///<
    UINT32                                                TWDebugEn:1 ; ///<
    UINT32                                            TWDebugNoWrap:1 ; ///<
    UINT32                                      TWDebugForceDisable:1 ; ///<
    UINT32                                            Reserved_14_3:12; ///<
    UINT32                                              TWDebugMask:17; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x60_STRUCT;

// **** D0F2xF4_x61 Register Definition ****
// Address
#define D0F2xF4_x61_ADDRESS                                     0x61

// Type
#define D0F2xF4_x61_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x61_Reserved_11_0_OFFSET                        0
#define D0F2xF4_x61_Reserved_11_0_WIDTH                         12
#define D0F2xF4_x61_Reserved_11_0_MASK                          0xfff
#define D0F2xF4_x61_TWDebugAddrLo_OFFSET                        12
#define D0F2xF4_x61_TWDebugAddrLo_WIDTH                         20
#define D0F2xF4_x61_TWDebugAddrLo_MASK                          0xfffff000

/// D0F2xF4_x61
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_11_0:12; ///<
    UINT32                                            TWDebugAddrLo:20; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x61_STRUCT;

// **** D0F2xF4_x62 Register Definition ****
// Address
#define D0F2xF4_x62_ADDRESS                                     0x62

// Type
#define D0F2xF4_x62_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x62_TWDebugAddrHi_OFFSET                        0
#define D0F2xF4_x62_TWDebugAddrHi_WIDTH                         32
#define D0F2xF4_x62_TWDebugAddrHi_MASK                          0xffffffff

/// D0F2xF4_x62
typedef union {
  struct {                                                              ///<
    UINT32                                            TWDebugAddrHi:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x62_STRUCT;

// **** D0F2xF4_x6A Register Definition ****
// Address
#define D0F2xF4_x6A_ADDRESS                                     0x6a

// Type
#define D0F2xF4_x6A_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x6A_IntEventOrderEn_OFFSET                      0
#define D0F2xF4_x6A_IntEventOrderEn_WIDTH                       1
#define D0F2xF4_x6A_IntEventOrderEn_MASK                        0x1
#define D0F2xF4_x6A_IntCPOrderEn_OFFSET                         1
#define D0F2xF4_x6A_IntCPOrderEn_WIDTH                          1
#define D0F2xF4_x6A_IntCPOrderEn_MASK                           0x2
#define D0F2xF4_x6A_IntPPROrderEn_OFFSET                        2
#define D0F2xF4_x6A_IntPPROrderEn_WIDTH                         1
#define D0F2xF4_x6A_IntPPROrderEn_MASK                          0x4
#define D0F2xF4_x6A_Reserved_31_3_OFFSET                        3
#define D0F2xF4_x6A_Reserved_31_3_WIDTH                         29
#define D0F2xF4_x6A_Reserved_31_3_MASK                          0xfffffff8

/// D0F2xF4_x6A
typedef union {
  struct {                                                              ///<
    UINT32                                          IntEventOrderEn:1 ; ///<
    UINT32                                             IntCPOrderEn:1 ; ///<
    UINT32                                            IntPPROrderEn:1 ; ///<
    UINT32                                            Reserved_31_3:29; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x6A_STRUCT;

// **** D0F2xF4_x70 Register Definition ****
// Address
#define D0F2xF4_x70_ADDRESS                                     0x70

// Type
#define D0F2xF4_x70_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x70_FC1Credits_OFFSET                           0
#define D0F2xF4_x70_FC1Credits_WIDTH                            6
#define D0F2xF4_x70_FC1Credits_MASK                             0x3f
#define D0F2xF4_x70_Reserved_6_6_OFFSET                         6
#define D0F2xF4_x70_Reserved_6_6_WIDTH                          1
#define D0F2xF4_x70_Reserved_6_6_MASK                           0x40
#define D0F2xF4_x70_FC1Override_OFFSET                          7
#define D0F2xF4_x70_FC1Override_WIDTH                           1
#define D0F2xF4_x70_FC1Override_MASK                            0x80
#define D0F2xF4_x70_FC2Credits_OFFSET                           8
#define D0F2xF4_x70_FC2Credits_WIDTH                            6
#define D0F2xF4_x70_FC2Credits_MASK                             0x3f00
#define D0F2xF4_x70_Reserved_14_14_OFFSET                       14
#define D0F2xF4_x70_Reserved_14_14_WIDTH                        1
#define D0F2xF4_x70_Reserved_14_14_MASK                         0x4000
#define D0F2xF4_x70_FC2Override_OFFSET                          15
#define D0F2xF4_x70_FC2Override_WIDTH                           1
#define D0F2xF4_x70_FC2Override_MASK                            0x8000
#define D0F2xF4_x70_FC3Credits_OFFSET                           16
#define D0F2xF4_x70_FC3Credits_WIDTH                            6
#define D0F2xF4_x70_FC3Credits_MASK                             0x3f0000
#define D0F2xF4_x70_Reserved_22_22_OFFSET                       22
#define D0F2xF4_x70_Reserved_22_22_WIDTH                        1
#define D0F2xF4_x70_Reserved_22_22_MASK                         0x400000
#define D0F2xF4_x70_FC3Override_OFFSET                          23
#define D0F2xF4_x70_FC3Override_WIDTH                           1
#define D0F2xF4_x70_FC3Override_MASK                            0x800000
#define D0F2xF4_x70_DTECredits_OFFSET                           24
#define D0F2xF4_x70_DTECredits_WIDTH                            6
#define D0F2xF4_x70_DTECredits_MASK                             0x3f000000
#define D0F2xF4_x70_Reserved_30_30_OFFSET                       30
#define D0F2xF4_x70_Reserved_30_30_WIDTH                        1
#define D0F2xF4_x70_Reserved_30_30_MASK                         0x40000000
#define D0F2xF4_x70_DTEOverride_OFFSET                          31
#define D0F2xF4_x70_DTEOverride_WIDTH                           1
#define D0F2xF4_x70_DTEOverride_MASK                            0x80000000

/// D0F2xF4_x70
typedef union {
  struct {                                                              ///<
    UINT32                                               FC1Credits:6 ; ///<
    UINT32                                             Reserved_6_6:1 ; ///<
    UINT32                                              FC1Override:1 ; ///<
    UINT32                                               FC2Credits:6 ; ///<
    UINT32                                           Reserved_14_14:1 ; ///<
    UINT32                                              FC2Override:1 ; ///<
    UINT32                                               FC3Credits:6 ; ///<
    UINT32                                           Reserved_22_22:1 ; ///<
    UINT32                                              FC3Override:1 ; ///<
    UINT32                                               DTECredits:6 ; ///<
    UINT32                                           Reserved_30_30:1 ; ///<
    UINT32                                              DTEOverride:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x70_STRUCT;

// **** D0F2xF4_x71 Register Definition ****
// Address
#define D0F2xF4_x71_ADDRESS                                     0x71

// Type
#define D0F2xF4_x71_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x71_PDTIECredits_OFFSET                         0
#define D0F2xF4_x71_PDTIECredits_WIDTH                          6
#define D0F2xF4_x71_PDTIECredits_MASK                           0x3f
#define D0F2xF4_x71_Reserved_6_6_OFFSET                         6
#define D0F2xF4_x71_Reserved_6_6_WIDTH                          1
#define D0F2xF4_x71_Reserved_6_6_MASK                           0x40
#define D0F2xF4_x71_PDTIEOverride_OFFSET                        7
#define D0F2xF4_x71_PDTIEOverride_WIDTH                         1
#define D0F2xF4_x71_PDTIEOverride_MASK                          0x80
#define D0F2xF4_x71_TWELCredits_OFFSET                          8
#define D0F2xF4_x71_TWELCredits_WIDTH                           6
#define D0F2xF4_x71_TWELCredits_MASK                            0x3f00
#define D0F2xF4_x71_Reserved_14_14_OFFSET                       14
#define D0F2xF4_x71_Reserved_14_14_WIDTH                        1
#define D0F2xF4_x71_Reserved_14_14_MASK                         0x4000
#define D0F2xF4_x71_TWELOverride_OFFSET                         15
#define D0F2xF4_x71_TWELOverride_WIDTH                          1
#define D0F2xF4_x71_TWELOverride_MASK                           0x8000
#define D0F2xF4_x71_CpPrefetchCredits_OFFSET                    16
#define D0F2xF4_x71_CpPrefetchCredits_WIDTH                     4
#define D0F2xF4_x71_CpPrefetchCredits_MASK                      0xf0000
#define D0F2xF4_x71_PprMcifCredits_OFFSET                       20
#define D0F2xF4_x71_PprMcifCredits_WIDTH                        4
#define D0F2xF4_x71_PprMcifCredits_MASK                         0xf00000
#define D0F2xF4_x71_Reserved_31_24_OFFSET                       24
#define D0F2xF4_x71_Reserved_31_24_WIDTH                        8
#define D0F2xF4_x71_Reserved_31_24_MASK                         0xff000000

/// D0F2xF4_x71
typedef union {
  struct {                                                              ///<
    UINT32                                             PDTIECredits:6 ; ///<
    UINT32                                             Reserved_6_6:1 ; ///<
    UINT32                                            PDTIEOverride:1 ; ///<
    UINT32                                              TWELCredits:6 ; ///<
    UINT32                                           Reserved_14_14:1 ; ///<
    UINT32                                             TWELOverride:1 ; ///<
    UINT32                                        CpPrefetchCredits:4 ; ///<
    UINT32                                           PprMcifCredits:4 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x71_STRUCT;

// **** D0F2xF4_x78 Register Definition ****
// Address
#define D0F2xF4_x78_ADDRESS                                     0x78

// Type
#define D0F2xF4_x78_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x78_MCIFBaseReadCredits_OFFSET                  0
#define D0F2xF4_x78_MCIFBaseReadCredits_WIDTH                   5
#define D0F2xF4_x78_MCIFBaseReadCredits_MASK                    0x1f
#define D0F2xF4_x78_Reserved_7_5_OFFSET                         5
#define D0F2xF4_x78_Reserved_7_5_WIDTH                          3
#define D0F2xF4_x78_Reserved_7_5_MASK                           0xe0
#define D0F2xF4_x78_MCIFIsocReadCredits_OFFSET                  8
#define D0F2xF4_x78_MCIFIsocReadCredits_WIDTH                   5
#define D0F2xF4_x78_MCIFIsocReadCredits_MASK                    0x1f00
#define D0F2xF4_x78_Reserved_15_13_OFFSET                       13
#define D0F2xF4_x78_Reserved_15_13_WIDTH                        3
#define D0F2xF4_x78_Reserved_15_13_MASK                         0xe000
#define D0F2xF4_x78_MCIFBaseWriteHdrCredits_OFFSET              16
#define D0F2xF4_x78_MCIFBaseWriteHdrCredits_WIDTH               5
#define D0F2xF4_x78_MCIFBaseWriteHdrCredits_MASK                0x1f0000
#define D0F2xF4_x78_Reserved_23_21_OFFSET                       21
#define D0F2xF4_x78_Reserved_23_21_WIDTH                        3
#define D0F2xF4_x78_Reserved_23_21_MASK                         0xe00000
#define D0F2xF4_x78_MCIFBaseWriteDataCredits_OFFSET             24
#define D0F2xF4_x78_MCIFBaseWriteDataCredits_WIDTH              5
#define D0F2xF4_x78_MCIFBaseWriteDataCredits_MASK               0x1f000000
#define D0F2xF4_x78_Reserved_31_29_OFFSET                       29
#define D0F2xF4_x78_Reserved_31_29_WIDTH                        3
#define D0F2xF4_x78_Reserved_31_29_MASK                         0xe0000000

/// D0F2xF4_x78
typedef union {
  struct {                                                              ///<
    UINT32                                      MCIFBaseReadCredits:5 ; ///<
    UINT32                                             Reserved_7_5:3 ; ///<
    UINT32                                      MCIFIsocReadCredits:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                  MCIFBaseWriteHdrCredits:5 ; ///<
    UINT32                                           Reserved_23_21:3 ; ///<
    UINT32                                 MCIFBaseWriteDataCredits:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x78_STRUCT;







// **** D0F2xF4_x80 Register Definition ****
// Address
#define D0F2xF4_x80_ADDRESS                                     0x80

// Type
#define D0F2xF4_x80_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x80_ERRRuleLock0_OFFSET                         0
#define D0F2xF4_x80_ERRRuleLock0_WIDTH                          1
#define D0F2xF4_x80_ERRRuleLock0_MASK                           0x1
#define D0F2xF4_x80_Reserved_3_1_OFFSET                         1
#define D0F2xF4_x80_Reserved_3_1_WIDTH                          3
#define D0F2xF4_x80_Reserved_3_1_MASK                           0xe
#define D0F2xF4_x80_ERRRuleDisable0_OFFSET                      4
#define D0F2xF4_x80_ERRRuleDisable0_WIDTH                       28
#define D0F2xF4_x80_ERRRuleDisable0_MASK                        0xfffffff0

/// D0F2xF4_x80
typedef union {
  struct {                                                              ///<
    UINT32                                             ERRRuleLock0:1 ; ///<
    UINT32                                             Reserved_3_1:3 ; ///<
    UINT32                                          ERRRuleDisable0:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x80_STRUCT;

// **** D0F2xF4_x81 Register Definition ****
// Address
#define D0F2xF4_x81_ADDRESS                                     0x81

// Type
#define D0F2xF4_x81_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x81_ERRRuleDisable1_OFFSET                      0
#define D0F2xF4_x81_ERRRuleDisable1_WIDTH                       32
#define D0F2xF4_x81_ERRRuleDisable1_MASK                        0xffffffff

/// D0F2xF4_x81
typedef union {
  struct {                                                              ///<
    UINT32                                          ERRRuleDisable1:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x81_STRUCT;

// **** D0F2xF4_x82 Register Definition ****
// Address
#define D0F2xF4_x82_ADDRESS                                     0x82

// Type
#define D0F2xF4_x82_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x82_ERRRuleDisable2_OFFSET                      0
#define D0F2xF4_x82_ERRRuleDisable2_WIDTH                       32
#define D0F2xF4_x82_ERRRuleDisable2_MASK                        0xffffffff

/// D0F2xF4_x82
typedef union {
  struct {                                                              ///<
    UINT32                                          ERRRuleDisable2:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x82_STRUCT;

// **** D0F2xF4_x90 Register Definition ****
// Address
#define D0F2xF4_x90_ADDRESS                                     0x90

// Type
#define D0F2xF4_x90_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x90_CKGateL2BRegsDisable_OFFSET                 0
#define D0F2xF4_x90_CKGateL2BRegsDisable_WIDTH                  1
#define D0F2xF4_x90_CKGateL2BRegsDisable_MASK                   0x1
#define D0F2xF4_x90_CKGateL2BDynamicDisable_OFFSET              1
#define D0F2xF4_x90_CKGateL2BDynamicDisable_WIDTH               1
#define D0F2xF4_x90_CKGateL2BDynamicDisable_MASK                0x2
#define D0F2xF4_x90_CKGateL2BMiscDisable_OFFSET                 2
#define D0F2xF4_x90_CKGateL2BMiscDisable_WIDTH                  1
#define D0F2xF4_x90_CKGateL2BMiscDisable_MASK                   0x4
#define D0F2xF4_x90_CKGateL2BCacheDisable_OFFSET                3
#define D0F2xF4_x90_CKGateL2BCacheDisable_WIDTH                 1
#define D0F2xF4_x90_CKGateL2BCacheDisable_MASK                  0x8
#define D0F2xF4_x90_CKGateL2BLength_OFFSET                      4
#define D0F2xF4_x90_CKGateL2BLength_WIDTH                       2
#define D0F2xF4_x90_CKGateL2BLength_MASK                        0x30
#define D0F2xF4_x90_CKGateL2BStop_OFFSET                        6
#define D0F2xF4_x90_CKGateL2BStop_WIDTH                         2
#define D0F2xF4_x90_CKGateL2BStop_MASK                          0xc0
#define D0F2xF4_x90_Reserved_31_8_OFFSET                        8
#define D0F2xF4_x90_Reserved_31_8_WIDTH                         24
#define D0F2xF4_x90_Reserved_31_8_MASK                          0xffffff00

/// D0F2xF4_x90
typedef union {
  struct {                                                              ///<
    UINT32                                     CKGateL2BRegsDisable:1 ; ///<
    UINT32                                  CKGateL2BDynamicDisable:1 ; ///<
    UINT32                                     CKGateL2BMiscDisable:1 ; ///<
    UINT32                                    CKGateL2BCacheDisable:1 ; ///<
    UINT32                                          CKGateL2BLength:2 ; ///<
    UINT32                                            CKGateL2BStop:2 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x90_STRUCT;

// **** D0F2xF4_x92 Register Definition ****
// Address
#define D0F2xF4_x92_ADDRESS                                     0x92

// Type
#define D0F2xF4_x92_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x92_PprInttimedelay_OFFSET                      0
#define D0F2xF4_x92_PprInttimedelay_WIDTH                       8
#define D0F2xF4_x92_PprInttimedelay_MASK                        0xff
#define D0F2xF4_x92_PprIntreqdelay_OFFSET                       8
#define D0F2xF4_x92_PprIntreqdelay_WIDTH                        8
#define D0F2xF4_x92_PprIntreqdelay_MASK                         0xff00
#define D0F2xF4_x92_PprIntcoallesceEn_OFFSET                    16
#define D0F2xF4_x92_PprIntcoallesceEn_WIDTH                     1
#define D0F2xF4_x92_PprIntcoallesceEn_MASK                      0x10000
#define D0F2xF4_x92_Reserved_31_17_OFFSET                       17
#define D0F2xF4_x92_Reserved_31_17_WIDTH                        15
#define D0F2xF4_x92_Reserved_31_17_MASK                         0xfffe0000

/// D0F2xF4_x92
typedef union {
  struct {                                                              ///<
    UINT32                                          PprInttimedelay:8 ; ///<
    UINT32                                           PprIntreqdelay:8 ; ///<
    UINT32                                        PprIntcoallesceEn:1 ; ///<
    UINT32                                           Reserved_31_17:15; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x92_STRUCT;

// **** D0F2xF4_x94 Register Definition ****
// Address
#define D0F2xF4_x94_ADDRESS                                     0x94

// Type
#define D0F2xF4_x94_TYPE                                        TYPE_D0F2xF4
// Field Data
#define D0F2xF4_x94_L2bregGstPgsize_OFFSET                      0
#define D0F2xF4_x94_L2bregGstPgsize_WIDTH                       2
#define D0F2xF4_x94_L2bregGstPgsize_MASK                        0x3
#define D0F2xF4_x94_L2bregHostPgsize_OFFSET                     2
#define D0F2xF4_x94_L2bregHostPgsize_WIDTH                      2
#define D0F2xF4_x94_L2bregHostPgsize_MASK                       0xc
#define D0F2xF4_x94_Reserved_31_4_OFFSET                        4
#define D0F2xF4_x94_Reserved_31_4_WIDTH                         28
#define D0F2xF4_x94_Reserved_31_4_MASK                          0xfffffff0

/// D0F2xF4_x94
typedef union {
  struct {                                                              ///<
    UINT32                                          L2bregGstPgsize:2 ; ///<
    UINT32                                         L2bregHostPgsize:2 ; ///<
    UINT32                                            Reserved_31_4:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xF4_x94_STRUCT;

// **** D0F2xFC_x32_L1 Register Definition ****
// Address
#define D0F2xFC_x32_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x32)

// Type
#define D0F2xFC_x32_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET                 0
#define D0F2xFC_x32_L1_AtsMultipleRespEn_WIDTH                  1
#define D0F2xFC_x32_L1_AtsMultipleRespEn_MASK                   0x1
#define D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET               1
#define D0F2xFC_x32_L1_AtsMultipleL1toL2En_WIDTH                1
#define D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK                 0x2
#define D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET                 2
#define D0F2xFC_x32_L1_TimeoutPulseExtEn_WIDTH                  1
#define D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK                   0x4
#define D0F2xFC_x32_L1_TlpprefixerrEn_OFFSET                    3
#define D0F2xFC_x32_L1_TlpprefixerrEn_WIDTH                     1
#define D0F2xFC_x32_L1_TlpprefixerrEn_MASK                      0x8
#define D0F2xFC_x32_L1_Reserved_31_4_OFFSET                     4
#define D0F2xFC_x32_L1_Reserved_31_4_WIDTH                      28
#define D0F2xFC_x32_L1_Reserved_31_4_MASK                       0xfffffff0

/// D0F2xFC_x32_L1
typedef union {
  struct {                                                              ///<
    UINT32                                        AtsMultipleRespEn:1 ; ///<
    UINT32                                      AtsMultipleL1toL2En:1 ; ///<
    UINT32                                        TimeoutPulseExtEn:1 ; ///<
    UINT32                                           TlpprefixerrEn:1 ; ///<
    UINT32                                            Reserved_31_4:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x32_L1_STRUCT;

// **** D0F2xFC_x11_L1 Register Definition ****
// Address
#define D0F2xFC_x11_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x11)

// Type
#define D0F2xFC_x11_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x11_L1_L1cachelinedis0_OFFSET                   0
#define D0F2xFC_x11_L1_L1cachelinedis0_WIDTH                    6
#define D0F2xFC_x11_L1_L1cachelinedis0_MASK                     0x3f
#define D0F2xFC_x11_L1_Reserved_7_6_OFFSET                      6
#define D0F2xFC_x11_L1_Reserved_7_6_WIDTH                       2
#define D0F2xFC_x11_L1_Reserved_7_6_MASK                        0xc0
#define D0F2xFC_x11_L1_L1cachelinedis1_OFFSET                   8
#define D0F2xFC_x11_L1_L1cachelinedis1_WIDTH                    6
#define D0F2xFC_x11_L1_L1cachelinedis1_MASK                     0x3f00
#define D0F2xFC_x11_L1_Reserved_31_14_OFFSET                    14
#define D0F2xFC_x11_L1_Reserved_31_14_WIDTH                     18
#define D0F2xFC_x11_L1_Reserved_31_14_MASK                      0xffffc000

/// D0F2xFC_x11_L1
typedef union {
  struct {                                                              ///<
    UINT32                                          L1cachelinedis0:6 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                          L1cachelinedis1:6 ; ///<
    UINT32                                           Reserved_31_14:18; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x11_L1_STRUCT;

// **** D0F2xFC_x34_L1 Register Definition ****
// Address
#define D0F2xFC_x34_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x34)

// Type
#define D0F2xFC_x34_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x34_L1_L1MempwrEn_OFFSET                        0
#define D0F2xFC_x34_L1_L1MempwrEn_WIDTH                         1
#define D0F2xFC_x34_L1_L1MempwrEn_MASK                          0x1
#define D0F2xFC_x34_L1_Reserved_7_1_OFFSET                      1
#define D0F2xFC_x34_L1_Reserved_7_1_WIDTH                       7
#define D0F2xFC_x34_L1_Reserved_7_1_MASK                        0xfe
#define D0F2xFC_x34_L1_L1MempwrTimer0_OFFSET                    8
#define D0F2xFC_x34_L1_L1MempwrTimer0_WIDTH                     8
#define D0F2xFC_x34_L1_L1MempwrTimer0_MASK                      0xff00
#define D0F2xFC_x34_L1_L1MempwrTimer1_OFFSET                    16
#define D0F2xFC_x34_L1_L1MempwrTimer1_WIDTH                     8
#define D0F2xFC_x34_L1_L1MempwrTimer1_MASK                      0xff0000
#define D0F2xFC_x34_L1_L1MempwrTimer2_OFFSET                    24
#define D0F2xFC_x34_L1_L1MempwrTimer2_WIDTH                     8
#define D0F2xFC_x34_L1_L1MempwrTimer2_MASK                      0xff000000

/// D0F2xFC_x34_L1
typedef union {
  struct {                                                              ///<
    UINT32                                               L1MempwrEn:1 ; ///<
    UINT32                                             Reserved_7_1:7 ; ///<
    UINT32                                           L1MempwrTimer0:8 ; ///<
    UINT32                                           L1MempwrTimer1:8 ; ///<
    UINT32                                           L1MempwrTimer2:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x34_L1_STRUCT;

// **** D0F2xFC_x0F_L1 Register Definition ****
// Address
#define D0F2xFC_x0F_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x0F)

// Type
#define D0F2xFC_x0F_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x0F_L1_AtsTlbinvPulseWidth_OFFSET               0
#define D0F2xFC_x0F_L1_AtsTlbinvPulseWidth_WIDTH                32
#define D0F2xFC_x0F_L1_AtsTlbinvPulseWidth_MASK                 0xffffffff

/// D0F2xFC_x0F_L1
typedef union {
  struct {                                                              ///<
    UINT32                                      AtsTlbinvPulseWidth:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x0F_L1_STRUCT;

// **** D0F2xFC_x0E_L1 Register Definition ****
// Address
#define D0F2xFC_x0E_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x0E)

// Type
#define D0F2xFC_x0E_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x0E_L1_Reserved_0_0_OFFSET                      0
#define D0F2xFC_x0E_L1_Reserved_0_0_WIDTH                       1
#define D0F2xFC_x0E_L1_Reserved_0_0_MASK                        0x1
#define D0F2xFC_x0E_L1_MsiToHtRemapDis_OFFSET                   1
#define D0F2xFC_x0E_L1_MsiToHtRemapDis_WIDTH                    1
#define D0F2xFC_x0E_L1_MsiToHtRemapDis_MASK                     0x2
#define D0F2xFC_x0E_L1_L1AbrtAtsDis_OFFSET                      2
#define D0F2xFC_x0E_L1_L1AbrtAtsDis_WIDTH                       1
#define D0F2xFC_x0E_L1_L1AbrtAtsDis_MASK                        0x4
#define D0F2xFC_x0E_L1_Reserved_5_3_OFFSET                      3
#define D0F2xFC_x0E_L1_Reserved_5_3_WIDTH                       3
#define D0F2xFC_x0E_L1_Reserved_5_3_MASK                        0x38
#define D0F2xFC_x0E_L1_MsiHtRsvIntMt_OFFSET                     6
#define D0F2xFC_x0E_L1_MsiHtRsvIntMt_WIDTH                      3
#define D0F2xFC_x0E_L1_MsiHtRsvIntMt_MASK                       0x1c0
#define D0F2xFC_x0E_L1_MsiHtRsvIntRqEio_OFFSET                  9
#define D0F2xFC_x0E_L1_MsiHtRsvIntRqEio_WIDTH                   1
#define D0F2xFC_x0E_L1_MsiHtRsvIntRqEio_MASK                    0x200
#define D0F2xFC_x0E_L1_MsiHtRsvIntDM_OFFSET                     10
#define D0F2xFC_x0E_L1_MsiHtRsvIntDM_WIDTH                      1
#define D0F2xFC_x0E_L1_MsiHtRsvIntDM_MASK                       0x400
#define D0F2xFC_x0E_L1_Reserved_11_11_OFFSET                    11
#define D0F2xFC_x0E_L1_Reserved_11_11_WIDTH                     1
#define D0F2xFC_x0E_L1_Reserved_11_11_MASK                      0x800
#define D0F2xFC_x0E_L1_MsiHtRsvIntDestination_OFFSET            12
#define D0F2xFC_x0E_L1_MsiHtRsvIntDestination_WIDTH             8
#define D0F2xFC_x0E_L1_MsiHtRsvIntDestination_MASK              0xff000
#define D0F2xFC_x0E_L1_MsiHtRsvIntVector_OFFSET                 20
#define D0F2xFC_x0E_L1_MsiHtRsvIntVector_WIDTH                  8
#define D0F2xFC_x0E_L1_MsiHtRsvIntVector_MASK                   0xff00000
#define D0F2xFC_x0E_L1_Reserved_31_28_OFFSET                    28
#define D0F2xFC_x0E_L1_Reserved_31_28_WIDTH                     4
#define D0F2xFC_x0E_L1_Reserved_31_28_MASK                      0xf0000000

/// D0F2xFC_x0E_L1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                          MsiToHtRemapDis:1 ; ///<
    UINT32                                             L1AbrtAtsDis:1 ; ///<
    UINT32                                             Reserved_5_3:3 ; ///<
    UINT32                                            MsiHtRsvIntMt:3 ; ///<
    UINT32                                         MsiHtRsvIntRqEio:1 ; ///<
    UINT32                                            MsiHtRsvIntDM:1 ; ///<
    UINT32                                           Reserved_11_11:1 ; ///<
    UINT32                                   MsiHtRsvIntDestination:8 ; ///<
    UINT32                                        MsiHtRsvIntVector:8 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x0E_L1_STRUCT;


// **** D0F2xFC_x37_L1 Register Definition ****
// Address
#define D0F2xFC_x37_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x37)

// Type
#define D0F2xFC_x37_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x37_L1_L1EfrSup_OFFSET                          0
#define D0F2xFC_x37_L1_L1EfrSup_WIDTH                           1
#define D0F2xFC_x37_L1_L1EfrSup_MASK                            0x1
#define D0F2xFC_x37_L1_L1PprSup_OFFSET                          1
#define D0F2xFC_x37_L1_L1PprSup_WIDTH                           1
#define D0F2xFC_x37_L1_L1PprSup_MASK                            0x2
#define D0F2xFC_x37_L1_Reserved_31_2_OFFSET                     2
#define D0F2xFC_x37_L1_Reserved_31_2_WIDTH                      30
#define D0F2xFC_x37_L1_Reserved_31_2_MASK                       0xfffffffc

/// D0F2xFC_x37_L1
typedef union {
  struct {                                                              ///<
    UINT32                                                 L1EfrSup:1 ; ///<
    UINT32                                                 L1PprSup:1 ; ///<
    UINT32                                            Reserved_31_2:30; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x37_L1_STRUCT;


// **** D0F2xFC_x20_L1 Register Definition ****
// Address
#define D0F2xFC_x20_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x20)

// Type
#define D0F2xFC_x20_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x20_L1_EntryStatus0_OFFSET                      0
#define D0F2xFC_x20_L1_EntryStatus0_WIDTH                       3
#define D0F2xFC_x20_L1_EntryStatus0_MASK                        0x7
#define D0F2xFC_x20_L1_EntryStatus1_OFFSET                      3
#define D0F2xFC_x20_L1_EntryStatus1_WIDTH                       3
#define D0F2xFC_x20_L1_EntryStatus1_MASK                        0x38
#define D0F2xFC_x20_L1_EntryStatus2_OFFSET                      6
#define D0F2xFC_x20_L1_EntryStatus2_WIDTH                       3
#define D0F2xFC_x20_L1_EntryStatus2_MASK                        0x1c0
#define D0F2xFC_x20_L1_EntryStatus3_OFFSET                      9
#define D0F2xFC_x20_L1_EntryStatus3_WIDTH                       3
#define D0F2xFC_x20_L1_EntryStatus3_MASK                        0xe00
#define D0F2xFC_x20_L1_EntryStatus4_OFFSET                      12
#define D0F2xFC_x20_L1_EntryStatus4_WIDTH                       3
#define D0F2xFC_x20_L1_EntryStatus4_MASK                        0x7000
#define D0F2xFC_x20_L1_EntryStatus5_OFFSET                      15
#define D0F2xFC_x20_L1_EntryStatus5_WIDTH                       3
#define D0F2xFC_x20_L1_EntryStatus5_MASK                        0x38000
#define D0F2xFC_x20_L1_EntryStatus6_OFFSET                      18
#define D0F2xFC_x20_L1_EntryStatus6_WIDTH                       3
#define D0F2xFC_x20_L1_EntryStatus6_MASK                        0x1c0000
#define D0F2xFC_x20_L1_EntryStatus7_OFFSET                      21
#define D0F2xFC_x20_L1_EntryStatus7_WIDTH                       3
#define D0F2xFC_x20_L1_EntryStatus7_MASK                        0xe00000
#define D0F2xFC_x20_L1_EntryStatus8_OFFSET                      24
#define D0F2xFC_x20_L1_EntryStatus8_WIDTH                       3
#define D0F2xFC_x20_L1_EntryStatus8_MASK                        0x7000000
#define D0F2xFC_x20_L1_EntryStatus9_OFFSET                      27
#define D0F2xFC_x20_L1_EntryStatus9_WIDTH                       3
#define D0F2xFC_x20_L1_EntryStatus9_MASK                        0x38000000
#define D0F2xFC_x20_L1_Reserved_31_30_OFFSET                    30
#define D0F2xFC_x20_L1_Reserved_31_30_WIDTH                     2
#define D0F2xFC_x20_L1_Reserved_31_30_MASK                      0xc0000000

/// D0F2xFC_x20_L1
typedef union {
  struct {                                                              ///<
    UINT32                                             EntryStatus0:3 ; ///<
    UINT32                                             EntryStatus1:3 ; ///<
    UINT32                                             EntryStatus2:3 ; ///<
    UINT32                                             EntryStatus3:3 ; ///<
    UINT32                                             EntryStatus4:3 ; ///<
    UINT32                                             EntryStatus5:3 ; ///<
    UINT32                                             EntryStatus6:3 ; ///<
    UINT32                                             EntryStatus7:3 ; ///<
    UINT32                                             EntryStatus8:3 ; ///<
    UINT32                                             EntryStatus9:3 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x20_L1_STRUCT;

// **** D0F2xFC_x35_L1 Register Definition ****
// Address
#define D0F2xFC_x35_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x35)

// Type
#define D0F2xFC_x35_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x35_L1_L1MempwrTimer3_OFFSET                    0
#define D0F2xFC_x35_L1_L1MempwrTimer3_WIDTH                     8
#define D0F2xFC_x35_L1_L1MempwrTimer3_MASK                      0xff
#define D0F2xFC_x35_L1_Reserved_31_8_OFFSET                     8
#define D0F2xFC_x35_L1_Reserved_31_8_WIDTH                      24
#define D0F2xFC_x35_L1_Reserved_31_8_MASK                       0xffffff00

/// D0F2xFC_x35_L1
typedef union {
  struct {                                                              ///<
    UINT32                                           L1MempwrTimer3:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x35_L1_STRUCT;


// **** D0F2xFC_x0C_L1 Register Definition ****
// Address
#define D0F2xFC_x0C_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x0C)

// Type
#define D0F2xFC_x0C_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x0C_L1_UnfilterDis_OFFSET                       0
#define D0F2xFC_x0C_L1_UnfilterDis_WIDTH                        1
#define D0F2xFC_x0C_L1_UnfilterDis_MASK                         0x1
#define D0F2xFC_x0C_L1_FragmentDis_OFFSET                       1
#define D0F2xFC_x0C_L1_FragmentDis_WIDTH                        1
#define D0F2xFC_x0C_L1_FragmentDis_MASK                         0x2
#define D0F2xFC_x0C_L1_CacheirOnly_OFFSET                       2
#define D0F2xFC_x0C_L1_CacheirOnly_WIDTH                        1
#define D0F2xFC_x0C_L1_CacheirOnly_MASK                         0x4
#define D0F2xFC_x0C_L1_CacheiwOnly_OFFSET                       3
#define D0F2xFC_x0C_L1_CacheiwOnly_WIDTH                        1
#define D0F2xFC_x0C_L1_CacheiwOnly_MASK                         0x8
#define D0F2xFC_x0C_L1_Reserved0_OFFSET                         4
#define D0F2xFC_x0C_L1_Reserved0_WIDTH                          1
#define D0F2xFC_x0C_L1_Reserved0_MASK                           0x10
#define D0F2xFC_x0C_L1_ReplacementSel_OFFSET                    5
#define D0F2xFC_x0C_L1_ReplacementSel_WIDTH                     1
#define D0F2xFC_x0C_L1_ReplacementSel_MASK                      0x20
#define D0F2xFC_x0C_L1_Reserved_7_6_OFFSET                      6
#define D0F2xFC_x0C_L1_Reserved_7_6_WIDTH                       2
#define D0F2xFC_x0C_L1_Reserved_7_6_MASK                        0xc0
#define D0F2xFC_x0C_L1_L2Credits_OFFSET                         8
#define D0F2xFC_x0C_L1_L2Credits_WIDTH                          6
#define D0F2xFC_x0C_L1_L2Credits_MASK                           0x3f00
#define D0F2xFC_x0C_L1_Reserved1_OFFSET                         14
#define D0F2xFC_x0C_L1_Reserved1_WIDTH                          6
#define D0F2xFC_x0C_L1_Reserved1_MASK                           0xfc000
#define D0F2xFC_x0C_L1_L1Banks_OFFSET                           20
#define D0F2xFC_x0C_L1_L1Banks_WIDTH                            2
#define D0F2xFC_x0C_L1_L1Banks_MASK                             0x300000
#define D0F2xFC_x0C_L1_Reserved_23_22_OFFSET                    22
#define D0F2xFC_x0C_L1_Reserved_23_22_WIDTH                     2
#define D0F2xFC_x0C_L1_Reserved_23_22_MASK                      0xc00000
#define D0F2xFC_x0C_L1_L1Entries_OFFSET                         24
#define D0F2xFC_x0C_L1_L1Entries_WIDTH                          4
#define D0F2xFC_x0C_L1_L1Entries_MASK                           0xf000000
#define D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET                 28
#define D0F2xFC_x0C_L1_L1VirtOrderQueues_WIDTH                  3
#define D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK                   0x70000000
#define D0F2xFC_x0C_L1_Reserved_31_31_OFFSET                    31
#define D0F2xFC_x0C_L1_Reserved_31_31_WIDTH                     1
#define D0F2xFC_x0C_L1_Reserved_31_31_MASK                      0x80000000

/// D0F2xFC_x0C_L1
typedef union {
  struct {                                                              ///<
    UINT32                                              UnfilterDis:1 ; ///<
    UINT32                                              FragmentDis:1 ; ///<
    UINT32                                              CacheirOnly:1 ; ///<
    UINT32                                              CacheiwOnly:1 ; ///<
    UINT32                                                Reserved0:1 ; ///<
    UINT32                                           ReplacementSel:1 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                                L2Credits:6 ; ///<
    UINT32                                                Reserved1:6 ; ///<
    UINT32                                                  L1Banks:2 ; ///<
    UINT32                                           Reserved_23_22:2 ; ///<
    UINT32                                                L1Entries:4 ; ///<
    UINT32                                        L1VirtOrderQueues:3 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x0C_L1_STRUCT;


// **** D0F2xFC_x08_L1 Register Definition ****
// Address
#define D0F2xFC_x08_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x08)

// Type
#define D0F2xFC_x08_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x08_L1_L1debugStatus_OFFSET                     0
#define D0F2xFC_x08_L1_L1debugStatus_WIDTH                      32
#define D0F2xFC_x08_L1_L1debugStatus_MASK                       0xffffffff

/// D0F2xFC_x08_L1
typedef union {
  struct {                                                              ///<
    UINT32                                            L1debugStatus:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x08_L1_STRUCT;


// **** D0F2xFC_x10_L1 Register Definition ****
// Address
#define D0F2xFC_x10_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x10)

// Type
#define D0F2xFC_x10_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x10_L1_L1cachebanksel0_OFFSET                   0
#define D0F2xFC_x10_L1_L1cachebanksel0_WIDTH                    16
#define D0F2xFC_x10_L1_L1cachebanksel0_MASK                     0xffff
#define D0F2xFC_x10_L1_Reserved_31_16_OFFSET                    16
#define D0F2xFC_x10_L1_Reserved_31_16_WIDTH                     16
#define D0F2xFC_x10_L1_Reserved_31_16_MASK                      0xffff0000

/// D0F2xFC_x10_L1
typedef union {
  struct {                                                              ///<
    UINT32                                          L1cachebanksel0:16; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x10_L1_STRUCT;

// **** D0F2xFC_x23_L1 Register Definition ****
// Address
#define D0F2xFC_x23_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x23)

// Type
#define D0F2xFC_x23_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x23_L1_EntryStatus30_OFFSET                     0
#define D0F2xFC_x23_L1_EntryStatus30_WIDTH                      3
#define D0F2xFC_x23_L1_EntryStatus30_MASK                       0x7
#define D0F2xFC_x23_L1_EntryStatus31_OFFSET                     3
#define D0F2xFC_x23_L1_EntryStatus31_WIDTH                      3
#define D0F2xFC_x23_L1_EntryStatus31_MASK                       0x38
#define D0F2xFC_x23_L1_Reserved_7_6_OFFSET                      6
#define D0F2xFC_x23_L1_Reserved_7_6_WIDTH                       2
#define D0F2xFC_x23_L1_Reserved_7_6_MASK                        0xc0
#define D0F2xFC_x23_L1_InvalidationStatus_OFFSET                8
#define D0F2xFC_x23_L1_InvalidationStatus_WIDTH                 8
#define D0F2xFC_x23_L1_InvalidationStatus_MASK                  0xff00
#define D0F2xFC_x23_L1_Reserved_31_16_OFFSET                    16
#define D0F2xFC_x23_L1_Reserved_31_16_WIDTH                     16
#define D0F2xFC_x23_L1_Reserved_31_16_MASK                      0xffff0000

/// D0F2xFC_x23_L1
typedef union {
  struct {                                                              ///<
    UINT32                                            EntryStatus30:3 ; ///<
    UINT32                                            EntryStatus31:3 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                       InvalidationStatus:8 ; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x23_L1_STRUCT;

// **** D0F2xFC_x22_L1 Register Definition ****
// Address
#define D0F2xFC_x22_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x22)

// Type
#define D0F2xFC_x22_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x22_L1_EntryStatus20_OFFSET                     0
#define D0F2xFC_x22_L1_EntryStatus20_WIDTH                      3
#define D0F2xFC_x22_L1_EntryStatus20_MASK                       0x7
#define D0F2xFC_x22_L1_EntryStatus21_OFFSET                     3
#define D0F2xFC_x22_L1_EntryStatus21_WIDTH                      3
#define D0F2xFC_x22_L1_EntryStatus21_MASK                       0x38
#define D0F2xFC_x22_L1_EntryStatus22_OFFSET                     6
#define D0F2xFC_x22_L1_EntryStatus22_WIDTH                      3
#define D0F2xFC_x22_L1_EntryStatus22_MASK                       0x1c0
#define D0F2xFC_x22_L1_EntryStatus23_OFFSET                     9
#define D0F2xFC_x22_L1_EntryStatus23_WIDTH                      3
#define D0F2xFC_x22_L1_EntryStatus23_MASK                       0xe00
#define D0F2xFC_x22_L1_EntryStatus24_OFFSET                     12
#define D0F2xFC_x22_L1_EntryStatus24_WIDTH                      3
#define D0F2xFC_x22_L1_EntryStatus24_MASK                       0x7000
#define D0F2xFC_x22_L1_EntryStatus25_OFFSET                     15
#define D0F2xFC_x22_L1_EntryStatus25_WIDTH                      3
#define D0F2xFC_x22_L1_EntryStatus25_MASK                       0x38000
#define D0F2xFC_x22_L1_EntryStatus26_OFFSET                     18
#define D0F2xFC_x22_L1_EntryStatus26_WIDTH                      3
#define D0F2xFC_x22_L1_EntryStatus26_MASK                       0x1c0000
#define D0F2xFC_x22_L1_EntryStatus27_OFFSET                     21
#define D0F2xFC_x22_L1_EntryStatus27_WIDTH                      3
#define D0F2xFC_x22_L1_EntryStatus27_MASK                       0xe00000
#define D0F2xFC_x22_L1_EntryStatus28_OFFSET                     24
#define D0F2xFC_x22_L1_EntryStatus28_WIDTH                      3
#define D0F2xFC_x22_L1_EntryStatus28_MASK                       0x7000000
#define D0F2xFC_x22_L1_EntryStatus29_OFFSET                     27
#define D0F2xFC_x22_L1_EntryStatus29_WIDTH                      3
#define D0F2xFC_x22_L1_EntryStatus29_MASK                       0x38000000
#define D0F2xFC_x22_L1_Reserved_31_30_OFFSET                    30
#define D0F2xFC_x22_L1_Reserved_31_30_WIDTH                     2
#define D0F2xFC_x22_L1_Reserved_31_30_MASK                      0xc0000000

/// D0F2xFC_x22_L1
typedef union {
  struct {                                                              ///<
    UINT32                                            EntryStatus20:3 ; ///<
    UINT32                                            EntryStatus21:3 ; ///<
    UINT32                                            EntryStatus22:3 ; ///<
    UINT32                                            EntryStatus23:3 ; ///<
    UINT32                                            EntryStatus24:3 ; ///<
    UINT32                                            EntryStatus25:3 ; ///<
    UINT32                                            EntryStatus26:3 ; ///<
    UINT32                                            EntryStatus27:3 ; ///<
    UINT32                                            EntryStatus28:3 ; ///<
    UINT32                                            EntryStatus29:3 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x22_L1_STRUCT;

// **** D0F2xFC_x01_L1 Register Definition ****
// Address
#define D0F2xFC_x01_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x01)

// Type
#define D0F2xFC_x01_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x01_L1_L1PerfCount0_OFFSET                      0
#define D0F2xFC_x01_L1_L1PerfCount0_WIDTH                       32
#define D0F2xFC_x01_L1_L1PerfCount0_MASK                        0xffffffff

/// D0F2xFC_x01_L1
typedef union {
  struct {                                                              ///<
    UINT32                                             L1PerfCount0:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x01_L1_STRUCT;

// **** D0F2xFC_x36_L1 Register Definition ****
// Address
#define D0F2xFC_x36_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x36)

// Type
#define D0F2xFC_x36_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x36_L1_L1CanonicalErrEn_OFFSET                  0
#define D0F2xFC_x36_L1_L1CanonicalErrEn_WIDTH                   1
#define D0F2xFC_x36_L1_L1CanonicalErrEn_MASK                    0x1
#define D0F2xFC_x36_L1_Reserved_7_1_OFFSET                      1
#define D0F2xFC_x36_L1_Reserved_7_1_WIDTH                       7
#define D0F2xFC_x36_L1_Reserved_7_1_MASK                        0xfe
#define D0F2xFC_x36_L1_L1GuestAddrMsk_OFFSET                    8
#define D0F2xFC_x36_L1_L1GuestAddrMsk_WIDTH                     24
#define D0F2xFC_x36_L1_L1GuestAddrMsk_MASK                      0xffffff00

/// D0F2xFC_x36_L1
typedef union {
  struct {                                                              ///<
    UINT32                                         L1CanonicalErrEn:1 ; ///<
    UINT32                                             Reserved_7_1:7 ; ///<
    UINT32                                           L1GuestAddrMsk:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x36_L1_STRUCT;

// **** D0F2xFC_x0D_L1 Register Definition ****
// Address
#define D0F2xFC_x0D_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x0D)

// Type
#define D0F2xFC_x0D_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x0D_L1_VOQPortBits_OFFSET                       0
#define D0F2xFC_x0D_L1_VOQPortBits_WIDTH                        3
#define D0F2xFC_x0D_L1_VOQPortBits_MASK                         0x7
#define D0F2xFC_x0D_L1_Reserved_3_3_OFFSET                      3
#define D0F2xFC_x0D_L1_Reserved_3_3_WIDTH                       1
#define D0F2xFC_x0D_L1_Reserved_3_3_MASK                        0x8
#define D0F2xFC_x0D_L1_VOQFuncBits_OFFSET                       4
#define D0F2xFC_x0D_L1_VOQFuncBits_WIDTH                        3
#define D0F2xFC_x0D_L1_VOQFuncBits_MASK                         0x70
#define D0F2xFC_x0D_L1_Reserved_7_7_OFFSET                      7
#define D0F2xFC_x0D_L1_Reserved_7_7_WIDTH                       1
#define D0F2xFC_x0D_L1_Reserved_7_7_MASK                        0x80
#define D0F2xFC_x0D_L1_VOQXorMode_OFFSET                        8
#define D0F2xFC_x0D_L1_VOQXorMode_WIDTH                         1
#define D0F2xFC_x0D_L1_VOQXorMode_MASK                          0x100
#define D0F2xFC_x0D_L1_CacheByPass_OFFSET                       9
#define D0F2xFC_x0D_L1_CacheByPass_WIDTH                        1
#define D0F2xFC_x0D_L1_CacheByPass_MASK                         0x200
#define D0F2xFC_x0D_L1_L1CacheParityEn_OFFSET                   10
#define D0F2xFC_x0D_L1_L1CacheParityEn_WIDTH                    1
#define D0F2xFC_x0D_L1_L1CacheParityEn_MASK                     0x400
#define D0F2xFC_x0D_L1_L1ParityEn_OFFSET                        11
#define D0F2xFC_x0D_L1_L1ParityEn_WIDTH                         1
#define D0F2xFC_x0D_L1_L1ParityEn_MASK                          0x800
#define D0F2xFC_x0D_L1_L1DTEDis_OFFSET                          12
#define D0F2xFC_x0D_L1_L1DTEDis_WIDTH                           1
#define D0F2xFC_x0D_L1_L1DTEDis_MASK                            0x1000
#define D0F2xFC_x0D_L1_BlockL1Dis_OFFSET                        13
#define D0F2xFC_x0D_L1_BlockL1Dis_WIDTH                         1
#define D0F2xFC_x0D_L1_BlockL1Dis_MASK                          0x2000
#define D0F2xFC_x0D_L1_WqEntrydis_OFFSET                        14
#define D0F2xFC_x0D_L1_WqEntrydis_WIDTH                         5
#define D0F2xFC_x0D_L1_WqEntrydis_MASK                          0x7c000
#define D0F2xFC_x0D_L1_AtsNobufferInsert_OFFSET                 19
#define D0F2xFC_x0D_L1_AtsNobufferInsert_WIDTH                  1
#define D0F2xFC_x0D_L1_AtsNobufferInsert_MASK                   0x80000
#define D0F2xFC_x0D_L1_SndFilterDis_OFFSET                      20
#define D0F2xFC_x0D_L1_SndFilterDis_WIDTH                       1
#define D0F2xFC_x0D_L1_SndFilterDis_MASK                        0x100000
#define D0F2xFC_x0D_L1_L1orderEn_OFFSET                         21
#define D0F2xFC_x0D_L1_L1orderEn_WIDTH                          1
#define D0F2xFC_x0D_L1_L1orderEn_MASK                           0x200000
#define D0F2xFC_x0D_L1_L1CacheInvAllEn_OFFSET                   22
#define D0F2xFC_x0D_L1_L1CacheInvAllEn_WIDTH                    1
#define D0F2xFC_x0D_L1_L1CacheInvAllEn_MASK                     0x400000
#define D0F2xFC_x0D_L1_SelectTimeoutPulse_OFFSET                23
#define D0F2xFC_x0D_L1_SelectTimeoutPulse_WIDTH                 3
#define D0F2xFC_x0D_L1_SelectTimeoutPulse_MASK                  0x3800000
#define D0F2xFC_x0D_L1_L1CacheSelReqid_OFFSET                   26
#define D0F2xFC_x0D_L1_L1CacheSelReqid_WIDTH                    1
#define D0F2xFC_x0D_L1_L1CacheSelReqid_MASK                     0x4000000
#define D0F2xFC_x0D_L1_L1CacheSelInterleave_OFFSET              27
#define D0F2xFC_x0D_L1_L1CacheSelInterleave_WIDTH               1
#define D0F2xFC_x0D_L1_L1CacheSelInterleave_MASK                0x8000000
#define D0F2xFC_x0D_L1_PretransNovaFilteren_OFFSET              28
#define D0F2xFC_x0D_L1_PretransNovaFilteren_WIDTH               1
#define D0F2xFC_x0D_L1_PretransNovaFilteren_MASK                0x10000000
#define D0F2xFC_x0D_L1_Untrans2mFilteren_OFFSET                 29
#define D0F2xFC_x0D_L1_Untrans2mFilteren_WIDTH                  1
#define D0F2xFC_x0D_L1_Untrans2mFilteren_MASK                   0x20000000
#define D0F2xFC_x0D_L1_L1DebugCntrMode_OFFSET                   30
#define D0F2xFC_x0D_L1_L1DebugCntrMode_WIDTH                    1
#define D0F2xFC_x0D_L1_L1DebugCntrMode_MASK                     0x40000000
#define D0F2xFC_x0D_L1_Reserved_31_31_OFFSET                    31
#define D0F2xFC_x0D_L1_Reserved_31_31_WIDTH                     1
#define D0F2xFC_x0D_L1_Reserved_31_31_MASK                      0x80000000

/// D0F2xFC_x0D_L1
typedef union {
  struct {                                                              ///<
    UINT32                                              VOQPortBits:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                              VOQFuncBits:3 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                               VOQXorMode:1 ; ///<
    UINT32                                              CacheByPass:1 ; ///<
    UINT32                                          L1CacheParityEn:1 ; ///<
    UINT32                                               L1ParityEn:1 ; ///<
    UINT32                                                 L1DTEDis:1 ; ///<
    UINT32                                               BlockL1Dis:1 ; ///<
    UINT32                                               WqEntrydis:5 ; ///<
    UINT32                                        AtsNobufferInsert:1 ; ///<
    UINT32                                             SndFilterDis:1 ; ///<
    UINT32                                                L1orderEn:1 ; ///<
    UINT32                                          L1CacheInvAllEn:1 ; ///<
    UINT32                                       SelectTimeoutPulse:3 ; ///<
    UINT32                                          L1CacheSelReqid:1 ; ///<
    UINT32                                     L1CacheSelInterleave:1 ; ///<
    UINT32                                     PretransNovaFilteren:1 ; ///<
    UINT32                                        Untrans2mFilteren:1 ; ///<
    UINT32                                          L1DebugCntrMode:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x0D_L1_STRUCT;

// **** D0F2xFC_x33_L1 Register Definition ****
// Address
#define D0F2xFC_x33_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x33)

// Type
#define D0F2xFC_x33_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x33_L1_L1ClkgateLen_OFFSET                      0
#define D0F2xFC_x33_L1_L1ClkgateLen_WIDTH                       2
#define D0F2xFC_x33_L1_L1ClkgateLen_MASK                        0x3
#define D0F2xFC_x33_L1_Reserved_3_2_OFFSET                      2
#define D0F2xFC_x33_L1_Reserved_3_2_WIDTH                       2
#define D0F2xFC_x33_L1_Reserved_3_2_MASK                        0xc
#define D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET                    4
#define D0F2xFC_x33_L1_L1DmaClkgateEn_WIDTH                     1
#define D0F2xFC_x33_L1_L1DmaClkgateEn_MASK                      0x10
#define D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET                  5
#define D0F2xFC_x33_L1_L1CacheClkgateEn_WIDTH                   1
#define D0F2xFC_x33_L1_L1CacheClkgateEn_MASK                    0x20
#define D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET                  6
#define D0F2xFC_x33_L1_L1CpslvClkgateEn_WIDTH                   1
#define D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK                    0x40
#define D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET               7
#define D0F2xFC_x33_L1_L1DmaInputClkgateEn_WIDTH                1
#define D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK                 0x80
#define D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET                   8
#define D0F2xFC_x33_L1_L1PerfClkgateEn_WIDTH                    1
#define D0F2xFC_x33_L1_L1PerfClkgateEn_MASK                     0x100
#define D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET                 9
#define D0F2xFC_x33_L1_L1MemoryClkgateEn_WIDTH                  1
#define D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK                   0x200
#define D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET                    10
#define D0F2xFC_x33_L1_L1RegClkgateEn_WIDTH                     1
#define D0F2xFC_x33_L1_L1RegClkgateEn_MASK                      0x400
#define D0F2xFC_x33_L1_L1HostreqClkgateEn_OFFSET                11
#define D0F2xFC_x33_L1_L1HostreqClkgateEn_WIDTH                 1
#define D0F2xFC_x33_L1_L1HostreqClkgateEn_MASK                  0x800
#define D0F2xFC_x33_L1_Reserved_30_12_OFFSET                    12
#define D0F2xFC_x33_L1_Reserved_30_12_WIDTH                     19
#define D0F2xFC_x33_L1_Reserved_30_12_MASK                      0x7ffff000
#define D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET                     31
#define D0F2xFC_x33_L1_L1L2ClkgateEn_WIDTH                      1
#define D0F2xFC_x33_L1_L1L2ClkgateEn_MASK                       0x80000000

/// D0F2xFC_x33_L1
typedef union {
  struct {                                                              ///<
    UINT32                                             L1ClkgateLen:2 ; ///<
    UINT32                                             Reserved_3_2:2 ; ///<
    UINT32                                           L1DmaClkgateEn:1 ; ///<
    UINT32                                         L1CacheClkgateEn:1 ; ///<
    UINT32                                         L1CpslvClkgateEn:1 ; ///<
    UINT32                                      L1DmaInputClkgateEn:1 ; ///<
    UINT32                                          L1PerfClkgateEn:1 ; ///<
    UINT32                                        L1MemoryClkgateEn:1 ; ///<
    UINT32                                           L1RegClkgateEn:1 ; ///<
    UINT32                                       L1HostreqClkgateEn:1 ; ///<
    UINT32                                           Reserved_30_12:19; ///<
    UINT32                                            L1L2ClkgateEn:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x33_L1_STRUCT;


// **** D0F2xFC_x21_L1 Register Definition ****
// Address
#define D0F2xFC_x21_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x21)

// Type
#define D0F2xFC_x21_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x21_L1_EntryStatus10_OFFSET                     0
#define D0F2xFC_x21_L1_EntryStatus10_WIDTH                      3
#define D0F2xFC_x21_L1_EntryStatus10_MASK                       0x7
#define D0F2xFC_x21_L1_EntryStatus11_OFFSET                     3
#define D0F2xFC_x21_L1_EntryStatus11_WIDTH                      3
#define D0F2xFC_x21_L1_EntryStatus11_MASK                       0x38
#define D0F2xFC_x21_L1_EntryStatus12_OFFSET                     6
#define D0F2xFC_x21_L1_EntryStatus12_WIDTH                      3
#define D0F2xFC_x21_L1_EntryStatus12_MASK                       0x1c0
#define D0F2xFC_x21_L1_EntryStatus13_OFFSET                     9
#define D0F2xFC_x21_L1_EntryStatus13_WIDTH                      3
#define D0F2xFC_x21_L1_EntryStatus13_MASK                       0xe00
#define D0F2xFC_x21_L1_EntryStatus14_OFFSET                     12
#define D0F2xFC_x21_L1_EntryStatus14_WIDTH                      3
#define D0F2xFC_x21_L1_EntryStatus14_MASK                       0x7000
#define D0F2xFC_x21_L1_EntryStatus15_OFFSET                     15
#define D0F2xFC_x21_L1_EntryStatus15_WIDTH                      3
#define D0F2xFC_x21_L1_EntryStatus15_MASK                       0x38000
#define D0F2xFC_x21_L1_EntryStatus16_OFFSET                     18
#define D0F2xFC_x21_L1_EntryStatus16_WIDTH                      3
#define D0F2xFC_x21_L1_EntryStatus16_MASK                       0x1c0000
#define D0F2xFC_x21_L1_EntryStatus17_OFFSET                     21
#define D0F2xFC_x21_L1_EntryStatus17_WIDTH                      3
#define D0F2xFC_x21_L1_EntryStatus17_MASK                       0xe00000
#define D0F2xFC_x21_L1_EntryStatus18_OFFSET                     24
#define D0F2xFC_x21_L1_EntryStatus18_WIDTH                      3
#define D0F2xFC_x21_L1_EntryStatus18_MASK                       0x7000000
#define D0F2xFC_x21_L1_EntryStatus19_OFFSET                     27
#define D0F2xFC_x21_L1_EntryStatus19_WIDTH                      3
#define D0F2xFC_x21_L1_EntryStatus19_MASK                       0x38000000
#define D0F2xFC_x21_L1_Reserved_31_30_OFFSET                    30
#define D0F2xFC_x21_L1_Reserved_31_30_WIDTH                     2
#define D0F2xFC_x21_L1_Reserved_31_30_MASK                      0xc0000000

/// D0F2xFC_x21_L1
typedef union {
  struct {                                                              ///<
    UINT32                                            EntryStatus10:3 ; ///<
    UINT32                                            EntryStatus11:3 ; ///<
    UINT32                                            EntryStatus12:3 ; ///<
    UINT32                                            EntryStatus13:3 ; ///<
    UINT32                                            EntryStatus14:3 ; ///<
    UINT32                                            EntryStatus15:3 ; ///<
    UINT32                                            EntryStatus16:3 ; ///<
    UINT32                                            EntryStatus17:3 ; ///<
    UINT32                                            EntryStatus18:3 ; ///<
    UINT32                                            EntryStatus19:3 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x21_L1_STRUCT;

// **** D0F2xFC_x00_L1 Register Definition ****
// Address
#define D0F2xFC_x00_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x00)

// Type
#define D0F2xFC_x00_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x00_L1_L1PerfEvent0_OFFSET                      0
#define D0F2xFC_x00_L1_L1PerfEvent0_WIDTH                       8
#define D0F2xFC_x00_L1_L1PerfEvent0_MASK                        0xff
#define D0F2xFC_x00_L1_L1PerfEvent1_OFFSET                      8
#define D0F2xFC_x00_L1_L1PerfEvent1_WIDTH                       8
#define D0F2xFC_x00_L1_L1PerfEvent1_MASK                        0xff00
#define D0F2xFC_x00_L1_L1PerfCountHi0_OFFSET                    16
#define D0F2xFC_x00_L1_L1PerfCountHi0_WIDTH                     8
#define D0F2xFC_x00_L1_L1PerfCountHi0_MASK                      0xff0000
#define D0F2xFC_x00_L1_L1PerfCountHi1_OFFSET                    24
#define D0F2xFC_x00_L1_L1PerfCountHi1_WIDTH                     8
#define D0F2xFC_x00_L1_L1PerfCountHi1_MASK                      0xff000000

/// D0F2xFC_x00_L1
typedef union {
  struct {                                                              ///<
    UINT32                                             L1PerfEvent0:8 ; ///<
    UINT32                                             L1PerfEvent1:8 ; ///<
    UINT32                                           L1PerfCountHi0:8 ; ///<
    UINT32                                           L1PerfCountHi1:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x00_L1_STRUCT;

// **** D0F2xFC_x02_L1 Register Definition ****
// Address
#define D0F2xFC_x02_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x02)

// Type
#define D0F2xFC_x02_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x02_L1_L1PerfCount1_OFFSET                      0
#define D0F2xFC_x02_L1_L1PerfCount1_WIDTH                       32
#define D0F2xFC_x02_L1_L1PerfCount1_MASK                        0xffffffff

/// D0F2xFC_x02_L1
typedef union {
  struct {                                                              ///<
    UINT32                                             L1PerfCount1:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x02_L1_STRUCT;



// **** D0F2xFC_x07_L1 Register Definition ****
// Address
#define D0F2xFC_x07_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x07)

// Type
#define D0F2xFC_x07_L1_TYPE                                     TYPE_D0F2xFC
// Field Data
#define D0F2xFC_x07_L1_PhantomFuncEn_OFFSET                     0
#define D0F2xFC_x07_L1_PhantomFuncEn_WIDTH                      1
#define D0F2xFC_x07_L1_PhantomFuncEn_MASK                       0x1
#define D0F2xFC_x07_L1_Reserved_10_1_OFFSET                     1
#define D0F2xFC_x07_L1_Reserved_10_1_WIDTH                      10
#define D0F2xFC_x07_L1_Reserved_10_1_MASK                       0x7fe
#define D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET                   11
#define D0F2xFC_x07_L1_SpecReqFilterEn_WIDTH                    1
#define D0F2xFC_x07_L1_SpecReqFilterEn_MASK                     0x800
#define D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET                       12
#define D0F2xFC_x07_L1_AtsSeqNumEn_WIDTH                        1
#define D0F2xFC_x07_L1_AtsSeqNumEn_MASK                         0x1000
#define D0F2xFC_x07_L1_Reserved_13_13_OFFSET                    13
#define D0F2xFC_x07_L1_Reserved_13_13_WIDTH                     1
#define D0F2xFC_x07_L1_Reserved_13_13_MASK                      0x2000
#define D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET             14
#define D0F2xFC_x07_L1_AtsPhysPageOverlapDis_WIDTH              1
#define D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK               0x4000
#define D0F2xFC_x07_L1_Reserved_16_15_OFFSET                    15
#define D0F2xFC_x07_L1_Reserved_16_15_WIDTH                     2
#define D0F2xFC_x07_L1_Reserved_16_15_MASK                      0x18000
#define D0F2xFC_x07_L1_L1NwEn_OFFSET                            17
#define D0F2xFC_x07_L1_L1NwEn_WIDTH                             1
#define D0F2xFC_x07_L1_L1NwEn_MASK                              0x20000
#define D0F2xFC_x07_L1_Reserved_31_18_OFFSET                    18
#define D0F2xFC_x07_L1_Reserved_31_18_WIDTH                     14
#define D0F2xFC_x07_L1_Reserved_31_18_MASK                      0xfffc0000

/// D0F2xFC_x07_L1
typedef union {
  struct {                                                              ///<
    UINT32                                            PhantomFuncEn:1 ; ///<
    UINT32                                            Reserved_10_1:10; ///<
    UINT32                                          SpecReqFilterEn:1 ; ///<
    UINT32                                              AtsSeqNumEn:1 ; ///<
    UINT32                                           Reserved_13_13:1 ; ///<
    UINT32                                    AtsPhysPageOverlapDis:1 ; ///<
    UINT32                                           Reserved_16_15:2 ; ///<
    UINT32                                                   L1NwEn:1 ; ///<
    UINT32                                           Reserved_31_18:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F2xFC_x07_L1_STRUCT;

// **** D18F2x9C_x0000_0000_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0000_dct1_mp0_ADDRESS                    0x0

// Type
#define D18F2x9C_x0000_0000_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0000_dct1_mp0_CkeDrvStren_OFFSET         0
#define D18F2x9C_x0000_0000_dct1_mp0_CkeDrvStren_WIDTH          3
#define D18F2x9C_x0000_0000_dct1_mp0_CkeDrvStren_MASK           0x7
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_3_3_OFFSET        3
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_3_3_WIDTH         1
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_3_3_MASK          0x8
#define D18F2x9C_x0000_0000_dct1_mp0_CsOdtDrvStren_OFFSET       4
#define D18F2x9C_x0000_0000_dct1_mp0_CsOdtDrvStren_WIDTH        3
#define D18F2x9C_x0000_0000_dct1_mp0_CsOdtDrvStren_MASK         0x70
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_7_7_OFFSET        7
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_7_7_WIDTH         1
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_7_7_MASK          0x80
#define D18F2x9C_x0000_0000_dct1_mp0_AddrCmdDrvStren_OFFSET     8
#define D18F2x9C_x0000_0000_dct1_mp0_AddrCmdDrvStren_WIDTH      3
#define D18F2x9C_x0000_0000_dct1_mp0_AddrCmdDrvStren_MASK       0x700
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_11_11_OFFSET      11
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_11_11_WIDTH       1
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_11_11_MASK        0x800
#define D18F2x9C_x0000_0000_dct1_mp0_ClkDrvStren_OFFSET         12
#define D18F2x9C_x0000_0000_dct1_mp0_ClkDrvStren_WIDTH          3
#define D18F2x9C_x0000_0000_dct1_mp0_ClkDrvStren_MASK           0x7000
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_15_15_OFFSET      15
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_15_15_WIDTH       1
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_15_15_MASK        0x8000
#define D18F2x9C_x0000_0000_dct1_mp0_DataDrvStren_OFFSET        16
#define D18F2x9C_x0000_0000_dct1_mp0_DataDrvStren_WIDTH         3
#define D18F2x9C_x0000_0000_dct1_mp0_DataDrvStren_MASK          0x70000
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_19_19_OFFSET      19
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_19_19_WIDTH       1
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_19_19_MASK        0x80000
#define D18F2x9C_x0000_0000_dct1_mp0_DqsDrvStren_OFFSET         20
#define D18F2x9C_x0000_0000_dct1_mp0_DqsDrvStren_WIDTH          3
#define D18F2x9C_x0000_0000_dct1_mp0_DqsDrvStren_MASK           0x700000
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_27_23_OFFSET      23
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_27_23_WIDTH       5
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_27_23_MASK        0xf800000
#define D18F2x9C_x0000_0000_dct1_mp0_ProcOdt_OFFSET             28
#define D18F2x9C_x0000_0000_dct1_mp0_ProcOdt_WIDTH              3
#define D18F2x9C_x0000_0000_dct1_mp0_ProcOdt_MASK               0x70000000
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_31_31_OFFSET      31
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_31_31_WIDTH       1
#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_31_31_MASK        0x80000000

/// D18F2x9C_x0000_0000_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                              CkeDrvStren:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                            CsOdtDrvStren:3 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                          AddrCmdDrvStren:3 ; ///<
    UINT32                                           Reserved_11_11:1 ; ///<
    UINT32                                              ClkDrvStren:3 ; ///<
    UINT32                                           Reserved_15_15:1 ; ///<
    UINT32                                             DataDrvStren:3 ; ///<
    UINT32                                           Reserved_19_19:1 ; ///<
    UINT32                                              DqsDrvStren:3 ; ///<
    UINT32                                           Reserved_27_23:5 ; ///<
    UINT32                                                  ProcOdt:3 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0000_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0000_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0000_dct0_mp0_ADDRESS                    0x0

// Type
#define D18F2x9C_x0000_0000_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0000_dct0_mp0_CkeDrvStren_OFFSET         0
#define D18F2x9C_x0000_0000_dct0_mp0_CkeDrvStren_WIDTH          3
#define D18F2x9C_x0000_0000_dct0_mp0_CkeDrvStren_MASK           0x7
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_3_3_OFFSET        3
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_3_3_WIDTH         1
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_3_3_MASK          0x8
#define D18F2x9C_x0000_0000_dct0_mp0_CsOdtDrvStren_OFFSET       4
#define D18F2x9C_x0000_0000_dct0_mp0_CsOdtDrvStren_WIDTH        3
#define D18F2x9C_x0000_0000_dct0_mp0_CsOdtDrvStren_MASK         0x70
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_7_7_OFFSET        7
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_7_7_WIDTH         1
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_7_7_MASK          0x80
#define D18F2x9C_x0000_0000_dct0_mp0_AddrCmdDrvStren_OFFSET     8
#define D18F2x9C_x0000_0000_dct0_mp0_AddrCmdDrvStren_WIDTH      3
#define D18F2x9C_x0000_0000_dct0_mp0_AddrCmdDrvStren_MASK       0x700
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_11_11_OFFSET      11
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_11_11_WIDTH       1
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_11_11_MASK        0x800
#define D18F2x9C_x0000_0000_dct0_mp0_ClkDrvStren_OFFSET         12
#define D18F2x9C_x0000_0000_dct0_mp0_ClkDrvStren_WIDTH          3
#define D18F2x9C_x0000_0000_dct0_mp0_ClkDrvStren_MASK           0x7000
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_15_15_OFFSET      15
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_15_15_WIDTH       1
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_15_15_MASK        0x8000
#define D18F2x9C_x0000_0000_dct0_mp0_DataDrvStren_OFFSET        16
#define D18F2x9C_x0000_0000_dct0_mp0_DataDrvStren_WIDTH         3
#define D18F2x9C_x0000_0000_dct0_mp0_DataDrvStren_MASK          0x70000
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_19_19_OFFSET      19
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_19_19_WIDTH       1
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_19_19_MASK        0x80000
#define D18F2x9C_x0000_0000_dct0_mp0_DqsDrvStren_OFFSET         20
#define D18F2x9C_x0000_0000_dct0_mp0_DqsDrvStren_WIDTH          3
#define D18F2x9C_x0000_0000_dct0_mp0_DqsDrvStren_MASK           0x700000
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_27_23_OFFSET      23
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_27_23_WIDTH       5
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_27_23_MASK        0xf800000
#define D18F2x9C_x0000_0000_dct0_mp0_ProcOdt_OFFSET             28
#define D18F2x9C_x0000_0000_dct0_mp0_ProcOdt_WIDTH              3
#define D18F2x9C_x0000_0000_dct0_mp0_ProcOdt_MASK               0x70000000
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_31_31_OFFSET      31
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_31_31_WIDTH       1
#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_31_31_MASK        0x80000000

/// D18F2x9C_x0000_0000_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                              CkeDrvStren:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                            CsOdtDrvStren:3 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                          AddrCmdDrvStren:3 ; ///<
    UINT32                                           Reserved_11_11:1 ; ///<
    UINT32                                              ClkDrvStren:3 ; ///<
    UINT32                                           Reserved_15_15:1 ; ///<
    UINT32                                             DataDrvStren:3 ; ///<
    UINT32                                           Reserved_19_19:1 ; ///<
    UINT32                                              DqsDrvStren:3 ; ///<
    UINT32                                           Reserved_27_23:5 ; ///<
    UINT32                                                  ProcOdt:3 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0000_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0000_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0000_dct1_mp1_ADDRESS                    0x0

// Type
#define D18F2x9C_x0000_0000_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0000_dct1_mp1_CkeDrvStren_OFFSET         0
#define D18F2x9C_x0000_0000_dct1_mp1_CkeDrvStren_WIDTH          3
#define D18F2x9C_x0000_0000_dct1_mp1_CkeDrvStren_MASK           0x7
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_3_3_OFFSET        3
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_3_3_WIDTH         1
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_3_3_MASK          0x8
#define D18F2x9C_x0000_0000_dct1_mp1_CsOdtDrvStren_OFFSET       4
#define D18F2x9C_x0000_0000_dct1_mp1_CsOdtDrvStren_WIDTH        3
#define D18F2x9C_x0000_0000_dct1_mp1_CsOdtDrvStren_MASK         0x70
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_7_7_OFFSET        7
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_7_7_WIDTH         1
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_7_7_MASK          0x80
#define D18F2x9C_x0000_0000_dct1_mp1_AddrCmdDrvStren_OFFSET     8
#define D18F2x9C_x0000_0000_dct1_mp1_AddrCmdDrvStren_WIDTH      3
#define D18F2x9C_x0000_0000_dct1_mp1_AddrCmdDrvStren_MASK       0x700
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_11_11_OFFSET      11
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_11_11_WIDTH       1
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_11_11_MASK        0x800
#define D18F2x9C_x0000_0000_dct1_mp1_ClkDrvStren_OFFSET         12
#define D18F2x9C_x0000_0000_dct1_mp1_ClkDrvStren_WIDTH          3
#define D18F2x9C_x0000_0000_dct1_mp1_ClkDrvStren_MASK           0x7000
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_15_15_OFFSET      15
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_15_15_WIDTH       1
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_15_15_MASK        0x8000
#define D18F2x9C_x0000_0000_dct1_mp1_DataDrvStren_OFFSET        16
#define D18F2x9C_x0000_0000_dct1_mp1_DataDrvStren_WIDTH         3
#define D18F2x9C_x0000_0000_dct1_mp1_DataDrvStren_MASK          0x70000
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_19_19_OFFSET      19
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_19_19_WIDTH       1
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_19_19_MASK        0x80000
#define D18F2x9C_x0000_0000_dct1_mp1_DqsDrvStren_OFFSET         20
#define D18F2x9C_x0000_0000_dct1_mp1_DqsDrvStren_WIDTH          3
#define D18F2x9C_x0000_0000_dct1_mp1_DqsDrvStren_MASK           0x700000
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_27_23_OFFSET      23
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_27_23_WIDTH       5
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_27_23_MASK        0xf800000
#define D18F2x9C_x0000_0000_dct1_mp1_ProcOdt_OFFSET             28
#define D18F2x9C_x0000_0000_dct1_mp1_ProcOdt_WIDTH              3
#define D18F2x9C_x0000_0000_dct1_mp1_ProcOdt_MASK               0x70000000
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_31_31_OFFSET      31
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_31_31_WIDTH       1
#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_31_31_MASK        0x80000000

/// D18F2x9C_x0000_0000_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                              CkeDrvStren:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                            CsOdtDrvStren:3 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                          AddrCmdDrvStren:3 ; ///<
    UINT32                                           Reserved_11_11:1 ; ///<
    UINT32                                              ClkDrvStren:3 ; ///<
    UINT32                                           Reserved_15_15:1 ; ///<
    UINT32                                             DataDrvStren:3 ; ///<
    UINT32                                           Reserved_19_19:1 ; ///<
    UINT32                                              DqsDrvStren:3 ; ///<
    UINT32                                           Reserved_27_23:5 ; ///<
    UINT32                                                  ProcOdt:3 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0000_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0000_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0000_dct0_mp1_ADDRESS                    0x0

// Type
#define D18F2x9C_x0000_0000_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0000_dct0_mp1_CkeDrvStren_OFFSET         0
#define D18F2x9C_x0000_0000_dct0_mp1_CkeDrvStren_WIDTH          3
#define D18F2x9C_x0000_0000_dct0_mp1_CkeDrvStren_MASK           0x7
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_3_3_OFFSET        3
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_3_3_WIDTH         1
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_3_3_MASK          0x8
#define D18F2x9C_x0000_0000_dct0_mp1_CsOdtDrvStren_OFFSET       4
#define D18F2x9C_x0000_0000_dct0_mp1_CsOdtDrvStren_WIDTH        3
#define D18F2x9C_x0000_0000_dct0_mp1_CsOdtDrvStren_MASK         0x70
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_7_7_OFFSET        7
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_7_7_WIDTH         1
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_7_7_MASK          0x80
#define D18F2x9C_x0000_0000_dct0_mp1_AddrCmdDrvStren_OFFSET     8
#define D18F2x9C_x0000_0000_dct0_mp1_AddrCmdDrvStren_WIDTH      3
#define D18F2x9C_x0000_0000_dct0_mp1_AddrCmdDrvStren_MASK       0x700
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_11_11_OFFSET      11
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_11_11_WIDTH       1
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_11_11_MASK        0x800
#define D18F2x9C_x0000_0000_dct0_mp1_ClkDrvStren_OFFSET         12
#define D18F2x9C_x0000_0000_dct0_mp1_ClkDrvStren_WIDTH          3
#define D18F2x9C_x0000_0000_dct0_mp1_ClkDrvStren_MASK           0x7000
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_15_15_OFFSET      15
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_15_15_WIDTH       1
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_15_15_MASK        0x8000
#define D18F2x9C_x0000_0000_dct0_mp1_DataDrvStren_OFFSET        16
#define D18F2x9C_x0000_0000_dct0_mp1_DataDrvStren_WIDTH         3
#define D18F2x9C_x0000_0000_dct0_mp1_DataDrvStren_MASK          0x70000
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_19_19_OFFSET      19
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_19_19_WIDTH       1
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_19_19_MASK        0x80000
#define D18F2x9C_x0000_0000_dct0_mp1_DqsDrvStren_OFFSET         20
#define D18F2x9C_x0000_0000_dct0_mp1_DqsDrvStren_WIDTH          3
#define D18F2x9C_x0000_0000_dct0_mp1_DqsDrvStren_MASK           0x700000
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_27_23_OFFSET      23
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_27_23_WIDTH       5
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_27_23_MASK        0xf800000
#define D18F2x9C_x0000_0000_dct0_mp1_ProcOdt_OFFSET             28
#define D18F2x9C_x0000_0000_dct0_mp1_ProcOdt_WIDTH              3
#define D18F2x9C_x0000_0000_dct0_mp1_ProcOdt_MASK               0x70000000
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_31_31_OFFSET      31
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_31_31_WIDTH       1
#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_31_31_MASK        0x80000000

/// D18F2x9C_x0000_0000_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                              CkeDrvStren:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                            CsOdtDrvStren:3 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                          AddrCmdDrvStren:3 ; ///<
    UINT32                                           Reserved_11_11:1 ; ///<
    UINT32                                              ClkDrvStren:3 ; ///<
    UINT32                                           Reserved_15_15:1 ; ///<
    UINT32                                             DataDrvStren:3 ; ///<
    UINT32                                           Reserved_19_19:1 ; ///<
    UINT32                                              DqsDrvStren:3 ; ///<
    UINT32                                           Reserved_27_23:5 ; ///<
    UINT32                                                  ProcOdt:3 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0000_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0001_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0001_dct1_mp0_ADDRESS                    0x1

// Type
#define D18F2x9C_x0000_0001_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0001_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0001_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0001_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0001_dct0_mp0_ADDRESS                    0x1

// Type
#define D18F2x9C_x0000_0001_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0001_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0001_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0001_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0001_dct1_mp1_ADDRESS                    0x1

// Type
#define D18F2x9C_x0000_0001_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0001_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0001_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0001_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0001_dct0_mp1_ADDRESS                    0x1

// Type
#define D18F2x9C_x0000_0001_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0001_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0001_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0002_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0002_dct1_mp1_ADDRESS                    0x2

// Type
#define D18F2x9C_x0000_0002_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0002_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0002_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0002_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0002_dct1_mp0_ADDRESS                    0x2

// Type
#define D18F2x9C_x0000_0002_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0002_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0002_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0002_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0002_dct0_mp1_ADDRESS                    0x2

// Type
#define D18F2x9C_x0000_0002_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0002_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0002_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0002_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0002_dct0_mp0_ADDRESS                    0x2

// Type
#define D18F2x9C_x0000_0002_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0002_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0002_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0004_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0004_dct1_mp1_ADDRESS                    0x4

// Type
#define D18F2x9C_x0000_0004_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0004_dct1_mp1_CkeFineDelay_OFFSET        0
#define D18F2x9C_x0000_0004_dct1_mp1_CkeFineDelay_WIDTH         5
#define D18F2x9C_x0000_0004_dct1_mp1_CkeFineDelay_MASK          0x1f
#define D18F2x9C_x0000_0004_dct1_mp1_CkeSetup_OFFSET            5
#define D18F2x9C_x0000_0004_dct1_mp1_CkeSetup_WIDTH             1
#define D18F2x9C_x0000_0004_dct1_mp1_CkeSetup_MASK              0x20
#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_7_6_OFFSET        6
#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_7_6_WIDTH         2
#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_7_6_MASK          0xc0
#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtFineDelay_OFFSET      8
#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtFineDelay_WIDTH       5
#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtFineDelay_MASK        0x1f00
#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtSetup_OFFSET          13
#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtSetup_WIDTH           1
#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtSetup_MASK            0x2000
#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_15_14_OFFSET      14
#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_15_14_WIDTH       2
#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_15_14_MASK        0xc000
#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdFineDelay_OFFSET    16
#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdFineDelay_WIDTH     5
#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdFineDelay_MASK      0x1f0000
#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdSetup_OFFSET        21
#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdSetup_WIDTH         1
#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdSetup_MASK          0x200000
#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_31_22_OFFSET      22
#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_31_22_WIDTH       10
#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_31_22_MASK        0xffc00000

/// D18F2x9C_x0000_0004_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             CkeFineDelay:5 ; ///<
    UINT32                                                 CkeSetup:1 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                           CsOdtFineDelay:5 ; ///<
    UINT32                                               CsOdtSetup:1 ; ///<
    UINT32                                           Reserved_15_14:2 ; ///<
    UINT32                                         AddrCmdFineDelay:5 ; ///<
    UINT32                                             AddrCmdSetup:1 ; ///<
    UINT32                                           Reserved_31_22:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0004_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0004_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0004_dct0_mp0_ADDRESS                    0x4

// Type
#define D18F2x9C_x0000_0004_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0004_dct0_mp0_CkeFineDelay_OFFSET        0
#define D18F2x9C_x0000_0004_dct0_mp0_CkeFineDelay_WIDTH         5
#define D18F2x9C_x0000_0004_dct0_mp0_CkeFineDelay_MASK          0x1f
#define D18F2x9C_x0000_0004_dct0_mp0_CkeSetup_OFFSET            5
#define D18F2x9C_x0000_0004_dct0_mp0_CkeSetup_WIDTH             1
#define D18F2x9C_x0000_0004_dct0_mp0_CkeSetup_MASK              0x20
#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_7_6_OFFSET        6
#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_7_6_WIDTH         2
#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_7_6_MASK          0xc0
#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtFineDelay_OFFSET      8
#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtFineDelay_WIDTH       5
#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtFineDelay_MASK        0x1f00
#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtSetup_OFFSET          13
#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtSetup_WIDTH           1
#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtSetup_MASK            0x2000
#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_15_14_OFFSET      14
#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_15_14_WIDTH       2
#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_15_14_MASK        0xc000
#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdFineDelay_OFFSET    16
#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdFineDelay_WIDTH     5
#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdFineDelay_MASK      0x1f0000
#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdSetup_OFFSET        21
#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdSetup_WIDTH         1
#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdSetup_MASK          0x200000
#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_31_22_OFFSET      22
#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_31_22_WIDTH       10
#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_31_22_MASK        0xffc00000

/// D18F2x9C_x0000_0004_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             CkeFineDelay:5 ; ///<
    UINT32                                                 CkeSetup:1 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                           CsOdtFineDelay:5 ; ///<
    UINT32                                               CsOdtSetup:1 ; ///<
    UINT32                                           Reserved_15_14:2 ; ///<
    UINT32                                         AddrCmdFineDelay:5 ; ///<
    UINT32                                             AddrCmdSetup:1 ; ///<
    UINT32                                           Reserved_31_22:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0004_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0004_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0004_dct0_mp1_ADDRESS                    0x4

// Type
#define D18F2x9C_x0000_0004_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0004_dct0_mp1_CkeFineDelay_OFFSET        0
#define D18F2x9C_x0000_0004_dct0_mp1_CkeFineDelay_WIDTH         5
#define D18F2x9C_x0000_0004_dct0_mp1_CkeFineDelay_MASK          0x1f
#define D18F2x9C_x0000_0004_dct0_mp1_CkeSetup_OFFSET            5
#define D18F2x9C_x0000_0004_dct0_mp1_CkeSetup_WIDTH             1
#define D18F2x9C_x0000_0004_dct0_mp1_CkeSetup_MASK              0x20
#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_7_6_OFFSET        6
#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_7_6_WIDTH         2
#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_7_6_MASK          0xc0
#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtFineDelay_OFFSET      8
#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtFineDelay_WIDTH       5
#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtFineDelay_MASK        0x1f00
#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtSetup_OFFSET          13
#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtSetup_WIDTH           1
#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtSetup_MASK            0x2000
#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_15_14_OFFSET      14
#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_15_14_WIDTH       2
#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_15_14_MASK        0xc000
#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdFineDelay_OFFSET    16
#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdFineDelay_WIDTH     5
#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdFineDelay_MASK      0x1f0000
#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdSetup_OFFSET        21
#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdSetup_WIDTH         1
#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdSetup_MASK          0x200000
#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_31_22_OFFSET      22
#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_31_22_WIDTH       10
#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_31_22_MASK        0xffc00000

/// D18F2x9C_x0000_0004_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             CkeFineDelay:5 ; ///<
    UINT32                                                 CkeSetup:1 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                           CsOdtFineDelay:5 ; ///<
    UINT32                                               CsOdtSetup:1 ; ///<
    UINT32                                           Reserved_15_14:2 ; ///<
    UINT32                                         AddrCmdFineDelay:5 ; ///<
    UINT32                                             AddrCmdSetup:1 ; ///<
    UINT32                                           Reserved_31_22:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0004_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0004_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0004_dct1_mp0_ADDRESS                    0x4

// Type
#define D18F2x9C_x0000_0004_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0004_dct1_mp0_CkeFineDelay_OFFSET        0
#define D18F2x9C_x0000_0004_dct1_mp0_CkeFineDelay_WIDTH         5
#define D18F2x9C_x0000_0004_dct1_mp0_CkeFineDelay_MASK          0x1f
#define D18F2x9C_x0000_0004_dct1_mp0_CkeSetup_OFFSET            5
#define D18F2x9C_x0000_0004_dct1_mp0_CkeSetup_WIDTH             1
#define D18F2x9C_x0000_0004_dct1_mp0_CkeSetup_MASK              0x20
#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_7_6_OFFSET        6
#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_7_6_WIDTH         2
#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_7_6_MASK          0xc0
#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtFineDelay_OFFSET      8
#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtFineDelay_WIDTH       5
#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtFineDelay_MASK        0x1f00
#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtSetup_OFFSET          13
#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtSetup_WIDTH           1
#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtSetup_MASK            0x2000
#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_15_14_OFFSET      14
#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_15_14_WIDTH       2
#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_15_14_MASK        0xc000
#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdFineDelay_OFFSET    16
#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdFineDelay_WIDTH     5
#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdFineDelay_MASK      0x1f0000
#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdSetup_OFFSET        21
#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdSetup_WIDTH         1
#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdSetup_MASK          0x200000
#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_31_22_OFFSET      22
#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_31_22_WIDTH       10
#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_31_22_MASK        0xffc00000

/// D18F2x9C_x0000_0004_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             CkeFineDelay:5 ; ///<
    UINT32                                                 CkeSetup:1 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                           CsOdtFineDelay:5 ; ///<
    UINT32                                               CsOdtSetup:1 ; ///<
    UINT32                                           Reserved_15_14:2 ; ///<
    UINT32                                         AddrCmdFineDelay:5 ; ///<
    UINT32                                             AddrCmdSetup:1 ; ///<
    UINT32                                           Reserved_31_22:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0004_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0005_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0005_dct0_mp0_ADDRESS                    0x5

// Type
#define D18F2x9C_x0000_0005_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0005_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0005_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0005_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0005_dct1_mp0_ADDRESS                    0x5

// Type
#define D18F2x9C_x0000_0005_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0005_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0005_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0005_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0005_dct1_mp1_ADDRESS                    0x5

// Type
#define D18F2x9C_x0000_0005_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0005_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0005_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0005_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0005_dct0_mp1_ADDRESS                    0x5

// Type
#define D18F2x9C_x0000_0005_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0005_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0005_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0006_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0006_dct1_mp0_ADDRESS                    0x6

// Type
#define D18F2x9C_x0000_0006_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0006_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0006_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0006_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0006_dct0_mp1_ADDRESS                    0x6

// Type
#define D18F2x9C_x0000_0006_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0006_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0006_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0006_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0006_dct1_mp1_ADDRESS                    0x6

// Type
#define D18F2x9C_x0000_0006_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0006_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0006_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0006_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0006_dct0_mp0_ADDRESS                    0x6

// Type
#define D18F2x9C_x0000_0006_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0006_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0006_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0008_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0008_dct0_mp1_ADDRESS                    0x8

// Type
#define D18F2x9C_x0000_0008_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0008_dct0_mp1_WrtLvTrEn_OFFSET           0
#define D18F2x9C_x0000_0008_dct0_mp1_WrtLvTrEn_WIDTH            1
#define D18F2x9C_x0000_0008_dct0_mp1_WrtLvTrEn_MASK             0x1
#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_1_1_OFFSET        1
#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_1_1_WIDTH         1
#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_1_1_MASK          0x2
#define D18F2x9C_x0000_0008_dct0_mp1_TrNibbleSel_OFFSET         2
#define D18F2x9C_x0000_0008_dct0_mp1_TrNibbleSel_WIDTH          1
#define D18F2x9C_x0000_0008_dct0_mp1_TrNibbleSel_MASK           0x4
#define D18F2x9C_x0000_0008_dct0_mp1_PhyFenceTrEn_OFFSET        3
#define D18F2x9C_x0000_0008_dct0_mp1_PhyFenceTrEn_WIDTH         1
#define D18F2x9C_x0000_0008_dct0_mp1_PhyFenceTrEn_MASK          0x8
#define D18F2x9C_x0000_0008_dct0_mp1_TrChipSel_OFFSET           4
#define D18F2x9C_x0000_0008_dct0_mp1_TrChipSel_WIDTH            2
#define D18F2x9C_x0000_0008_dct0_mp1_TrChipSel_MASK             0x30
#define D18F2x9C_x0000_0008_dct0_mp1_FenceTrSel_OFFSET          6
#define D18F2x9C_x0000_0008_dct0_mp1_FenceTrSel_WIDTH           2
#define D18F2x9C_x0000_0008_dct0_mp1_FenceTrSel_MASK            0xc0
#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdt_OFFSET             8
#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdt_WIDTH              4
#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdt_MASK               0xf00
#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdtEn_OFFSET           12
#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdtEn_WIDTH            1
#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdtEn_MASK             0x1000
#define D18F2x9C_x0000_0008_dct0_mp1_DqsRcvTrEn_OFFSET          13
#define D18F2x9C_x0000_0008_dct0_mp1_DqsRcvTrEn_WIDTH           1
#define D18F2x9C_x0000_0008_dct0_mp1_DqsRcvTrEn_MASK            0x2000
#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_28_14_OFFSET      14
#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_28_14_WIDTH       15
#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_28_14_MASK        0x1fffc000
#define D18F2x9C_x0000_0008_dct0_mp1_DisablePredriverCal_OFFSET 29
#define D18F2x9C_x0000_0008_dct0_mp1_DisablePredriverCal_WIDTH  1
#define D18F2x9C_x0000_0008_dct0_mp1_DisablePredriverCal_MASK   0x20000000
#define D18F2x9C_x0000_0008_dct0_mp1_DisAutoComp_OFFSET         30
#define D18F2x9C_x0000_0008_dct0_mp1_DisAutoComp_WIDTH          1
#define D18F2x9C_x0000_0008_dct0_mp1_DisAutoComp_MASK           0x40000000
#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_31_31_OFFSET      31
#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_31_31_WIDTH       1
#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_31_31_MASK        0x80000000

/// D18F2x9C_x0000_0008_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                WrtLvTrEn:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                              TrNibbleSel:1 ; ///<
    UINT32                                             PhyFenceTrEn:1 ; ///<
    UINT32                                                TrChipSel:2 ; ///<
    UINT32                                               FenceTrSel:2 ; ///<
    UINT32                                                  WrLvOdt:4 ; ///<
    UINT32                                                WrLvOdtEn:1 ; ///<
    UINT32                                               DqsRcvTrEn:1 ; ///<
    UINT32                                           Reserved_28_14:15; ///<
    UINT32                                      DisablePredriverCal:1 ; ///<
    UINT32                                              DisAutoComp:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0008_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0008_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0008_dct0_mp0_ADDRESS                    0x8

// Type
#define D18F2x9C_x0000_0008_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0008_dct0_mp0_WrtLvTrEn_OFFSET           0
#define D18F2x9C_x0000_0008_dct0_mp0_WrtLvTrEn_WIDTH            1
#define D18F2x9C_x0000_0008_dct0_mp0_WrtLvTrEn_MASK             0x1
#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_1_1_OFFSET        1
#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_1_1_WIDTH         1
#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_1_1_MASK          0x2
#define D18F2x9C_x0000_0008_dct0_mp0_TrNibbleSel_OFFSET         2
#define D18F2x9C_x0000_0008_dct0_mp0_TrNibbleSel_WIDTH          1
#define D18F2x9C_x0000_0008_dct0_mp0_TrNibbleSel_MASK           0x4
#define D18F2x9C_x0000_0008_dct0_mp0_PhyFenceTrEn_OFFSET        3
#define D18F2x9C_x0000_0008_dct0_mp0_PhyFenceTrEn_WIDTH         1
#define D18F2x9C_x0000_0008_dct0_mp0_PhyFenceTrEn_MASK          0x8
#define D18F2x9C_x0000_0008_dct0_mp0_TrChipSel_OFFSET           4
#define D18F2x9C_x0000_0008_dct0_mp0_TrChipSel_WIDTH            2
#define D18F2x9C_x0000_0008_dct0_mp0_TrChipSel_MASK             0x30
#define D18F2x9C_x0000_0008_dct0_mp0_FenceTrSel_OFFSET          6
#define D18F2x9C_x0000_0008_dct0_mp0_FenceTrSel_WIDTH           2
#define D18F2x9C_x0000_0008_dct0_mp0_FenceTrSel_MASK            0xc0
#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdt_OFFSET             8
#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdt_WIDTH              4
#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdt_MASK               0xf00
#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdtEn_OFFSET           12
#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdtEn_WIDTH            1
#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdtEn_MASK             0x1000
#define D18F2x9C_x0000_0008_dct0_mp0_DqsRcvTrEn_OFFSET          13
#define D18F2x9C_x0000_0008_dct0_mp0_DqsRcvTrEn_WIDTH           1
#define D18F2x9C_x0000_0008_dct0_mp0_DqsRcvTrEn_MASK            0x2000
#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_28_14_OFFSET      14
#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_28_14_WIDTH       15
#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_28_14_MASK        0x1fffc000
#define D18F2x9C_x0000_0008_dct0_mp0_DisablePredriverCal_OFFSET 29
#define D18F2x9C_x0000_0008_dct0_mp0_DisablePredriverCal_WIDTH  1
#define D18F2x9C_x0000_0008_dct0_mp0_DisablePredriverCal_MASK   0x20000000
#define D18F2x9C_x0000_0008_dct0_mp0_DisAutoComp_OFFSET         30
#define D18F2x9C_x0000_0008_dct0_mp0_DisAutoComp_WIDTH          1
#define D18F2x9C_x0000_0008_dct0_mp0_DisAutoComp_MASK           0x40000000
#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_31_31_OFFSET      31
#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_31_31_WIDTH       1
#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_31_31_MASK        0x80000000

/// D18F2x9C_x0000_0008_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                WrtLvTrEn:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                              TrNibbleSel:1 ; ///<
    UINT32                                             PhyFenceTrEn:1 ; ///<
    UINT32                                                TrChipSel:2 ; ///<
    UINT32                                               FenceTrSel:2 ; ///<
    UINT32                                                  WrLvOdt:4 ; ///<
    UINT32                                                WrLvOdtEn:1 ; ///<
    UINT32                                               DqsRcvTrEn:1 ; ///<
    UINT32                                           Reserved_28_14:15; ///<
    UINT32                                      DisablePredriverCal:1 ; ///<
    UINT32                                              DisAutoComp:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0008_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0008_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0008_dct1_mp0_ADDRESS                    0x8

// Type
#define D18F2x9C_x0000_0008_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0008_dct1_mp0_WrtLvTrEn_OFFSET           0
#define D18F2x9C_x0000_0008_dct1_mp0_WrtLvTrEn_WIDTH            1
#define D18F2x9C_x0000_0008_dct1_mp0_WrtLvTrEn_MASK             0x1
#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_1_1_OFFSET        1
#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_1_1_WIDTH         1
#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_1_1_MASK          0x2
#define D18F2x9C_x0000_0008_dct1_mp0_TrNibbleSel_OFFSET         2
#define D18F2x9C_x0000_0008_dct1_mp0_TrNibbleSel_WIDTH          1
#define D18F2x9C_x0000_0008_dct1_mp0_TrNibbleSel_MASK           0x4
#define D18F2x9C_x0000_0008_dct1_mp0_PhyFenceTrEn_OFFSET        3
#define D18F2x9C_x0000_0008_dct1_mp0_PhyFenceTrEn_WIDTH         1
#define D18F2x9C_x0000_0008_dct1_mp0_PhyFenceTrEn_MASK          0x8
#define D18F2x9C_x0000_0008_dct1_mp0_TrChipSel_OFFSET           4
#define D18F2x9C_x0000_0008_dct1_mp0_TrChipSel_WIDTH            2
#define D18F2x9C_x0000_0008_dct1_mp0_TrChipSel_MASK             0x30
#define D18F2x9C_x0000_0008_dct1_mp0_FenceTrSel_OFFSET          6
#define D18F2x9C_x0000_0008_dct1_mp0_FenceTrSel_WIDTH           2
#define D18F2x9C_x0000_0008_dct1_mp0_FenceTrSel_MASK            0xc0
#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdt_OFFSET             8
#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdt_WIDTH              4
#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdt_MASK               0xf00
#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdtEn_OFFSET           12
#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdtEn_WIDTH            1
#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdtEn_MASK             0x1000
#define D18F2x9C_x0000_0008_dct1_mp0_DqsRcvTrEn_OFFSET          13
#define D18F2x9C_x0000_0008_dct1_mp0_DqsRcvTrEn_WIDTH           1
#define D18F2x9C_x0000_0008_dct1_mp0_DqsRcvTrEn_MASK            0x2000
#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_28_14_OFFSET      14
#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_28_14_WIDTH       15
#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_28_14_MASK        0x1fffc000
#define D18F2x9C_x0000_0008_dct1_mp0_DisablePredriverCal_OFFSET 29
#define D18F2x9C_x0000_0008_dct1_mp0_DisablePredriverCal_WIDTH  1
#define D18F2x9C_x0000_0008_dct1_mp0_DisablePredriverCal_MASK   0x20000000
#define D18F2x9C_x0000_0008_dct1_mp0_DisAutoComp_OFFSET         30
#define D18F2x9C_x0000_0008_dct1_mp0_DisAutoComp_WIDTH          1
#define D18F2x9C_x0000_0008_dct1_mp0_DisAutoComp_MASK           0x40000000
#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_31_31_OFFSET      31
#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_31_31_WIDTH       1
#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_31_31_MASK        0x80000000

/// D18F2x9C_x0000_0008_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                                WrtLvTrEn:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                              TrNibbleSel:1 ; ///<
    UINT32                                             PhyFenceTrEn:1 ; ///<
    UINT32                                                TrChipSel:2 ; ///<
    UINT32                                               FenceTrSel:2 ; ///<
    UINT32                                                  WrLvOdt:4 ; ///<
    UINT32                                                WrLvOdtEn:1 ; ///<
    UINT32                                               DqsRcvTrEn:1 ; ///<
    UINT32                                           Reserved_28_14:15; ///<
    UINT32                                      DisablePredriverCal:1 ; ///<
    UINT32                                              DisAutoComp:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0008_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0008_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0008_dct1_mp1_ADDRESS                    0x8

// Type
#define D18F2x9C_x0000_0008_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0008_dct1_mp1_WrtLvTrEn_OFFSET           0
#define D18F2x9C_x0000_0008_dct1_mp1_WrtLvTrEn_WIDTH            1
#define D18F2x9C_x0000_0008_dct1_mp1_WrtLvTrEn_MASK             0x1
#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_1_1_OFFSET        1
#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_1_1_WIDTH         1
#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_1_1_MASK          0x2
#define D18F2x9C_x0000_0008_dct1_mp1_TrNibbleSel_OFFSET         2
#define D18F2x9C_x0000_0008_dct1_mp1_TrNibbleSel_WIDTH          1
#define D18F2x9C_x0000_0008_dct1_mp1_TrNibbleSel_MASK           0x4
#define D18F2x9C_x0000_0008_dct1_mp1_PhyFenceTrEn_OFFSET        3
#define D18F2x9C_x0000_0008_dct1_mp1_PhyFenceTrEn_WIDTH         1
#define D18F2x9C_x0000_0008_dct1_mp1_PhyFenceTrEn_MASK          0x8
#define D18F2x9C_x0000_0008_dct1_mp1_TrChipSel_OFFSET           4
#define D18F2x9C_x0000_0008_dct1_mp1_TrChipSel_WIDTH            2
#define D18F2x9C_x0000_0008_dct1_mp1_TrChipSel_MASK             0x30
#define D18F2x9C_x0000_0008_dct1_mp1_FenceTrSel_OFFSET          6
#define D18F2x9C_x0000_0008_dct1_mp1_FenceTrSel_WIDTH           2
#define D18F2x9C_x0000_0008_dct1_mp1_FenceTrSel_MASK            0xc0
#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdt_OFFSET             8
#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdt_WIDTH              4
#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdt_MASK               0xf00
#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdtEn_OFFSET           12
#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdtEn_WIDTH            1
#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdtEn_MASK             0x1000
#define D18F2x9C_x0000_0008_dct1_mp1_DqsRcvTrEn_OFFSET          13
#define D18F2x9C_x0000_0008_dct1_mp1_DqsRcvTrEn_WIDTH           1
#define D18F2x9C_x0000_0008_dct1_mp1_DqsRcvTrEn_MASK            0x2000
#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_28_14_OFFSET      14
#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_28_14_WIDTH       15
#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_28_14_MASK        0x1fffc000
#define D18F2x9C_x0000_0008_dct1_mp1_DisablePredriverCal_OFFSET 29
#define D18F2x9C_x0000_0008_dct1_mp1_DisablePredriverCal_WIDTH  1
#define D18F2x9C_x0000_0008_dct1_mp1_DisablePredriverCal_MASK   0x20000000
#define D18F2x9C_x0000_0008_dct1_mp1_DisAutoComp_OFFSET         30
#define D18F2x9C_x0000_0008_dct1_mp1_DisAutoComp_WIDTH          1
#define D18F2x9C_x0000_0008_dct1_mp1_DisAutoComp_MASK           0x40000000
#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_31_31_OFFSET      31
#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_31_31_WIDTH       1
#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_31_31_MASK        0x80000000

/// D18F2x9C_x0000_0008_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                                WrtLvTrEn:1 ; ///<
    UINT32                                             Reserved_1_1:1 ; ///<
    UINT32                                              TrNibbleSel:1 ; ///<
    UINT32                                             PhyFenceTrEn:1 ; ///<
    UINT32                                                TrChipSel:2 ; ///<
    UINT32                                               FenceTrSel:2 ; ///<
    UINT32                                                  WrLvOdt:4 ; ///<
    UINT32                                                WrLvOdtEn:1 ; ///<
    UINT32                                               DqsRcvTrEn:1 ; ///<
    UINT32                                           Reserved_28_14:15; ///<
    UINT32                                      DisablePredriverCal:1 ; ///<
    UINT32                                              DisAutoComp:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0008_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_000B_dct0 Register Definition ****
// Address
#define D18F2x9C_x0000_000B_dct0_ADDRESS                        0xb

// Type
#define D18F2x9C_x0000_000B_dct0_TYPE                           TYPE_D18F2x9C_dct0
// Field Data
#define D18F2x9C_x0000_000B_dct0_Reserved_22_0_OFFSET           0
#define D18F2x9C_x0000_000B_dct0_Reserved_22_0_WIDTH            23
#define D18F2x9C_x0000_000B_dct0_Reserved_22_0_MASK             0x7fffff
#define D18F2x9C_x0000_000B_dct0_PhySelfRefreshMode_OFFSET      23
#define D18F2x9C_x0000_000B_dct0_PhySelfRefreshMode_WIDTH       1
#define D18F2x9C_x0000_000B_dct0_PhySelfRefreshMode_MASK        0x800000
#define D18F2x9C_x0000_000B_dct0_Reserved_25_24_OFFSET          24
#define D18F2x9C_x0000_000B_dct0_Reserved_25_24_WIDTH           2
#define D18F2x9C_x0000_000B_dct0_Reserved_25_24_MASK            0x3000000
#define D18F2x9C_x0000_000B_dct0_PhyPS_OFFSET                   26
#define D18F2x9C_x0000_000B_dct0_PhyPS_WIDTH                    1
#define D18F2x9C_x0000_000B_dct0_PhyPS_MASK                     0x4000000
#define D18F2x9C_x0000_000B_dct0_Reserved_29_27_OFFSET          27
#define D18F2x9C_x0000_000B_dct0_Reserved_29_27_WIDTH           3
#define D18F2x9C_x0000_000B_dct0_Reserved_29_27_MASK            0x38000000
#define D18F2x9C_x0000_000B_dct0_PhyPSReq_OFFSET                30
#define D18F2x9C_x0000_000B_dct0_PhyPSReq_WIDTH                 1
#define D18F2x9C_x0000_000B_dct0_PhyPSReq_MASK                  0x40000000
#define D18F2x9C_x0000_000B_dct0_DynModeChange_OFFSET           31
#define D18F2x9C_x0000_000B_dct0_DynModeChange_WIDTH            1
#define D18F2x9C_x0000_000B_dct0_DynModeChange_MASK             0x80000000

/// D18F2x9C_x0000_000B_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_22_0:23; ///<
    UINT32                                       PhySelfRefreshMode:1 ; ///<
    UINT32                                           Reserved_25_24:2 ; ///<
    UINT32                                                    PhyPS:1 ; ///<
    UINT32                                           Reserved_29_27:3 ; ///<
    UINT32                                                 PhyPSReq:1 ; ///<
    UINT32                                            DynModeChange:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_000B_dct0_STRUCT;

// **** D18F2x9C_x0000_000B_dct1 Register Definition ****
// Address
#define D18F2x9C_x0000_000B_dct1_ADDRESS                        0xb

// Type
#define D18F2x9C_x0000_000B_dct1_TYPE                           TYPE_D18F2x9C_dct1
// Field Data
#define D18F2x9C_x0000_000B_dct1_Reserved_22_0_OFFSET           0
#define D18F2x9C_x0000_000B_dct1_Reserved_22_0_WIDTH            23
#define D18F2x9C_x0000_000B_dct1_Reserved_22_0_MASK             0x7fffff
#define D18F2x9C_x0000_000B_dct1_PhySelfRefreshMode_OFFSET      23
#define D18F2x9C_x0000_000B_dct1_PhySelfRefreshMode_WIDTH       1
#define D18F2x9C_x0000_000B_dct1_PhySelfRefreshMode_MASK        0x800000
#define D18F2x9C_x0000_000B_dct1_Reserved_25_24_OFFSET          24
#define D18F2x9C_x0000_000B_dct1_Reserved_25_24_WIDTH           2
#define D18F2x9C_x0000_000B_dct1_Reserved_25_24_MASK            0x3000000
#define D18F2x9C_x0000_000B_dct1_PhyPS_OFFSET                   26
#define D18F2x9C_x0000_000B_dct1_PhyPS_WIDTH                    1
#define D18F2x9C_x0000_000B_dct1_PhyPS_MASK                     0x4000000
#define D18F2x9C_x0000_000B_dct1_Reserved_29_27_OFFSET          27
#define D18F2x9C_x0000_000B_dct1_Reserved_29_27_WIDTH           3
#define D18F2x9C_x0000_000B_dct1_Reserved_29_27_MASK            0x38000000
#define D18F2x9C_x0000_000B_dct1_PhyPSReq_OFFSET                30
#define D18F2x9C_x0000_000B_dct1_PhyPSReq_WIDTH                 1
#define D18F2x9C_x0000_000B_dct1_PhyPSReq_MASK                  0x40000000
#define D18F2x9C_x0000_000B_dct1_DynModeChange_OFFSET           31
#define D18F2x9C_x0000_000B_dct1_DynModeChange_WIDTH            1
#define D18F2x9C_x0000_000B_dct1_DynModeChange_MASK             0x80000000

/// D18F2x9C_x0000_000B_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_22_0:23; ///<
    UINT32                                       PhySelfRefreshMode:1 ; ///<
    UINT32                                           Reserved_25_24:2 ; ///<
    UINT32                                                    PhyPS:1 ; ///<
    UINT32                                           Reserved_29_27:3 ; ///<
    UINT32                                                 PhyPSReq:1 ; ///<
    UINT32                                            DynModeChange:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_000B_dct1_STRUCT;

// **** D18F2x9C_x0000_000C_dct1 Register Definition ****
// Address
#define D18F2x9C_x0000_000C_dct1_ADDRESS                        0xc

// Type
#define D18F2x9C_x0000_000C_dct1_TYPE                           TYPE_D18F2x9C_dct1
// Field Data
#define D18F2x9C_x0000_000C_dct1_ChipSelTri_OFFSET              0
#define D18F2x9C_x0000_000C_dct1_ChipSelTri_WIDTH               8
#define D18F2x9C_x0000_000C_dct1_ChipSelTri_MASK                0xff
#define D18F2x9C_x0000_000C_dct1_ODTTri_OFFSET                  8
#define D18F2x9C_x0000_000C_dct1_ODTTri_WIDTH                   4
#define D18F2x9C_x0000_000C_dct1_ODTTri_MASK                    0xf00
#define D18F2x9C_x0000_000C_dct1_CKETri_OFFSET                  12
#define D18F2x9C_x0000_000C_dct1_CKETri_WIDTH                   4
#define D18F2x9C_x0000_000C_dct1_CKETri_MASK                    0xf000
#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxPad_OFFSET     16
#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxPad_WIDTH      5
#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxPad_MASK       0x1f0000
#define D18F2x9C_x0000_000C_dct1_FenceThresholdRxDll_OFFSET     21
#define D18F2x9C_x0000_000C_dct1_FenceThresholdRxDll_WIDTH      5
#define D18F2x9C_x0000_000C_dct1_FenceThresholdRxDll_MASK       0x3e00000
#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxDll_OFFSET     26
#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxDll_WIDTH      5
#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxDll_MASK       0x7c000000
#define D18F2x9C_x0000_000C_dct1_Reserved_31_31_OFFSET          31
#define D18F2x9C_x0000_000C_dct1_Reserved_31_31_WIDTH           1
#define D18F2x9C_x0000_000C_dct1_Reserved_31_31_MASK            0x80000000

/// D18F2x9C_x0000_000C_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                               ChipSelTri:8 ; ///<
    UINT32                                                   ODTTri:4 ; ///<
    UINT32                                                   CKETri:4 ; ///<
    UINT32                                      FenceThresholdTxPad:5 ; ///<
    UINT32                                      FenceThresholdRxDll:5 ; ///<
    UINT32                                      FenceThresholdTxDll:5 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_000C_dct1_STRUCT;

// **** D18F2x9C_x0000_000C_dct0 Register Definition ****
// Address
#define D18F2x9C_x0000_000C_dct0_ADDRESS                        0xc

// Type
#define D18F2x9C_x0000_000C_dct0_TYPE                           TYPE_D18F2x9C_dct0
// Field Data
#define D18F2x9C_x0000_000C_dct0_ChipSelTri_OFFSET              0
#define D18F2x9C_x0000_000C_dct0_ChipSelTri_WIDTH               8
#define D18F2x9C_x0000_000C_dct0_ChipSelTri_MASK                0xff
#define D18F2x9C_x0000_000C_dct0_ODTTri_OFFSET                  8
#define D18F2x9C_x0000_000C_dct0_ODTTri_WIDTH                   4
#define D18F2x9C_x0000_000C_dct0_ODTTri_MASK                    0xf00
#define D18F2x9C_x0000_000C_dct0_CKETri_OFFSET                  12
#define D18F2x9C_x0000_000C_dct0_CKETri_WIDTH                   4
#define D18F2x9C_x0000_000C_dct0_CKETri_MASK                    0xf000
#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxPad_OFFSET     16
#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxPad_WIDTH      5
#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxPad_MASK       0x1f0000
#define D18F2x9C_x0000_000C_dct0_FenceThresholdRxDll_OFFSET     21
#define D18F2x9C_x0000_000C_dct0_FenceThresholdRxDll_WIDTH      5
#define D18F2x9C_x0000_000C_dct0_FenceThresholdRxDll_MASK       0x3e00000
#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxDll_OFFSET     26
#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxDll_WIDTH      5
#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxDll_MASK       0x7c000000
#define D18F2x9C_x0000_000C_dct0_Reserved_31_31_OFFSET          31
#define D18F2x9C_x0000_000C_dct0_Reserved_31_31_WIDTH           1
#define D18F2x9C_x0000_000C_dct0_Reserved_31_31_MASK            0x80000000

/// D18F2x9C_x0000_000C_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                               ChipSelTri:8 ; ///<
    UINT32                                                   ODTTri:4 ; ///<
    UINT32                                                   CKETri:4 ; ///<
    UINT32                                      FenceThresholdTxPad:5 ; ///<
    UINT32                                      FenceThresholdRxDll:5 ; ///<
    UINT32                                      FenceThresholdTxDll:5 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_000C_dct0_STRUCT;

// **** D18F2x9C_x0000_000D_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_000D_dct0_mp1_ADDRESS                    0xd

// Type
#define D18F2x9C_x0000_000D_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_000D_dct0_mp1_TxMaxDurDllNoLock_OFFSET   0
#define D18F2x9C_x0000_000D_dct0_mp1_TxMaxDurDllNoLock_WIDTH    4
#define D18F2x9C_x0000_000D_dct0_mp1_TxMaxDurDllNoLock_MASK     0xf
#define D18F2x9C_x0000_000D_dct0_mp1_TxCPUpdPeriod_OFFSET       4
#define D18F2x9C_x0000_000D_dct0_mp1_TxCPUpdPeriod_WIDTH        3
#define D18F2x9C_x0000_000D_dct0_mp1_TxCPUpdPeriod_MASK         0x70
#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_7_7_OFFSET        7
#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_7_7_WIDTH         1
#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_7_7_MASK          0x80
#define D18F2x9C_x0000_000D_dct0_mp1_TxDLLWakeupTime_OFFSET     8
#define D18F2x9C_x0000_000D_dct0_mp1_TxDLLWakeupTime_WIDTH      2
#define D18F2x9C_x0000_000D_dct0_mp1_TxDLLWakeupTime_MASK       0x300
#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_000D_dct0_mp1_RxMaxDurDllNoLock_OFFSET   16
#define D18F2x9C_x0000_000D_dct0_mp1_RxMaxDurDllNoLock_WIDTH    4
#define D18F2x9C_x0000_000D_dct0_mp1_RxMaxDurDllNoLock_MASK     0xf0000
#define D18F2x9C_x0000_000D_dct0_mp1_RxCPUpdPeriod_OFFSET       20
#define D18F2x9C_x0000_000D_dct0_mp1_RxCPUpdPeriod_WIDTH        3
#define D18F2x9C_x0000_000D_dct0_mp1_RxCPUpdPeriod_MASK         0x700000
#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_23_23_OFFSET      23
#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_23_23_WIDTH       1
#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_23_23_MASK        0x800000
#define D18F2x9C_x0000_000D_dct0_mp1_RxDLLWakeupTime_OFFSET     24
#define D18F2x9C_x0000_000D_dct0_mp1_RxDLLWakeupTime_WIDTH      2
#define D18F2x9C_x0000_000D_dct0_mp1_RxDLLWakeupTime_MASK       0x3000000
#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_000D_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        TxMaxDurDllNoLock:4 ; ///<
    UINT32                                            TxCPUpdPeriod:3 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                          TxDLLWakeupTime:2 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                        RxMaxDurDllNoLock:4 ; ///<
    UINT32                                            RxCPUpdPeriod:3 ; ///<
    UINT32                                           Reserved_23_23:1 ; ///<
    UINT32                                          RxDLLWakeupTime:2 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_000D_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_000D_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_000D_dct1_mp1_ADDRESS                    0xd

// Type
#define D18F2x9C_x0000_000D_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_000D_dct1_mp1_TxMaxDurDllNoLock_OFFSET   0
#define D18F2x9C_x0000_000D_dct1_mp1_TxMaxDurDllNoLock_WIDTH    4
#define D18F2x9C_x0000_000D_dct1_mp1_TxMaxDurDllNoLock_MASK     0xf
#define D18F2x9C_x0000_000D_dct1_mp1_TxCPUpdPeriod_OFFSET       4
#define D18F2x9C_x0000_000D_dct1_mp1_TxCPUpdPeriod_WIDTH        3
#define D18F2x9C_x0000_000D_dct1_mp1_TxCPUpdPeriod_MASK         0x70
#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_7_7_OFFSET        7
#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_7_7_WIDTH         1
#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_7_7_MASK          0x80
#define D18F2x9C_x0000_000D_dct1_mp1_TxDLLWakeupTime_OFFSET     8
#define D18F2x9C_x0000_000D_dct1_mp1_TxDLLWakeupTime_WIDTH      2
#define D18F2x9C_x0000_000D_dct1_mp1_TxDLLWakeupTime_MASK       0x300
#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_000D_dct1_mp1_RxMaxDurDllNoLock_OFFSET   16
#define D18F2x9C_x0000_000D_dct1_mp1_RxMaxDurDllNoLock_WIDTH    4
#define D18F2x9C_x0000_000D_dct1_mp1_RxMaxDurDllNoLock_MASK     0xf0000
#define D18F2x9C_x0000_000D_dct1_mp1_RxCPUpdPeriod_OFFSET       20
#define D18F2x9C_x0000_000D_dct1_mp1_RxCPUpdPeriod_WIDTH        3
#define D18F2x9C_x0000_000D_dct1_mp1_RxCPUpdPeriod_MASK         0x700000
#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_23_23_OFFSET      23
#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_23_23_WIDTH       1
#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_23_23_MASK        0x800000
#define D18F2x9C_x0000_000D_dct1_mp1_RxDLLWakeupTime_OFFSET     24
#define D18F2x9C_x0000_000D_dct1_mp1_RxDLLWakeupTime_WIDTH      2
#define D18F2x9C_x0000_000D_dct1_mp1_RxDLLWakeupTime_MASK       0x3000000
#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_000D_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        TxMaxDurDllNoLock:4 ; ///<
    UINT32                                            TxCPUpdPeriod:3 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                          TxDLLWakeupTime:2 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                        RxMaxDurDllNoLock:4 ; ///<
    UINT32                                            RxCPUpdPeriod:3 ; ///<
    UINT32                                           Reserved_23_23:1 ; ///<
    UINT32                                          RxDLLWakeupTime:2 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_000D_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_000D_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_000D_dct0_mp0_ADDRESS                    0xd

// Type
#define D18F2x9C_x0000_000D_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_000D_dct0_mp0_TxMaxDurDllNoLock_OFFSET   0
#define D18F2x9C_x0000_000D_dct0_mp0_TxMaxDurDllNoLock_WIDTH    4
#define D18F2x9C_x0000_000D_dct0_mp0_TxMaxDurDllNoLock_MASK     0xf
#define D18F2x9C_x0000_000D_dct0_mp0_TxCPUpdPeriod_OFFSET       4
#define D18F2x9C_x0000_000D_dct0_mp0_TxCPUpdPeriod_WIDTH        3
#define D18F2x9C_x0000_000D_dct0_mp0_TxCPUpdPeriod_MASK         0x70
#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_7_7_OFFSET        7
#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_7_7_WIDTH         1
#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_7_7_MASK          0x80
#define D18F2x9C_x0000_000D_dct0_mp0_TxDLLWakeupTime_OFFSET     8
#define D18F2x9C_x0000_000D_dct0_mp0_TxDLLWakeupTime_WIDTH      2
#define D18F2x9C_x0000_000D_dct0_mp0_TxDLLWakeupTime_MASK       0x300
#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_000D_dct0_mp0_RxMaxDurDllNoLock_OFFSET   16
#define D18F2x9C_x0000_000D_dct0_mp0_RxMaxDurDllNoLock_WIDTH    4
#define D18F2x9C_x0000_000D_dct0_mp0_RxMaxDurDllNoLock_MASK     0xf0000
#define D18F2x9C_x0000_000D_dct0_mp0_RxCPUpdPeriod_OFFSET       20
#define D18F2x9C_x0000_000D_dct0_mp0_RxCPUpdPeriod_WIDTH        3
#define D18F2x9C_x0000_000D_dct0_mp0_RxCPUpdPeriod_MASK         0x700000
#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_23_23_OFFSET      23
#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_23_23_WIDTH       1
#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_23_23_MASK        0x800000
#define D18F2x9C_x0000_000D_dct0_mp0_RxDLLWakeupTime_OFFSET     24
#define D18F2x9C_x0000_000D_dct0_mp0_RxDLLWakeupTime_WIDTH      2
#define D18F2x9C_x0000_000D_dct0_mp0_RxDLLWakeupTime_MASK       0x3000000
#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_000D_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        TxMaxDurDllNoLock:4 ; ///<
    UINT32                                            TxCPUpdPeriod:3 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                          TxDLLWakeupTime:2 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                        RxMaxDurDllNoLock:4 ; ///<
    UINT32                                            RxCPUpdPeriod:3 ; ///<
    UINT32                                           Reserved_23_23:1 ; ///<
    UINT32                                          RxDLLWakeupTime:2 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_000D_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_000D_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_000D_dct1_mp0_ADDRESS                    0xd

// Type
#define D18F2x9C_x0000_000D_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_000D_dct1_mp0_TxMaxDurDllNoLock_OFFSET   0
#define D18F2x9C_x0000_000D_dct1_mp0_TxMaxDurDllNoLock_WIDTH    4
#define D18F2x9C_x0000_000D_dct1_mp0_TxMaxDurDllNoLock_MASK     0xf
#define D18F2x9C_x0000_000D_dct1_mp0_TxCPUpdPeriod_OFFSET       4
#define D18F2x9C_x0000_000D_dct1_mp0_TxCPUpdPeriod_WIDTH        3
#define D18F2x9C_x0000_000D_dct1_mp0_TxCPUpdPeriod_MASK         0x70
#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_7_7_OFFSET        7
#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_7_7_WIDTH         1
#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_7_7_MASK          0x80
#define D18F2x9C_x0000_000D_dct1_mp0_TxDLLWakeupTime_OFFSET     8
#define D18F2x9C_x0000_000D_dct1_mp0_TxDLLWakeupTime_WIDTH      2
#define D18F2x9C_x0000_000D_dct1_mp0_TxDLLWakeupTime_MASK       0x300
#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_000D_dct1_mp0_RxMaxDurDllNoLock_OFFSET   16
#define D18F2x9C_x0000_000D_dct1_mp0_RxMaxDurDllNoLock_WIDTH    4
#define D18F2x9C_x0000_000D_dct1_mp0_RxMaxDurDllNoLock_MASK     0xf0000
#define D18F2x9C_x0000_000D_dct1_mp0_RxCPUpdPeriod_OFFSET       20
#define D18F2x9C_x0000_000D_dct1_mp0_RxCPUpdPeriod_WIDTH        3
#define D18F2x9C_x0000_000D_dct1_mp0_RxCPUpdPeriod_MASK         0x700000
#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_23_23_OFFSET      23
#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_23_23_WIDTH       1
#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_23_23_MASK        0x800000
#define D18F2x9C_x0000_000D_dct1_mp0_RxDLLWakeupTime_OFFSET     24
#define D18F2x9C_x0000_000D_dct1_mp0_RxDLLWakeupTime_WIDTH      2
#define D18F2x9C_x0000_000D_dct1_mp0_RxDLLWakeupTime_MASK       0x3000000
#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_000D_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        TxMaxDurDllNoLock:4 ; ///<
    UINT32                                            TxCPUpdPeriod:3 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                          TxDLLWakeupTime:2 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                        RxMaxDurDllNoLock:4 ; ///<
    UINT32                                            RxCPUpdPeriod:3 ; ///<
    UINT32                                           Reserved_23_23:1 ; ///<
    UINT32                                          RxDLLWakeupTime:2 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_000D_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0010_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0010_dct0_mp1_ADDRESS                    0x10

// Type
#define D18F2x9C_x0000_0010_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0010_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0010_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0010_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0010_dct1_mp0_ADDRESS                    0x10

// Type
#define D18F2x9C_x0000_0010_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0010_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0010_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0010_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0010_dct0_mp0_ADDRESS                    0x10

// Type
#define D18F2x9C_x0000_0010_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0010_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0010_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0010_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0010_dct1_mp1_ADDRESS                    0x10

// Type
#define D18F2x9C_x0000_0010_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0010_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0010_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0011_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0011_dct1_mp0_ADDRESS                    0x11

// Type
#define D18F2x9C_x0000_0011_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0011_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0011_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0011_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0011_dct1_mp1_ADDRESS                    0x11

// Type
#define D18F2x9C_x0000_0011_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0011_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0011_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0011_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0011_dct0_mp0_ADDRESS                    0x11

// Type
#define D18F2x9C_x0000_0011_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0011_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0011_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0011_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0011_dct0_mp1_ADDRESS                    0x11

// Type
#define D18F2x9C_x0000_0011_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0011_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0011_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0013_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0013_dct1_mp1_ADDRESS                    0x13

// Type
#define D18F2x9C_x0000_0013_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0013_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0013_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0013_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0013_dct1_mp0_ADDRESS                    0x13

// Type
#define D18F2x9C_x0000_0013_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0013_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0013_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0013_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0013_dct0_mp0_ADDRESS                    0x13

// Type
#define D18F2x9C_x0000_0013_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0013_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0013_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0013_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0013_dct0_mp1_ADDRESS                    0x13

// Type
#define D18F2x9C_x0000_0013_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0013_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0013_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0014_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0014_dct1_mp0_ADDRESS                    0x14

// Type
#define D18F2x9C_x0000_0014_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0014_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0014_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0014_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0014_dct0_mp1_ADDRESS                    0x14

// Type
#define D18F2x9C_x0000_0014_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0014_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0014_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0014_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0014_dct0_mp0_ADDRESS                    0x14

// Type
#define D18F2x9C_x0000_0014_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0014_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0014_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0014_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0014_dct1_mp1_ADDRESS                    0x14

// Type
#define D18F2x9C_x0000_0014_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0014_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0014_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0016_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0016_dct0_mp0_ADDRESS                    0x16

// Type
#define D18F2x9C_x0000_0016_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0016_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0016_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0016_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0016_dct1_mp1_ADDRESS                    0x16

// Type
#define D18F2x9C_x0000_0016_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0016_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0016_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0016_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0016_dct1_mp0_ADDRESS                    0x16

// Type
#define D18F2x9C_x0000_0016_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0016_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0016_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0016_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0016_dct0_mp1_ADDRESS                    0x16

// Type
#define D18F2x9C_x0000_0016_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0016_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0016_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0017_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0017_dct0_mp1_ADDRESS                    0x17

// Type
#define D18F2x9C_x0000_0017_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0017_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0017_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0017_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0017_dct0_mp0_ADDRESS                    0x17

// Type
#define D18F2x9C_x0000_0017_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0017_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0017_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0017_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0017_dct1_mp1_ADDRESS                    0x17

// Type
#define D18F2x9C_x0000_0017_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0017_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0017_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0017_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0017_dct1_mp0_ADDRESS                    0x17

// Type
#define D18F2x9C_x0000_0017_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0017_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0017_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0019_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0019_dct1_mp0_ADDRESS                    0x19

// Type
#define D18F2x9C_x0000_0019_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0019_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0019_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0019_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0019_dct0_mp0_ADDRESS                    0x19

// Type
#define D18F2x9C_x0000_0019_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0019_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0019_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0019_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0019_dct0_mp1_ADDRESS                    0x19

// Type
#define D18F2x9C_x0000_0019_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0019_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0019_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0019_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0019_dct1_mp1_ADDRESS                    0x19

// Type
#define D18F2x9C_x0000_0019_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0019_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0019_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_001A_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_001A_dct1_mp1_ADDRESS                    0x1a

// Type
#define D18F2x9C_x0000_001A_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_001A_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_001A_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_001A_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_001A_dct1_mp0_ADDRESS                    0x1a

// Type
#define D18F2x9C_x0000_001A_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_001A_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_001A_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_001A_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_001A_dct0_mp1_ADDRESS                    0x1a

// Type
#define D18F2x9C_x0000_001A_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_001A_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_001A_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_001A_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_001A_dct0_mp0_ADDRESS                    0x1a

// Type
#define D18F2x9C_x0000_001A_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_001A_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_001A_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0020_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0020_dct0_mp1_ADDRESS                    0x20

// Type
#define D18F2x9C_x0000_0020_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0020_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0020_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0020_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0020_dct1_mp0_ADDRESS                    0x20

// Type
#define D18F2x9C_x0000_0020_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0020_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0020_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0020_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0020_dct1_mp1_ADDRESS                    0x20

// Type
#define D18F2x9C_x0000_0020_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0020_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0020_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0020_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0020_dct0_mp0_ADDRESS                    0x20

// Type
#define D18F2x9C_x0000_0020_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0020_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0020_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0021_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0021_dct0_mp1_ADDRESS                    0x21

// Type
#define D18F2x9C_x0000_0021_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0021_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0021_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0021_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0021_dct1_mp0_ADDRESS                    0x21

// Type
#define D18F2x9C_x0000_0021_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0021_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0021_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0021_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0021_dct1_mp1_ADDRESS                    0x21

// Type
#define D18F2x9C_x0000_0021_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0021_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0021_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0021_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0021_dct0_mp0_ADDRESS                    0x21

// Type
#define D18F2x9C_x0000_0021_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0021_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0021_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0023_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0023_dct0_mp1_ADDRESS                    0x23

// Type
#define D18F2x9C_x0000_0023_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0023_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0023_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0023_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0023_dct1_mp0_ADDRESS                    0x23

// Type
#define D18F2x9C_x0000_0023_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0023_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0023_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0023_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0023_dct1_mp1_ADDRESS                    0x23

// Type
#define D18F2x9C_x0000_0023_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0023_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0023_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0023_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0023_dct0_mp0_ADDRESS                    0x23

// Type
#define D18F2x9C_x0000_0023_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0023_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0023_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0024_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0024_dct1_mp1_ADDRESS                    0x24

// Type
#define D18F2x9C_x0000_0024_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0024_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0024_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0024_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0024_dct1_mp0_ADDRESS                    0x24

// Type
#define D18F2x9C_x0000_0024_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0024_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0024_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0024_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0024_dct0_mp1_ADDRESS                    0x24

// Type
#define D18F2x9C_x0000_0024_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0024_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0024_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0024_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0024_dct0_mp0_ADDRESS                    0x24

// Type
#define D18F2x9C_x0000_0024_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0024_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0024_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0026_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0026_dct1_mp0_ADDRESS                    0x26

// Type
#define D18F2x9C_x0000_0026_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0026_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0026_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0026_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0026_dct0_mp0_ADDRESS                    0x26

// Type
#define D18F2x9C_x0000_0026_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0026_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0026_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0026_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0026_dct1_mp1_ADDRESS                    0x26

// Type
#define D18F2x9C_x0000_0026_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0026_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0026_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0026_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0026_dct0_mp1_ADDRESS                    0x26

// Type
#define D18F2x9C_x0000_0026_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0026_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0026_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0027_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0027_dct0_mp1_ADDRESS                    0x27

// Type
#define D18F2x9C_x0000_0027_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0027_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0027_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0027_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0027_dct1_mp0_ADDRESS                    0x27

// Type
#define D18F2x9C_x0000_0027_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0027_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0027_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0027_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0027_dct0_mp0_ADDRESS                    0x27

// Type
#define D18F2x9C_x0000_0027_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0027_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0027_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0027_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0027_dct1_mp1_ADDRESS                    0x27

// Type
#define D18F2x9C_x0000_0027_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0027_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0027_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0029_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0029_dct0_mp0_ADDRESS                    0x29

// Type
#define D18F2x9C_x0000_0029_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0029_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0029_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0029_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0029_dct0_mp1_ADDRESS                    0x29

// Type
#define D18F2x9C_x0000_0029_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0029_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0029_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0029_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0029_dct1_mp0_ADDRESS                    0x29

// Type
#define D18F2x9C_x0000_0029_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0029_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0029_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0029_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0029_dct1_mp1_ADDRESS                    0x29

// Type
#define D18F2x9C_x0000_0029_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_0029_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0029_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_002A_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_002A_dct1_mp1_ADDRESS                    0x2a

// Type
#define D18F2x9C_x0000_002A_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_002A_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_002A_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_002A_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_002A_dct0_mp0_ADDRESS                    0x2a

// Type
#define D18F2x9C_x0000_002A_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_002A_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_002A_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_002A_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_002A_dct1_mp0_ADDRESS                    0x2a

// Type
#define D18F2x9C_x0000_002A_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_002A_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_002A_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_002A_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_002A_dct0_mp1_ADDRESS                    0x2a

// Type
#define D18F2x9C_x0000_002A_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_15_10_OFFSET      10
#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_15_10_WIDTH       6
#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_15_10_MASK        0xfc00
#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_31_26_OFFSET      26
#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_31_26_WIDTH       6
#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_31_26_MASK        0xfc000000

/// D18F2x9C_x0000_002A_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
    UINT32                                           Reserved_15_10:6 ; ///<
    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
    UINT32                                           Reserved_31_26:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_002A_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0030_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0030_dct1_mp1_ADDRESS                    0x30

// Type
#define D18F2x9C_x0000_0030_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0030_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0030_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0030_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0030_dct0_mp1_ADDRESS                    0x30

// Type
#define D18F2x9C_x0000_0030_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0030_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0030_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0030_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0030_dct0_mp0_ADDRESS                    0x30

// Type
#define D18F2x9C_x0000_0030_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0030_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0030_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0030_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0030_dct1_mp0_ADDRESS                    0x30

// Type
#define D18F2x9C_x0000_0030_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0030_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0030_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0031_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0031_dct0_mp0_ADDRESS                    0x31

// Type
#define D18F2x9C_x0000_0031_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0031_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0031_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0031_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0031_dct0_mp1_ADDRESS                    0x31

// Type
#define D18F2x9C_x0000_0031_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0031_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0031_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0031_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0031_dct1_mp0_ADDRESS                    0x31

// Type
#define D18F2x9C_x0000_0031_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0031_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0031_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0031_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0031_dct1_mp1_ADDRESS                    0x31

// Type
#define D18F2x9C_x0000_0031_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0031_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0031_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0033_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0033_dct1_mp1_ADDRESS                    0x33

// Type
#define D18F2x9C_x0000_0033_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0033_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0033_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0033_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0033_dct1_mp0_ADDRESS                    0x33

// Type
#define D18F2x9C_x0000_0033_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0033_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0033_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0033_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0033_dct0_mp0_ADDRESS                    0x33

// Type
#define D18F2x9C_x0000_0033_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0033_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0033_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0033_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0033_dct0_mp1_ADDRESS                    0x33

// Type
#define D18F2x9C_x0000_0033_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0033_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0033_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0034_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0034_dct0_mp0_ADDRESS                    0x34

// Type
#define D18F2x9C_x0000_0034_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0034_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0034_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0034_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0034_dct1_mp1_ADDRESS                    0x34

// Type
#define D18F2x9C_x0000_0034_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0034_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0034_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0034_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0034_dct1_mp0_ADDRESS                    0x34

// Type
#define D18F2x9C_x0000_0034_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0034_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0034_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0034_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0034_dct0_mp1_ADDRESS                    0x34

// Type
#define D18F2x9C_x0000_0034_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0034_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0034_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0036_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0036_dct1_mp1_ADDRESS                    0x36

// Type
#define D18F2x9C_x0000_0036_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0036_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0036_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0036_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0036_dct0_mp1_ADDRESS                    0x36

// Type
#define D18F2x9C_x0000_0036_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0036_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0036_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0036_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0036_dct1_mp0_ADDRESS                    0x36

// Type
#define D18F2x9C_x0000_0036_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0036_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0036_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0036_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0036_dct0_mp0_ADDRESS                    0x36

// Type
#define D18F2x9C_x0000_0036_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0036_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0036_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0037_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0037_dct1_mp1_ADDRESS                    0x37

// Type
#define D18F2x9C_x0000_0037_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0037_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0037_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0037_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0037_dct0_mp1_ADDRESS                    0x37

// Type
#define D18F2x9C_x0000_0037_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0037_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0037_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0037_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0037_dct0_mp0_ADDRESS                    0x37

// Type
#define D18F2x9C_x0000_0037_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0037_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0037_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0037_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0037_dct1_mp0_ADDRESS                    0x37

// Type
#define D18F2x9C_x0000_0037_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0037_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0037_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0039_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0039_dct0_mp1_ADDRESS                    0x39

// Type
#define D18F2x9C_x0000_0039_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0039_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0039_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0039_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0039_dct0_mp0_ADDRESS                    0x39

// Type
#define D18F2x9C_x0000_0039_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0039_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0039_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0039_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0039_dct1_mp0_ADDRESS                    0x39

// Type
#define D18F2x9C_x0000_0039_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0039_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0039_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0039_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0039_dct1_mp1_ADDRESS                    0x39

// Type
#define D18F2x9C_x0000_0039_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0039_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0039_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_003A_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_003A_dct1_mp0_ADDRESS                    0x3a

// Type
#define D18F2x9C_x0000_003A_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_003A_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_003A_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_003A_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_003A_dct0_mp1_ADDRESS                    0x3a

// Type
#define D18F2x9C_x0000_003A_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_003A_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_003A_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_003A_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_003A_dct0_mp0_ADDRESS                    0x3a

// Type
#define D18F2x9C_x0000_003A_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_003A_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_003A_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_003A_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_003A_dct1_mp1_ADDRESS                    0x3a

// Type
#define D18F2x9C_x0000_003A_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_003A_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_003A_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0040_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0040_dct0_mp1_ADDRESS                    0x40

// Type
#define D18F2x9C_x0000_0040_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0040_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0040_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0040_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0040_dct1_mp1_ADDRESS                    0x40

// Type
#define D18F2x9C_x0000_0040_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0040_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0040_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0040_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0040_dct1_mp0_ADDRESS                    0x40

// Type
#define D18F2x9C_x0000_0040_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0040_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0040_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0040_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0040_dct0_mp0_ADDRESS                    0x40

// Type
#define D18F2x9C_x0000_0040_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0040_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0040_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0041_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0041_dct1_mp1_ADDRESS                    0x41

// Type
#define D18F2x9C_x0000_0041_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0041_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0041_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0041_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0041_dct0_mp0_ADDRESS                    0x41

// Type
#define D18F2x9C_x0000_0041_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0041_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0041_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0041_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0041_dct1_mp0_ADDRESS                    0x41

// Type
#define D18F2x9C_x0000_0041_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0041_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0041_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0041_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0041_dct0_mp1_ADDRESS                    0x41

// Type
#define D18F2x9C_x0000_0041_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0041_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0041_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0043_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0043_dct1_mp0_ADDRESS                    0x43

// Type
#define D18F2x9C_x0000_0043_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0043_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0043_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0043_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0043_dct0_mp1_ADDRESS                    0x43

// Type
#define D18F2x9C_x0000_0043_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0043_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0043_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0043_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0043_dct1_mp1_ADDRESS                    0x43

// Type
#define D18F2x9C_x0000_0043_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0043_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0043_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0043_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0043_dct0_mp0_ADDRESS                    0x43

// Type
#define D18F2x9C_x0000_0043_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0043_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0043_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0044_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0044_dct0_mp0_ADDRESS                    0x44

// Type
#define D18F2x9C_x0000_0044_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0044_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0044_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0044_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0044_dct1_mp0_ADDRESS                    0x44

// Type
#define D18F2x9C_x0000_0044_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0044_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0044_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0044_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0044_dct1_mp1_ADDRESS                    0x44

// Type
#define D18F2x9C_x0000_0044_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0044_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0044_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0044_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0044_dct0_mp1_ADDRESS                    0x44

// Type
#define D18F2x9C_x0000_0044_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0044_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0044_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0046_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0046_dct1_mp1_ADDRESS                    0x46

// Type
#define D18F2x9C_x0000_0046_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0046_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0046_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0046_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0046_dct1_mp0_ADDRESS                    0x46

// Type
#define D18F2x9C_x0000_0046_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0046_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0046_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0046_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0046_dct0_mp1_ADDRESS                    0x46

// Type
#define D18F2x9C_x0000_0046_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0046_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0046_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0046_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0046_dct0_mp0_ADDRESS                    0x46

// Type
#define D18F2x9C_x0000_0046_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0046_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0046_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0047_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0047_dct1_mp1_ADDRESS                    0x47

// Type
#define D18F2x9C_x0000_0047_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0047_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0047_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0047_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0047_dct1_mp0_ADDRESS                    0x47

// Type
#define D18F2x9C_x0000_0047_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0047_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0047_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0047_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0047_dct0_mp1_ADDRESS                    0x47

// Type
#define D18F2x9C_x0000_0047_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0047_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0047_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0047_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0047_dct0_mp0_ADDRESS                    0x47

// Type
#define D18F2x9C_x0000_0047_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0047_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0047_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0049_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0049_dct0_mp1_ADDRESS                    0x49

// Type
#define D18F2x9C_x0000_0049_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0049_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0049_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0049_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0049_dct0_mp0_ADDRESS                    0x49

// Type
#define D18F2x9C_x0000_0049_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0049_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0049_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0049_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0049_dct1_mp1_ADDRESS                    0x49

// Type
#define D18F2x9C_x0000_0049_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0049_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0049_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0049_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0049_dct1_mp0_ADDRESS                    0x49

// Type
#define D18F2x9C_x0000_0049_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_0049_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0049_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_004A_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_004A_dct0_mp0_ADDRESS                    0x4a

// Type
#define D18F2x9C_x0000_004A_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_004A_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_004A_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_004A_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_004A_dct1_mp1_ADDRESS                    0x4a

// Type
#define D18F2x9C_x0000_004A_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_004A_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_004A_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_004A_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_004A_dct1_mp0_ADDRESS                    0x4a

// Type
#define D18F2x9C_x0000_004A_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_004A_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_004A_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_004A_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_004A_dct0_mp1_ADDRESS                    0x4a

// Type
#define D18F2x9C_x0000_004A_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly_OFFSET        0
#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly_WIDTH         5
#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly_MASK          0x1f
#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly_OFFSET       5
#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly_WIDTH        3
#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly_MASK         0xe0
#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_12_8_OFFSET       8
#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_12_8_WIDTH        5
#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_12_8_MASK         0x1f00
#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_15_13_OFFSET      13
#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_15_13_WIDTH       3
#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_15_13_MASK        0xe000
#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly1_OFFSET       16
#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly1_WIDTH        5
#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly1_OFFSET      21
#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly1_WIDTH       3
#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_28_24_OFFSET      24
#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_28_24_WIDTH       5
#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_28_24_MASK        0x1f000000
#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_31_29_OFFSET      29
#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_31_29_WIDTH       3
#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_31_29_MASK        0xe0000000

/// D18F2x9C_x0000_004A_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDqsFineDly:5 ; ///<
    UINT32                                            WrDqsGrossDly:3 ; ///<
    UINT32                                            Reserved_12_8:5 ; ///<
    UINT32                                           Reserved_15_13:3 ; ///<
    UINT32                                            WrDqsFineDly1:5 ; ///<
    UINT32                                           WrDqsGrossDly1:3 ; ///<
    UINT32                                           Reserved_28_24:5 ; ///<
    UINT32                                           Reserved_31_29:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_004A_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0050_dct0 Register Definition ****
// Address
#define D18F2x9C_x0000_0050_dct0_ADDRESS                        0x50

// Type
#define D18F2x9C_x0000_0050_dct0_TYPE                           TYPE_D18F2x9C_dct0
// Field Data
#define D18F2x9C_x0000_0050_dct0_PhRecFineDly_OFFSET            0
#define D18F2x9C_x0000_0050_dct0_PhRecFineDly_WIDTH             5
#define D18F2x9C_x0000_0050_dct0_PhRecFineDly_MASK              0x1f
#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly_OFFSET           5
#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly_WIDTH            2
#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly_MASK             0x60
#define D18F2x9C_x0000_0050_dct0_Reserved_7_7_OFFSET            7
#define D18F2x9C_x0000_0050_dct0_Reserved_7_7_WIDTH             1
#define D18F2x9C_x0000_0050_dct0_Reserved_7_7_MASK              0x80
#define D18F2x9C_x0000_0050_dct0_PhRecFineDly8_12_OFFSET        8
#define D18F2x9C_x0000_0050_dct0_PhRecFineDly8_12_WIDTH         5
#define D18F2x9C_x0000_0050_dct0_PhRecFineDly8_12_MASK          0x1f00
#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly13_14_OFFSET      13
#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly13_14_WIDTH       2
#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly13_14_MASK        0x6000
#define D18F2x9C_x0000_0050_dct0_Reserved_15_15_OFFSET          15
#define D18F2x9C_x0000_0050_dct0_Reserved_15_15_WIDTH           1
#define D18F2x9C_x0000_0050_dct0_Reserved_15_15_MASK            0x8000
#define D18F2x9C_x0000_0050_dct0_PhRecFineDly16_20_OFFSET       16
#define D18F2x9C_x0000_0050_dct0_PhRecFineDly16_20_WIDTH        5
#define D18F2x9C_x0000_0050_dct0_PhRecFineDly16_20_MASK         0x1f0000
#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly21_22_OFFSET      21
#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly21_22_WIDTH       2
#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly21_22_MASK        0x600000
#define D18F2x9C_x0000_0050_dct0_Reserved_23_23_OFFSET          23
#define D18F2x9C_x0000_0050_dct0_Reserved_23_23_WIDTH           1
#define D18F2x9C_x0000_0050_dct0_Reserved_23_23_MASK            0x800000
#define D18F2x9C_x0000_0050_dct0_PhRecFineDly24_28_OFFSET       24
#define D18F2x9C_x0000_0050_dct0_PhRecFineDly24_28_WIDTH        5
#define D18F2x9C_x0000_0050_dct0_PhRecFineDly24_28_MASK         0x1f000000
#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly29_30_OFFSET      29
#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly29_30_WIDTH       2
#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly29_30_MASK        0x60000000
#define D18F2x9C_x0000_0050_dct0_Reserved_31_31_OFFSET          31
#define D18F2x9C_x0000_0050_dct0_Reserved_31_31_WIDTH           1
#define D18F2x9C_x0000_0050_dct0_Reserved_31_31_MASK            0x80000000

/// D18F2x9C_x0000_0050_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             PhRecFineDly:5 ; ///<
    UINT32                                            PhRecGrossDly:2 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                         PhRecFineDly8_12:5 ; ///<
    UINT32                                       PhRecGrossDly13_14:2 ; ///<
    UINT32                                           Reserved_15_15:1 ; ///<
    UINT32                                        PhRecFineDly16_20:5 ; ///<
    UINT32                                       PhRecGrossDly21_22:2 ; ///<
    UINT32                                           Reserved_23_23:1 ; ///<
    UINT32                                        PhRecFineDly24_28:5 ; ///<
    UINT32                                       PhRecGrossDly29_30:2 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0050_dct0_STRUCT;

// **** D18F2x9C_x0000_0050_dct1 Register Definition ****
// Address
#define D18F2x9C_x0000_0050_dct1_ADDRESS                        0x50

// Type
#define D18F2x9C_x0000_0050_dct1_TYPE                           TYPE_D18F2x9C_dct1
// Field Data
#define D18F2x9C_x0000_0050_dct1_PhRecFineDly_OFFSET            0
#define D18F2x9C_x0000_0050_dct1_PhRecFineDly_WIDTH             5
#define D18F2x9C_x0000_0050_dct1_PhRecFineDly_MASK              0x1f
#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly_OFFSET           5
#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly_WIDTH            2
#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly_MASK             0x60
#define D18F2x9C_x0000_0050_dct1_Reserved_7_7_OFFSET            7
#define D18F2x9C_x0000_0050_dct1_Reserved_7_7_WIDTH             1
#define D18F2x9C_x0000_0050_dct1_Reserved_7_7_MASK              0x80
#define D18F2x9C_x0000_0050_dct1_PhRecFineDly8_12_OFFSET        8
#define D18F2x9C_x0000_0050_dct1_PhRecFineDly8_12_WIDTH         5
#define D18F2x9C_x0000_0050_dct1_PhRecFineDly8_12_MASK          0x1f00
#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly13_14_OFFSET      13
#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly13_14_WIDTH       2
#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly13_14_MASK        0x6000
#define D18F2x9C_x0000_0050_dct1_Reserved_15_15_OFFSET          15
#define D18F2x9C_x0000_0050_dct1_Reserved_15_15_WIDTH           1
#define D18F2x9C_x0000_0050_dct1_Reserved_15_15_MASK            0x8000
#define D18F2x9C_x0000_0050_dct1_PhRecFineDly16_20_OFFSET       16
#define D18F2x9C_x0000_0050_dct1_PhRecFineDly16_20_WIDTH        5
#define D18F2x9C_x0000_0050_dct1_PhRecFineDly16_20_MASK         0x1f0000
#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly21_22_OFFSET      21
#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly21_22_WIDTH       2
#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly21_22_MASK        0x600000
#define D18F2x9C_x0000_0050_dct1_Reserved_23_23_OFFSET          23
#define D18F2x9C_x0000_0050_dct1_Reserved_23_23_WIDTH           1
#define D18F2x9C_x0000_0050_dct1_Reserved_23_23_MASK            0x800000
#define D18F2x9C_x0000_0050_dct1_PhRecFineDly24_28_OFFSET       24
#define D18F2x9C_x0000_0050_dct1_PhRecFineDly24_28_WIDTH        5
#define D18F2x9C_x0000_0050_dct1_PhRecFineDly24_28_MASK         0x1f000000
#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly29_30_OFFSET      29
#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly29_30_WIDTH       2
#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly29_30_MASK        0x60000000
#define D18F2x9C_x0000_0050_dct1_Reserved_31_31_OFFSET          31
#define D18F2x9C_x0000_0050_dct1_Reserved_31_31_WIDTH           1
#define D18F2x9C_x0000_0050_dct1_Reserved_31_31_MASK            0x80000000

/// D18F2x9C_x0000_0050_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             PhRecFineDly:5 ; ///<
    UINT32                                            PhRecGrossDly:2 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                         PhRecFineDly8_12:5 ; ///<
    UINT32                                       PhRecGrossDly13_14:2 ; ///<
    UINT32                                           Reserved_15_15:1 ; ///<
    UINT32                                        PhRecFineDly16_20:5 ; ///<
    UINT32                                       PhRecGrossDly21_22:2 ; ///<
    UINT32                                           Reserved_23_23:1 ; ///<
    UINT32                                        PhRecFineDly24_28:5 ; ///<
    UINT32                                       PhRecGrossDly29_30:2 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0050_dct1_STRUCT;

// **** D18F2x9C_x0000_0051_dct1 Register Definition ****
// Address
#define D18F2x9C_x0000_0051_dct1_ADDRESS                        0x51

// Type
#define D18F2x9C_x0000_0051_dct1_TYPE                           TYPE_D18F2x9C_dct1
// Field Data
#define D18F2x9C_x0000_0051_dct1_PhRecFineDly_OFFSET            0
#define D18F2x9C_x0000_0051_dct1_PhRecFineDly_WIDTH             5
#define D18F2x9C_x0000_0051_dct1_PhRecFineDly_MASK              0x1f
#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly_OFFSET           5
#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly_WIDTH            2
#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly_MASK             0x60
#define D18F2x9C_x0000_0051_dct1_Reserved_7_7_OFFSET            7
#define D18F2x9C_x0000_0051_dct1_Reserved_7_7_WIDTH             1
#define D18F2x9C_x0000_0051_dct1_Reserved_7_7_MASK              0x80
#define D18F2x9C_x0000_0051_dct1_PhRecFineDly8_12_OFFSET        8
#define D18F2x9C_x0000_0051_dct1_PhRecFineDly8_12_WIDTH         5
#define D18F2x9C_x0000_0051_dct1_PhRecFineDly8_12_MASK          0x1f00
#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly13_14_OFFSET      13
#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly13_14_WIDTH       2
#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly13_14_MASK        0x6000
#define D18F2x9C_x0000_0051_dct1_Reserved_15_15_OFFSET          15
#define D18F2x9C_x0000_0051_dct1_Reserved_15_15_WIDTH           1
#define D18F2x9C_x0000_0051_dct1_Reserved_15_15_MASK            0x8000
#define D18F2x9C_x0000_0051_dct1_PhRecFineDly16_20_OFFSET       16
#define D18F2x9C_x0000_0051_dct1_PhRecFineDly16_20_WIDTH        5
#define D18F2x9C_x0000_0051_dct1_PhRecFineDly16_20_MASK         0x1f0000
#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly21_22_OFFSET      21
#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly21_22_WIDTH       2
#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly21_22_MASK        0x600000
#define D18F2x9C_x0000_0051_dct1_Reserved_23_23_OFFSET          23
#define D18F2x9C_x0000_0051_dct1_Reserved_23_23_WIDTH           1
#define D18F2x9C_x0000_0051_dct1_Reserved_23_23_MASK            0x800000
#define D18F2x9C_x0000_0051_dct1_PhRecFineDly24_28_OFFSET       24
#define D18F2x9C_x0000_0051_dct1_PhRecFineDly24_28_WIDTH        5
#define D18F2x9C_x0000_0051_dct1_PhRecFineDly24_28_MASK         0x1f000000
#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly29_30_OFFSET      29
#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly29_30_WIDTH       2
#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly29_30_MASK        0x60000000
#define D18F2x9C_x0000_0051_dct1_Reserved_31_31_OFFSET          31
#define D18F2x9C_x0000_0051_dct1_Reserved_31_31_WIDTH           1
#define D18F2x9C_x0000_0051_dct1_Reserved_31_31_MASK            0x80000000

/// D18F2x9C_x0000_0051_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             PhRecFineDly:5 ; ///<
    UINT32                                            PhRecGrossDly:2 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                         PhRecFineDly8_12:5 ; ///<
    UINT32                                       PhRecGrossDly13_14:2 ; ///<
    UINT32                                           Reserved_15_15:1 ; ///<
    UINT32                                        PhRecFineDly16_20:5 ; ///<
    UINT32                                       PhRecGrossDly21_22:2 ; ///<
    UINT32                                           Reserved_23_23:1 ; ///<
    UINT32                                        PhRecFineDly24_28:5 ; ///<
    UINT32                                       PhRecGrossDly29_30:2 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0051_dct1_STRUCT;

// **** D18F2x9C_x0000_0051_dct0 Register Definition ****
// Address
#define D18F2x9C_x0000_0051_dct0_ADDRESS                        0x51

// Type
#define D18F2x9C_x0000_0051_dct0_TYPE                           TYPE_D18F2x9C_dct0
// Field Data
#define D18F2x9C_x0000_0051_dct0_PhRecFineDly_OFFSET            0
#define D18F2x9C_x0000_0051_dct0_PhRecFineDly_WIDTH             5
#define D18F2x9C_x0000_0051_dct0_PhRecFineDly_MASK              0x1f
#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly_OFFSET           5
#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly_WIDTH            2
#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly_MASK             0x60
#define D18F2x9C_x0000_0051_dct0_Reserved_7_7_OFFSET            7
#define D18F2x9C_x0000_0051_dct0_Reserved_7_7_WIDTH             1
#define D18F2x9C_x0000_0051_dct0_Reserved_7_7_MASK              0x80
#define D18F2x9C_x0000_0051_dct0_PhRecFineDly8_12_OFFSET        8
#define D18F2x9C_x0000_0051_dct0_PhRecFineDly8_12_WIDTH         5
#define D18F2x9C_x0000_0051_dct0_PhRecFineDly8_12_MASK          0x1f00
#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly13_14_OFFSET      13
#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly13_14_WIDTH       2
#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly13_14_MASK        0x6000
#define D18F2x9C_x0000_0051_dct0_Reserved_15_15_OFFSET          15
#define D18F2x9C_x0000_0051_dct0_Reserved_15_15_WIDTH           1
#define D18F2x9C_x0000_0051_dct0_Reserved_15_15_MASK            0x8000
#define D18F2x9C_x0000_0051_dct0_PhRecFineDly16_20_OFFSET       16
#define D18F2x9C_x0000_0051_dct0_PhRecFineDly16_20_WIDTH        5
#define D18F2x9C_x0000_0051_dct0_PhRecFineDly16_20_MASK         0x1f0000
#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly21_22_OFFSET      21
#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly21_22_WIDTH       2
#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly21_22_MASK        0x600000
#define D18F2x9C_x0000_0051_dct0_Reserved_23_23_OFFSET          23
#define D18F2x9C_x0000_0051_dct0_Reserved_23_23_WIDTH           1
#define D18F2x9C_x0000_0051_dct0_Reserved_23_23_MASK            0x800000
#define D18F2x9C_x0000_0051_dct0_PhRecFineDly24_28_OFFSET       24
#define D18F2x9C_x0000_0051_dct0_PhRecFineDly24_28_WIDTH        5
#define D18F2x9C_x0000_0051_dct0_PhRecFineDly24_28_MASK         0x1f000000
#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly29_30_OFFSET      29
#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly29_30_WIDTH       2
#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly29_30_MASK        0x60000000
#define D18F2x9C_x0000_0051_dct0_Reserved_31_31_OFFSET          31
#define D18F2x9C_x0000_0051_dct0_Reserved_31_31_WIDTH           1
#define D18F2x9C_x0000_0051_dct0_Reserved_31_31_MASK            0x80000000

/// D18F2x9C_x0000_0051_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             PhRecFineDly:5 ; ///<
    UINT32                                            PhRecGrossDly:2 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                         PhRecFineDly8_12:5 ; ///<
    UINT32                                       PhRecGrossDly13_14:2 ; ///<
    UINT32                                           Reserved_15_15:1 ; ///<
    UINT32                                        PhRecFineDly16_20:5 ; ///<
    UINT32                                       PhRecGrossDly21_22:2 ; ///<
    UINT32                                           Reserved_23_23:1 ; ///<
    UINT32                                        PhRecFineDly24_28:5 ; ///<
    UINT32                                       PhRecGrossDly29_30:2 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0051_dct0_STRUCT;

// **** D18F2x9C_x0000_0101_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0101_dct0_mp1_ADDRESS                    0x101

// Type
#define D18F2x9C_x0000_0101_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0101_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0101_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0101_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0101_dct1_mp1_ADDRESS                    0x101

// Type
#define D18F2x9C_x0000_0101_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0101_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0101_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0101_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0101_dct1_mp0_ADDRESS                    0x101

// Type
#define D18F2x9C_x0000_0101_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0101_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0101_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0101_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0101_dct0_mp0_ADDRESS                    0x101

// Type
#define D18F2x9C_x0000_0101_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0101_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0101_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0102_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0102_dct1_mp1_ADDRESS                    0x102

// Type
#define D18F2x9C_x0000_0102_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0102_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0102_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0102_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0102_dct1_mp0_ADDRESS                    0x102

// Type
#define D18F2x9C_x0000_0102_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0102_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0102_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0102_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0102_dct0_mp0_ADDRESS                    0x102

// Type
#define D18F2x9C_x0000_0102_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0102_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0102_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0102_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0102_dct0_mp1_ADDRESS                    0x102

// Type
#define D18F2x9C_x0000_0102_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0102_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0102_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0105_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0105_dct1_mp1_ADDRESS                    0x105

// Type
#define D18F2x9C_x0000_0105_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0105_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0105_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0105_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0105_dct0_mp1_ADDRESS                    0x105

// Type
#define D18F2x9C_x0000_0105_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0105_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0105_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0105_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0105_dct0_mp0_ADDRESS                    0x105

// Type
#define D18F2x9C_x0000_0105_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0105_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0105_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0105_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0105_dct1_mp0_ADDRESS                    0x105

// Type
#define D18F2x9C_x0000_0105_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0105_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0105_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0106_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0106_dct0_mp1_ADDRESS                    0x106

// Type
#define D18F2x9C_x0000_0106_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0106_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0106_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0106_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0106_dct1_mp0_ADDRESS                    0x106

// Type
#define D18F2x9C_x0000_0106_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0106_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0106_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0106_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0106_dct0_mp0_ADDRESS                    0x106

// Type
#define D18F2x9C_x0000_0106_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0106_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0106_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0106_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0106_dct1_mp1_ADDRESS                    0x106

// Type
#define D18F2x9C_x0000_0106_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0106_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0106_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0201_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0201_dct0_mp1_ADDRESS                    0x201

// Type
#define D18F2x9C_x0000_0201_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0201_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0201_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0201_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0201_dct1_mp0_ADDRESS                    0x201

// Type
#define D18F2x9C_x0000_0201_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0201_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0201_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0201_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0201_dct1_mp1_ADDRESS                    0x201

// Type
#define D18F2x9C_x0000_0201_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0201_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0201_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0201_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0201_dct0_mp0_ADDRESS                    0x201

// Type
#define D18F2x9C_x0000_0201_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0201_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0201_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0202_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0202_dct1_mp1_ADDRESS                    0x202

// Type
#define D18F2x9C_x0000_0202_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0202_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0202_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0202_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0202_dct1_mp0_ADDRESS                    0x202

// Type
#define D18F2x9C_x0000_0202_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0202_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0202_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0202_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0202_dct0_mp1_ADDRESS                    0x202

// Type
#define D18F2x9C_x0000_0202_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0202_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0202_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0202_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0202_dct0_mp0_ADDRESS                    0x202

// Type
#define D18F2x9C_x0000_0202_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0202_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0202_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0205_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0205_dct1_mp1_ADDRESS                    0x205

// Type
#define D18F2x9C_x0000_0205_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0205_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0205_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0205_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0205_dct1_mp0_ADDRESS                    0x205

// Type
#define D18F2x9C_x0000_0205_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0205_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0205_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0205_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0205_dct0_mp1_ADDRESS                    0x205

// Type
#define D18F2x9C_x0000_0205_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0205_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0205_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0205_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0205_dct0_mp0_ADDRESS                    0x205

// Type
#define D18F2x9C_x0000_0205_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0205_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0205_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0206_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0206_dct0_mp0_ADDRESS                    0x206

// Type
#define D18F2x9C_x0000_0206_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0206_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0206_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0206_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0206_dct1_mp0_ADDRESS                    0x206

// Type
#define D18F2x9C_x0000_0206_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0206_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0206_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0206_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0206_dct0_mp1_ADDRESS                    0x206

// Type
#define D18F2x9C_x0000_0206_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0206_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0206_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0206_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0206_dct1_mp1_ADDRESS                    0x206

// Type
#define D18F2x9C_x0000_0206_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0206_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0206_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0301_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0301_dct1_mp0_ADDRESS                    0x301

// Type
#define D18F2x9C_x0000_0301_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0301_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0301_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0301_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0301_dct1_mp1_ADDRESS                    0x301

// Type
#define D18F2x9C_x0000_0301_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0301_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0301_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0301_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0301_dct0_mp0_ADDRESS                    0x301

// Type
#define D18F2x9C_x0000_0301_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0301_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0301_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0301_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0301_dct0_mp1_ADDRESS                    0x301

// Type
#define D18F2x9C_x0000_0301_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0301_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0301_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0302_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0302_dct1_mp1_ADDRESS                    0x302

// Type
#define D18F2x9C_x0000_0302_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0302_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0302_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0302_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0302_dct0_mp1_ADDRESS                    0x302

// Type
#define D18F2x9C_x0000_0302_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0302_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0302_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0302_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0302_dct1_mp0_ADDRESS                    0x302

// Type
#define D18F2x9C_x0000_0302_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0302_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0302_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0302_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0302_dct0_mp0_ADDRESS                    0x302

// Type
#define D18F2x9C_x0000_0302_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly_OFFSET        0
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly_WIDTH         5
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly_MASK          0x1f
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly_OFFSET       5
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly_WIDTH        3
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly_MASK         0xe0
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly1_OFFSET       8
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly1_WIDTH        5
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly1_MASK         0x1f00
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly1_OFFSET      13
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly1_WIDTH       3
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly1_MASK        0xe000
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly2_OFFSET       16
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly2_WIDTH        5
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly2_OFFSET      21
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly2_WIDTH       3
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly3_OFFSET       24
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly3_WIDTH        5
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly3_OFFSET      29
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly3_WIDTH       3
#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000

/// D18F2x9C_x0000_0302_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             WrDatFineDly:5 ; ///<
    UINT32                                            WrDatGrossDly:3 ; ///<
    UINT32                                            WrDatFineDly1:5 ; ///<
    UINT32                                           WrDatGrossDly1:3 ; ///<
    UINT32                                            WrDatFineDly2:5 ; ///<
    UINT32                                           WrDatGrossDly2:3 ; ///<
    UINT32                                            WrDatFineDly3:5 ; ///<
    UINT32                                           WrDatGrossDly3:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0302_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0305_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0305_dct0_mp0_ADDRESS                    0x305

// Type
#define D18F2x9C_x0000_0305_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0305_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0305_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0305_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0305_dct1_mp1_ADDRESS                    0x305

// Type
#define D18F2x9C_x0000_0305_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0305_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0305_dct1_mp1_STRUCT;

// **** D18F2x9C_x0000_0305_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0305_dct0_mp1_ADDRESS                    0x305

// Type
#define D18F2x9C_x0000_0305_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0305_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0305_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0305_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0305_dct1_mp0_ADDRESS                    0x305

// Type
#define D18F2x9C_x0000_0305_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0305_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0305_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0306_dct0_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0306_dct0_mp0_ADDRESS                    0x306

// Type
#define D18F2x9C_x0000_0306_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
// Field Data
#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0306_dct0_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0306_dct0_mp0_STRUCT;

// **** D18F2x9C_x0000_0306_dct0_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0306_dct0_mp1_ADDRESS                    0x306

// Type
#define D18F2x9C_x0000_0306_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
// Field Data
#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0306_dct0_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0306_dct0_mp1_STRUCT;

// **** D18F2x9C_x0000_0306_dct1_mp0 Register Definition ****
// Address
#define D18F2x9C_x0000_0306_dct1_mp0_ADDRESS                    0x306

// Type
#define D18F2x9C_x0000_0306_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
// Field Data
#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0306_dct1_mp0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0306_dct1_mp0_STRUCT;

// **** D18F2x9C_x0000_0306_dct1_mp1 Register Definition ****
// Address
#define D18F2x9C_x0000_0306_dct1_mp1_ADDRESS                    0x306

// Type
#define D18F2x9C_x0000_0306_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
// Field Data
#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_0_0_OFFSET        0
#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_0_0_WIDTH         1
#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_0_0_MASK          0x1
#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime_OFFSET           1
#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime_WIDTH            5
#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime_MASK             0x3e
#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_8_6_OFFSET        6
#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_8_6_WIDTH         3
#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_8_6_MASK          0x1c0
#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime1_OFFSET          9
#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime1_WIDTH           5
#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime1_MASK            0x3e00
#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_16_14_OFFSET      14
#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_16_14_WIDTH       3
#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_16_14_MASK        0x1c000
#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime2_OFFSET          17
#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime2_WIDTH           5
#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime2_MASK            0x3e0000
#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_24_22_OFFSET      22
#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_24_22_WIDTH       3
#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_24_22_MASK        0x1c00000
#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime3_OFFSET          25
#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime3_WIDTH           5
#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime3_MASK            0x3e000000
#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_31_30_OFFSET      30
#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_31_30_WIDTH       2
#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_31_30_MASK        0xc0000000

/// D18F2x9C_x0000_0306_dct1_mp1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                                RdDqsTime:5 ; ///<
    UINT32                                             Reserved_8_6:3 ; ///<
    UINT32                                               RdDqsTime1:5 ; ///<
    UINT32                                           Reserved_16_14:3 ; ///<
    UINT32                                               RdDqsTime2:5 ; ///<
    UINT32                                           Reserved_24_22:3 ; ///<
    UINT32                                               RdDqsTime3:5 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0000_0306_dct1_mp1_STRUCT;

// **** D18F2x9C_x0D0F_E00A_dct0 Register Definition ****
// Address
#define D18F2x9C_x0D0F_E00A_dct0_ADDRESS                    0x0d0fe00a

// Type
#define D18F2x9C_x0D0F_E00A_dct0_TYPE                       TYPE_D18F2x9C_dct0
// Field Data
#define D18F2x9C_x0D0F_E00A_dct0_Reserved_3_0_OFFSET        0
#define D18F2x9C_x0D0F_E00A_dct0_Reserved_3_0_WIDTH         4
#define D18F2x9C_x0D0F_E00A_dct0_Reserved_3_0_MASK          0xf
#define D18F2x9C_x0D0F_E00A_dct0_SkewMemClk_OFFSET          4
#define D18F2x9C_x0D0F_E00A_dct0_SkewMemClk_WIDTH           1
#define D18F2x9C_x0D0F_E00A_dct0_SkewMemClk_MASK            0x10
#define D18F2x9C_x0D0F_E00A_dct0_Reserved_11_5_OFFSET       5
#define D18F2x9C_x0D0F_E00A_dct0_Reserved_11_5_WIDTH        7
#define D18F2x9C_x0D0F_E00A_dct0_Reserved_11_5_MASK         0xfe0
#define D18F2x9C_x0D0F_E00A_dct0_Reserved_31_15_OFFSET      15
#define D18F2x9C_x0D0F_E00A_dct0_Reserved_31_15_WIDTH       17
#define D18F2x9C_x0D0F_E00A_dct0_Reserved_31_15_MASK        0xffff8000

/// D18F2x9C_x0D0F_E00A_dct0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_3_0:4 ; ///<
    UINT32                                               SkewMemClk:1 ; ///<
    UINT32                                            Reserved_11_5:7 ; ///<
    UINT32                                        :2 ; ///<
    UINT32                                          :1 ; ///<
    UINT32                                          Reserved_31_15:17 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0D0F_E00A_dct0_STRUCT;

// **** D18F2x9C_x0D0F_E00A_dct1 Register Definition ****
// Address
#define D18F2x9C_x0D0F_E00A_dct1_ADDRESS                    0x0d0fe00a

// Type
#define D18F2x9C_x0D0F_E00A_dct1_TYPE                       TYPE_D18F2x9C_dct1
// Field Data
#define D18F2x9C_x0D0F_E00A_dct1_Reserved_3_0_OFFSET        0
#define D18F2x9C_x0D0F_E00A_dct1_Reserved_3_0_WIDTH         4
#define D18F2x9C_x0D0F_E00A_dct1_Reserved_3_0_MASK          0xf
#define D18F2x9C_x0D0F_E00A_dct1_SkewMemClk_OFFSET          4
#define D18F2x9C_x0D0F_E00A_dct1_SkewMemClk_WIDTH           1
#define D18F2x9C_x0D0F_E00A_dct1_SkewMemClk_MASK            0x10
#define D18F2x9C_x0D0F_E00A_dct1_Reserved_11_5_OFFSET       5
#define D18F2x9C_x0D0F_E00A_dct1_Reserved_11_5_WIDTH        7
#define D18F2x9C_x0D0F_E00A_dct1_Reserved_11_5_MASK         0xfe0
#define D18F2x9C_x0D0F_E00A_dct1_Reserved_31_15_OFFSET      15
#define D18F2x9C_x0D0F_E00A_dct1_Reserved_31_15_WIDTH       17
#define D18F2x9C_x0D0F_E00A_dct1_Reserved_31_15_MASK        0xffff8000

/// D18F2x9C_x0D0F_E00A_dct1
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_3_0:4 ; ///<
    UINT32                                               SkewMemClk:1 ; ///<
    UINT32                                            Reserved_11_5:7 ; ///<
    UINT32                                        :2 ; ///<
    UINT32                                          :1 ; ///<
    UINT32                                          Reserved_31_15:17 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D18F2x9C_x0D0F_E00A_dct1_STRUCT;


// **** DxF0xE4_x01 Register Definition ****
// Address
#define DxF0xE4_x01_ADDRESS                                     0x1

// Type
#define DxF0xE4_x01_TYPE                                        TYPE_D4F0xE4
// Field Data
#define DxF0xE4_x01_Scratch_OFFSET                              0
#define DxF0xE4_x01_Scratch_WIDTH                               32
#define DxF0xE4_x01_Scratch_MASK                                0xffffffff

/// DxF0xE4_x01
typedef union {
  struct {                                                              ///<
    UINT32                                                  Scratch:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0xE4_x01_STRUCT;

// **** DxF0xE4_x02 Register Definition ****
// Address
#define DxF0xE4_x02_ADDRESS                                     0x2

// Type
#define DxF0xE4_x02_TYPE                                        TYPE_D4F0xE4
// Field Data
#define DxF0xE4_x02_Reserved_14_0_OFFSET                        0
#define DxF0xE4_x02_Reserved_14_0_WIDTH                         15
#define DxF0xE4_x02_Reserved_14_0_MASK                          0x7fff
#define DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET               15
#define DxF0xE4_x02_RegsLcAllowTxL1Control_WIDTH                1
#define DxF0xE4_x02_RegsLcAllowTxL1Control_MASK                 0x8000
#define DxF0xE4_x02_Reserved_31_16_OFFSET                       16
#define DxF0xE4_x02_Reserved_31_16_WIDTH                        16
#define DxF0xE4_x02_Reserved_31_16_MASK                         0xffff0000

/// DxF0xE4_x02
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_14_0:15; ///<
    UINT32                                   RegsLcAllowTxL1Control:1 ; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0xE4_x02_STRUCT;

// **** DxF0xE4_x50 Register Definition ****
// Address
#define DxF0xE4_x50_ADDRESS                                     0x50

// Type
#define DxF0xE4_x50_TYPE                                        TYPE_D4F0xE4
// Field Data
#define DxF0xE4_x50_PortLaneReversal_OFFSET                     0
#define DxF0xE4_x50_PortLaneReversal_WIDTH                      1
#define DxF0xE4_x50_PortLaneReversal_MASK                       0x1
#define DxF0xE4_x50_PhyLinkWidth_OFFSET                         1
#define DxF0xE4_x50_PhyLinkWidth_WIDTH                          6
#define DxF0xE4_x50_PhyLinkWidth_MASK                           0x7e
#define DxF0xE4_x50_Reserved_31_7_OFFSET                        7
#define DxF0xE4_x50_Reserved_31_7_WIDTH                         25
#define DxF0xE4_x50_Reserved_31_7_MASK                          0xffffff80

/// DxF0xE4_x50
typedef union {
  struct {                                                              ///<
    UINT32                                         PortLaneReversal:1 ; ///<
    UINT32                                             PhyLinkWidth:6 ; ///<
    UINT32                                            Reserved_31_7:25; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0xE4_x50_STRUCT;

// **** DxF0xE4_x70 Register Definition ****
// Address
#define DxF0xE4_x70_ADDRESS                                     0x70

// Type
#define DxF0xE4_x70_TYPE                                        TYPE_D4F0xE4
// Field Data
#define DxF0xE4_x70_Reserved_15_0_OFFSET                        0
#define DxF0xE4_x70_Reserved_15_0_WIDTH                         16
#define DxF0xE4_x70_Reserved_15_0_MASK                          0xffff
#define DxF0xE4_x70_RxRcbCplTimeout_OFFSET                      16
#define DxF0xE4_x70_RxRcbCplTimeout_WIDTH                       3
#define DxF0xE4_x70_RxRcbCplTimeout_MASK                        0x70000
#define DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET                  19
#define DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH                   1
#define DxF0xE4_x70_RxRcbCplTimeoutMode_MASK                    0x80000
#define DxF0xE4_x70_Reserved_31_20_OFFSET                       20
#define DxF0xE4_x70_Reserved_31_20_WIDTH                        12
#define DxF0xE4_x70_Reserved_31_20_MASK                         0xfff00000

/// DxF0xE4_x70
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_15_0:16; ///<
    UINT32                                          RxRcbCplTimeout:3 ; ///<
    UINT32                                      RxRcbCplTimeoutMode:1 ; ///<
    UINT32                                           Reserved_31_20:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0xE4_x70_STRUCT;

// **** DxF0xE4_xA0 Register Definition ****
// Address
#define DxF0xE4_xA0_ADDRESS                                     0xa0

// Type
#define DxF0xE4_xA0_TYPE                                        TYPE_D4F0xE4
// Field Data
#define DxF0xE4_xA0_Reserved_3_0_OFFSET                         0
#define DxF0xE4_xA0_Reserved_3_0_WIDTH                          4
#define DxF0xE4_xA0_Reserved_3_0_MASK                           0xf
#define DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET                     4
#define DxF0xE4_xA0_Lc16xClearTxPipe_WIDTH                      4
#define DxF0xE4_xA0_Lc16xClearTxPipe_MASK                       0xf0
#define DxF0xE4_xA0_LcL0sInactivity_OFFSET                      8
#define DxF0xE4_xA0_LcL0sInactivity_WIDTH                       4
#define DxF0xE4_xA0_LcL0sInactivity_MASK                        0xf00
#define DxF0xE4_xA0_LcL1Inactivity_OFFSET                       12
#define DxF0xE4_xA0_LcL1Inactivity_WIDTH                        4
#define DxF0xE4_xA0_LcL1Inactivity_MASK                         0xf000
#define DxF0xE4_xA0_Reserved_22_16_OFFSET                       16
#define DxF0xE4_xA0_Reserved_22_16_WIDTH                        7
#define DxF0xE4_xA0_Reserved_22_16_MASK                         0x7f0000
#define DxF0xE4_xA0_LcL1ImmediateAck_OFFSET                     23
#define DxF0xE4_xA0_LcL1ImmediateAck_WIDTH                      1
#define DxF0xE4_xA0_LcL1ImmediateAck_MASK                       0x800000
#define DxF0xE4_xA0_Reserved_31_24_OFFSET                       24
#define DxF0xE4_xA0_Reserved_31_24_WIDTH                        8
#define DxF0xE4_xA0_Reserved_31_24_MASK                         0xff000000

/// DxF0xE4_xA0
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_3_0:4 ; ///<
    UINT32                                         Lc16xClearTxPipe:4 ; ///<
    UINT32                                          LcL0sInactivity:4 ; ///<
    UINT32                                           LcL1Inactivity:4 ; ///<
    UINT32                                           Reserved_22_16:7 ; ///<
    UINT32                                         LcL1ImmediateAck:1 ; ///<
    UINT32                                           Reserved_31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0xE4_xA0_STRUCT;

// **** DxF0xE4_xA1 Register Definition ****
// Address
#define DxF0xE4_xA1_ADDRESS                                     0xa1

// Type
#define DxF0xE4_xA1_TYPE                                        TYPE_D4F0xE4
// Field Data
#define DxF0xE4_xA1_Reserved_10_0_OFFSET                        0
#define DxF0xE4_xA1_Reserved_10_0_WIDTH                         11
#define DxF0xE4_xA1_Reserved_10_0_MASK                          0x7ff
#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET               11
#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_WIDTH                1
#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK                 0x800
#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_OFFSET                12
#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_WIDTH                 1
#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_MASK                  0x1000
#define DxF0xE4_xA1_Reserved_31_13_OFFSET                       13
#define DxF0xE4_xA1_Reserved_31_13_WIDTH                        19
#define DxF0xE4_xA1_Reserved_31_13_MASK                         0xffffe000

/// DxF0xE4_xA1
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_10_0:11; ///<
    UINT32                                   LcDontGotoL0sifL1Armed:1 ; ///<
    UINT32                                    LcInitSpdChgWithCsrEn:1 ; ///<
    UINT32                                           Reserved_31_13:19; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0xE4_xA1_STRUCT;

// **** DxF0xE4_xA2 Register Definition ****
// Address
#define DxF0xE4_xA2_ADDRESS                                     0xa2

// Type
#define DxF0xE4_xA2_TYPE                                        TYPE_D4F0xE4
// Field Data
#define DxF0xE4_xA2_LcLinkWidth_OFFSET                          0
#define DxF0xE4_xA2_LcLinkWidth_WIDTH                           3
#define DxF0xE4_xA2_LcLinkWidth_MASK                            0x7
#define DxF0xE4_xA2_Reserved_3_3_OFFSET                         3
#define DxF0xE4_xA2_Reserved_3_3_WIDTH                          1
#define DxF0xE4_xA2_Reserved_3_3_MASK                           0x8
#define DxF0xE4_xA2_LcLinkWidthRd_OFFSET                        4
#define DxF0xE4_xA2_LcLinkWidthRd_WIDTH                         3
#define DxF0xE4_xA2_LcLinkWidthRd_MASK                          0x70
#define DxF0xE4_xA2_LcReconfigArcMissingEscape_OFFSET           7
#define DxF0xE4_xA2_LcReconfigArcMissingEscape_WIDTH            1
#define DxF0xE4_xA2_LcReconfigArcMissingEscape_MASK             0x80
#define DxF0xE4_xA2_LcReconfigNow_OFFSET                        8
#define DxF0xE4_xA2_LcReconfigNow_WIDTH                         1
#define DxF0xE4_xA2_LcReconfigNow_MASK                          0x100
#define DxF0xE4_xA2_LcRenegotiationSupport_OFFSET               9
#define DxF0xE4_xA2_LcRenegotiationSupport_WIDTH                1
#define DxF0xE4_xA2_LcRenegotiationSupport_MASK                 0x200
#define DxF0xE4_xA2_LcRenegotiateEn_OFFSET                      10
#define DxF0xE4_xA2_LcRenegotiateEn_WIDTH                       1
#define DxF0xE4_xA2_LcRenegotiateEn_MASK                        0x400
#define DxF0xE4_xA2_LcShortReconfigEn_OFFSET                    11
#define DxF0xE4_xA2_LcShortReconfigEn_WIDTH                     1
#define DxF0xE4_xA2_LcShortReconfigEn_MASK                      0x800
#define DxF0xE4_xA2_LcUpconfigureSupport_OFFSET                 12
#define DxF0xE4_xA2_LcUpconfigureSupport_WIDTH                  1
#define DxF0xE4_xA2_LcUpconfigureSupport_MASK                   0x1000
#define DxF0xE4_xA2_LcUpconfigureDis_OFFSET                     13
#define DxF0xE4_xA2_LcUpconfigureDis_WIDTH                      1
#define DxF0xE4_xA2_LcUpconfigureDis_MASK                       0x2000
#define DxF0xE4_xA2_Reserved_19_14_OFFSET                       14
#define DxF0xE4_xA2_Reserved_19_14_WIDTH                        6
#define DxF0xE4_xA2_Reserved_19_14_MASK                         0xfc000
#define DxF0xE4_xA2_LcUpconfigCapable_OFFSET                    20
#define DxF0xE4_xA2_LcUpconfigCapable_WIDTH                     1
#define DxF0xE4_xA2_LcUpconfigCapable_MASK                      0x100000
#define DxF0xE4_xA2_LcDynLanesPwrState_OFFSET                   21
#define DxF0xE4_xA2_LcDynLanesPwrState_WIDTH                    2
#define DxF0xE4_xA2_LcDynLanesPwrState_MASK                     0x600000
#define DxF0xE4_xA2_Reserved_31_23_OFFSET                       23
#define DxF0xE4_xA2_Reserved_31_23_WIDTH                        9
#define DxF0xE4_xA2_Reserved_31_23_MASK                         0xff800000

/// DxF0xE4_xA2
typedef union {
  struct {                                                              ///<
    UINT32                                              LcLinkWidth:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                                            LcLinkWidthRd:3 ; ///<
    UINT32                               LcReconfigArcMissingEscape:1 ; ///<
    UINT32                                            LcReconfigNow:1 ; ///<
    UINT32                                   LcRenegotiationSupport:1 ; ///<
    UINT32                                          LcRenegotiateEn:1 ; ///<
    UINT32                                        LcShortReconfigEn:1 ; ///<
    UINT32                                     LcUpconfigureSupport:1 ; ///<
    UINT32                                         LcUpconfigureDis:1 ; ///<
    UINT32                                           Reserved_19_14:6 ; ///<
    UINT32                                        LcUpconfigCapable:1 ; ///<
    UINT32                                       LcDynLanesPwrState:2 ; ///<
    UINT32                                           Reserved_31_23:9 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0xE4_xA2_STRUCT;

// **** DxF0xE4_xA3 Register Definition ****
// Address
#define DxF0xE4_xA3_ADDRESS                                     0xa3

// Type
#define DxF0xE4_xA3_TYPE                                        TYPE_D4F0xE4
// Field Data
#define DxF0xE4_xA3_Reserved_8_0_OFFSET                         0
#define DxF0xE4_xA3_Reserved_8_0_WIDTH                          9
#define DxF0xE4_xA3_Reserved_8_0_MASK                           0x1ff
#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET              9
#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_WIDTH               1
#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK                0x200
#define DxF0xE4_xA3_Reserved_31_10_OFFSET                       10
#define DxF0xE4_xA3_Reserved_31_10_WIDTH                        22
#define DxF0xE4_xA3_Reserved_31_10_MASK                         0xfffffc00

/// DxF0xE4_xA3
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_8_0:9 ; ///<
    UINT32                                  LcXmitFtsBeforeRecovery:1 ; ///<
    UINT32                                           Reserved_31_10:22; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0xE4_xA3_STRUCT;

// **** DxF0xE4_xA4 Register Definition ****
// Address
#define DxF0xE4_xA4_ADDRESS                                     0xa4

// Type
#define DxF0xE4_xA4_TYPE                                        TYPE_D4F0xE4
// Field Data
#define DxF0xE4_xA4_LcGen2EnStrap_OFFSET                        0
#define DxF0xE4_xA4_LcGen2EnStrap_WIDTH                         1
#define DxF0xE4_xA4_LcGen2EnStrap_MASK                          0x1
#define DxF0xE4_xA4_Reserved_5_1_OFFSET                         1
#define DxF0xE4_xA4_Reserved_5_1_WIDTH                          5
#define DxF0xE4_xA4_Reserved_5_1_MASK                           0x3e
#define DxF0xE4_xA4_LcForceDisSwSpeedChange_OFFSET              6
#define DxF0xE4_xA4_LcForceDisSwSpeedChange_WIDTH               1
#define DxF0xE4_xA4_LcForceDisSwSpeedChange_MASK                0x40
#define DxF0xE4_xA4_Reserved_8_7_OFFSET                         7
#define DxF0xE4_xA4_Reserved_8_7_WIDTH                          2
#define DxF0xE4_xA4_Reserved_8_7_MASK                           0x180
#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_OFFSET            9
#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_WIDTH             1
#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_MASK              0x200
#define DxF0xE4_xA4_Reserved_11_10_OFFSET                       10
#define DxF0xE4_xA4_Reserved_11_10_WIDTH                        2
#define DxF0xE4_xA4_Reserved_11_10_MASK                         0xc00
#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_OFFSET           12
#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_WIDTH            1
#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_MASK             0x1000
#define DxF0xE4_xA4_Reserved_18_13_OFFSET                       13
#define DxF0xE4_xA4_Reserved_18_13_WIDTH                        6
#define DxF0xE4_xA4_Reserved_18_13_MASK                         0x7e000
#define DxF0xE4_xA4_LcOtherSideSupportsGen2_OFFSET              19
#define DxF0xE4_xA4_LcOtherSideSupportsGen2_WIDTH               1
#define DxF0xE4_xA4_LcOtherSideSupportsGen2_MASK                0x80000
#define DxF0xE4_xA4_Reserved_26_20_OFFSET                       20
#define DxF0xE4_xA4_Reserved_26_20_WIDTH                        7
#define DxF0xE4_xA4_Reserved_26_20_MASK                         0x7f00000
#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_OFFSET          27
#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_WIDTH           1
#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_MASK            0x8000000
#define DxF0xE4_xA4_Reserved_31_28_OFFSET                       28
#define DxF0xE4_xA4_Reserved_31_28_WIDTH                        4
#define DxF0xE4_xA4_Reserved_31_28_MASK                         0xf0000000

/// DxF0xE4_xA4
typedef union {
  struct {                                                              ///<
    UINT32                                            LcGen2EnStrap:1 ; ///<
    UINT32                                             Reserved_5_1:5 ; ///<
    UINT32                                  LcForceDisSwSpeedChange:1 ; ///<
    UINT32                                             Reserved_8_7:2 ; ///<
    UINT32                                LcInitiateLinkSpeedChange:1 ; ///<
    UINT32                                           Reserved_11_10:2 ; ///<
    UINT32                               LcSpeedChangeAttemptFailed:1 ; ///<
    UINT32                                           Reserved_18_13:6 ; ///<
    UINT32                                  LcOtherSideSupportsGen2:1 ; ///<
    UINT32                                           Reserved_26_20:7 ; ///<
    UINT32                              LcMultUpstreamAutoSpdChngEn:1 ; ///<
    UINT32                                           Reserved_31_28:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0xE4_xA4_STRUCT;

// **** DxF0xE4_xA5 Register Definition ****
// Address
#define DxF0xE4_xA5_ADDRESS                                     0xa5

// Type
#define DxF0xE4_xA5_TYPE                                        TYPE_D4F0xE4
// Field Data
#define DxF0xE4_xA5_LcCurrentState_OFFSET                       0
#define DxF0xE4_xA5_LcCurrentState_WIDTH                        6
#define DxF0xE4_xA5_LcCurrentState_MASK                         0x3f
#define DxF0xE4_xA5_Reserved_7_6_OFFSET                         6
#define DxF0xE4_xA5_Reserved_7_6_WIDTH                          2
#define DxF0xE4_xA5_Reserved_7_6_MASK                           0xc0
#define DxF0xE4_xA5_LcPrevState1_OFFSET                         8
#define DxF0xE4_xA5_LcPrevState1_WIDTH                          6
#define DxF0xE4_xA5_LcPrevState1_MASK                           0x3f00
#define DxF0xE4_xA5_Reserved_15_14_OFFSET                       14
#define DxF0xE4_xA5_Reserved_15_14_WIDTH                        2
#define DxF0xE4_xA5_Reserved_15_14_MASK                         0xc000
#define DxF0xE4_xA5_LcPrevState2_OFFSET                         16
#define DxF0xE4_xA5_LcPrevState2_WIDTH                          6
#define DxF0xE4_xA5_LcPrevState2_MASK                           0x3f0000
#define DxF0xE4_xA5_Reserved_23_22_OFFSET                       22
#define DxF0xE4_xA5_Reserved_23_22_WIDTH                        2
#define DxF0xE4_xA5_Reserved_23_22_MASK                         0xc00000
#define DxF0xE4_xA5_LcPrevState3_OFFSET                         24
#define DxF0xE4_xA5_LcPrevState3_WIDTH                          6
#define DxF0xE4_xA5_LcPrevState3_MASK                           0x3f000000
#define DxF0xE4_xA5_Reserved_31_30_OFFSET                       30
#define DxF0xE4_xA5_Reserved_31_30_WIDTH                        2
#define DxF0xE4_xA5_Reserved_31_30_MASK                         0xc0000000

/// DxF0xE4_xA5
typedef union {
  struct {                                                              ///<
    UINT32                                           LcCurrentState:6 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                             LcPrevState1:6 ; ///<
    UINT32                                           Reserved_15_14:2 ; ///<
    UINT32                                             LcPrevState2:6 ; ///<
    UINT32                                           Reserved_23_22:2 ; ///<
    UINT32                                             LcPrevState3:6 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0xE4_xA5_STRUCT;

// **** DxF0xE4_xB1 Register Definition ****
// Address
#define DxF0xE4_xB1_ADDRESS                                     0xb1

// Type
#define DxF0xE4_xB1_TYPE                                        TYPE_D4F0xE4
// Field Data
#define DxF0xE4_xB1_Reserved_18_0_OFFSET                        0
#define DxF0xE4_xB1_Reserved_18_0_WIDTH                         19
#define DxF0xE4_xB1_Reserved_18_0_MASK                          0x7ffff
#define DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET                  19
#define DxF0xE4_xB1_LcDeassertRxEnInL0s_WIDTH                   1
#define DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK                    0x80000
#define DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET                    20
#define DxF0xE4_xB1_LcBlockElIdleinL0_WIDTH                     1
#define DxF0xE4_xB1_LcBlockElIdleinL0_MASK                      0x100000
#define DxF0xE4_xB1_Reserved_31_21_OFFSET                       21
#define DxF0xE4_xB1_Reserved_31_21_WIDTH                        11
#define DxF0xE4_xB1_Reserved_31_21_MASK                         0xffe00000

/// DxF0xE4_xB1
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_18_0:19; ///<
    UINT32                                      LcDeassertRxEnInL0s:1 ; ///<
    UINT32                                        LcBlockElIdleinL0:1 ; ///<
    UINT32                                           Reserved_31_21:11; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0xE4_xB1_STRUCT;

// **** DxF0xE4_xB5 Register Definition ****
// Address
#define DxF0xE4_xB5_ADDRESS                                     0xb5

// Type
#define DxF0xE4_xB5_TYPE                                        TYPE_D4F0xE4
// Field Data
#define DxF0xE4_xB5_LcSelectDeemphasis_OFFSET                   0
#define DxF0xE4_xB5_LcSelectDeemphasis_WIDTH                    1
#define DxF0xE4_xB5_LcSelectDeemphasis_MASK                     0x1
#define DxF0xE4_xB5_LcSelectDeemphasisCntl_OFFSET               1
#define DxF0xE4_xB5_LcSelectDeemphasisCntl_WIDTH                2
#define DxF0xE4_xB5_LcSelectDeemphasisCntl_MASK                 0x6
#define DxF0xE4_xB5_LcRcvdDeemphasis_OFFSET                     3
#define DxF0xE4_xB5_LcRcvdDeemphasis_WIDTH                      1
#define DxF0xE4_xB5_LcRcvdDeemphasis_MASK                       0x8
#define DxF0xE4_xB5_Reserved_29_4_OFFSET                        4
#define DxF0xE4_xB5_Reserved_29_4_WIDTH                         26
#define DxF0xE4_xB5_Reserved_29_4_MASK                          0x3ffffff0
#define DxF0xE4_xB5_LcGoToRecovery_OFFSET                       30
#define DxF0xE4_xB5_LcGoToRecovery_WIDTH                        1
#define DxF0xE4_xB5_LcGoToRecovery_MASK                         0x40000000
#define DxF0xE4_xB5_Reserved_31_31_OFFSET                       31
#define DxF0xE4_xB5_Reserved_31_31_WIDTH                        1
#define DxF0xE4_xB5_Reserved_31_31_MASK                         0x80000000

/// DxF0xE4_xB5
typedef union {
  struct {                                                              ///<
    UINT32                                       LcSelectDeemphasis:1 ; ///<
    UINT32                                   LcSelectDeemphasisCntl:2 ; ///<
    UINT32                                         LcRcvdDeemphasis:1 ; ///<
    UINT32                                            Reserved_29_4:26; ///<
    UINT32                                           LcGoToRecovery:1 ; ///<
    UINT32                                           Reserved_31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0xE4_xB5_STRUCT;

// **** DxF0xE4_xC0 Register Definition ****
// Address
#define DxF0xE4_xC0_ADDRESS                                     0xc0

// Type
#define DxF0xE4_xC0_TYPE                                        TYPE_D4F0xE4
// Field Data
#define DxF0xE4_xC0_Reserved_12_0_OFFSET                        0
#define DxF0xE4_xC0_Reserved_12_0_WIDTH                         13
#define DxF0xE4_xC0_Reserved_12_0_MASK                          0x1fff
#define DxF0xE4_xC0_StrapForceCompliance_OFFSET                 13
#define DxF0xE4_xC0_StrapForceCompliance_WIDTH                  1
#define DxF0xE4_xC0_StrapForceCompliance_MASK                   0x2000
#define DxF0xE4_xC0_Reserved_14_14_OFFSET                       14
#define DxF0xE4_xC0_Reserved_14_14_WIDTH                        1
#define DxF0xE4_xC0_Reserved_14_14_MASK                         0x4000
#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET       15
#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_WIDTH        1
#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK         0x8000
#define DxF0xE4_xC0_Reserved_31_16_OFFSET                       16
#define DxF0xE4_xC0_Reserved_31_16_WIDTH                        16
#define DxF0xE4_xC0_Reserved_31_16_MASK                         0xffff0000

/// DxF0xE4_xC0
typedef union {
  struct {                                                              ///<
    UINT32                                            Reserved_12_0:13; ///<
    UINT32                                     StrapForceCompliance:1 ; ///<
    UINT32                                           Reserved_14_14:1 ; ///<
    UINT32                           StrapAutoRcSpeedNegotiationDis:1 ; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0xE4_xC0_STRUCT;

// **** DxF0xE4_xC1 Register Definition ****
// Address
#define DxF0xE4_xC1_ADDRESS                                     0xc1

// Type
#define DxF0xE4_xC1_TYPE                                        TYPE_D4F0xE4
// Field Data
#define DxF0xE4_xC1_StrapReverseLanes_OFFSET                    0
#define DxF0xE4_xC1_StrapReverseLanes_WIDTH                     1
#define DxF0xE4_xC1_StrapReverseLanes_MASK                      0x1
#define DxF0xE4_xC1_StrapE2EPrefixEn_OFFSET                     1
#define DxF0xE4_xC1_StrapE2EPrefixEn_WIDTH                      1
#define DxF0xE4_xC1_StrapE2EPrefixEn_MASK                       0x2
#define DxF0xE4_xC1_StrapExtendedFmtSupported_OFFSET            2
#define DxF0xE4_xC1_StrapExtendedFmtSupported_WIDTH             1
#define DxF0xE4_xC1_StrapExtendedFmtSupported_MASK              0x4
#define DxF0xE4_xC1_Reserved_31_3_OFFSET                        3
#define DxF0xE4_xC1_Reserved_31_3_WIDTH                         29
#define DxF0xE4_xC1_Reserved_31_3_MASK                          0xfffffff8

/// DxF0xE4_xC1
typedef union {
  struct {                                                              ///<
    UINT32                                        StrapReverseLanes:1 ; ///<
    UINT32                                         StrapE2EPrefixEn:1 ; ///<
    UINT32                                StrapExtendedFmtSupported:1 ; ///<
    UINT32                                            Reserved_31_3:29; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} DxF0xE4_xC1_STRUCT;

// **** GMMx00 Register Definition ****
// Address
#define GMMx00_ADDRESS                                          0x0

// Type
#define GMMx00_TYPE                                             TYPE_GMM
// Field Data
#define GMMx00_MM_OFFSET_OFFSET                                 0
#define GMMx00_MM_OFFSET_WIDTH                                  31
#define GMMx00_MM_OFFSET_MASK                                   0x7fffffff
#define GMMx00_MM_APER_OFFSET                                   31
#define GMMx00_MM_APER_WIDTH                                    1
#define GMMx00_MM_APER_MASK                                     0x80000000

/// GMMx00
typedef union {
  struct {                                                              ///<
    UINT32                                                MM_OFFSET:31; ///<
    UINT32                                                  MM_APER:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx00_STRUCT;

// **** GMMx04 Register Definition ****
// Address
#define GMMx04_ADDRESS                                          0x4

// Type
#define GMMx04_TYPE                                             TYPE_GMM
// Field Data
#define GMMx04_MM_DATA_OFFSET                                   0
#define GMMx04_MM_DATA_WIDTH                                    32
#define GMMx04_MM_DATA_MASK                                     0xffffffff

/// GMMx04
typedef union {
  struct {                                                              ///<
    UINT32                                                  MM_DATA:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx04_STRUCT;

// **** GMMx63C Register Definition ****
// Address
#define GMMx63C_ADDRESS                                         0x63c

// Type
#define GMMx63C_TYPE                                            TYPE_GMM
// Field Data
#define GMMx63C_VoltageForceEn_OFFSET                           0
#define GMMx63C_VoltageForceEn_WIDTH                            1
#define GMMx63C_VoltageForceEn_MASK                             0x1
#define GMMx63C_VoltageChangeEn_OFFSET                          1
#define GMMx63C_VoltageChangeEn_WIDTH                           1
#define GMMx63C_VoltageChangeEn_MASK                            0x2
#define GMMx63C_VoltageChangeReq_OFFSET                         2
#define GMMx63C_VoltageChangeReq_WIDTH                          1
#define GMMx63C_VoltageChangeReq_MASK                           0x4
#define GMMx63C_Reserved_7_3_OFFSET                             3
#define GMMx63C_Reserved_7_3_WIDTH                              5
#define GMMx63C_Reserved_7_3_MASK                               0xf8
#define GMMx63C_VoltageLevel_OFFSET                             8
#define GMMx63C_VoltageLevel_WIDTH                              8
#define GMMx63C_VoltageLevel_MASK                               0xff00
#define GMMx63C_Reserved_31_16_OFFSET                           16
#define GMMx63C_Reserved_31_16_WIDTH                            16
#define GMMx63C_Reserved_31_16_MASK                             0xffff0000

/// GMMx63C
typedef union {
  struct {                                                              ///<
    UINT32                                           VoltageForceEn:1 ; ///<
    UINT32                                          VoltageChangeEn:1 ; ///<
    UINT32                                         VoltageChangeReq:1 ; ///<
    UINT32                                             Reserved_7_3:5 ; ///<
    UINT32                                             VoltageLevel:8 ; ///<
    UINT32                                           Reserved_31_16:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx63C_STRUCT;

// **** GMMx640 Register Definition ****
// Address
#define GMMx640_ADDRESS                                         0x640

// Type
#define GMMx640_TYPE                                            TYPE_GMM
// Field Data
#define GMMx640_VoltageChangeAck_OFFSET                         0
#define GMMx640_VoltageChangeAck_WIDTH                          1
#define GMMx640_VoltageChangeAck_MASK                           0x1
#define GMMx640_CurrentVoltageLevel_OFFSET                      1
#define GMMx640_CurrentVoltageLevel_WIDTH                       8
#define GMMx640_CurrentVoltageLevel_MASK                        0x1fe
#define GMMx640_Reserved_31_9_OFFSET                            9
#define GMMx640_Reserved_31_9_WIDTH                             23
#define GMMx640_Reserved_31_9_MASK                              0xfffffe00

/// GMMx640
typedef union {
  struct {                                                              ///<
    UINT32                                         VoltageChangeAck:1 ; ///<
    UINT32                                      CurrentVoltageLevel:8 ; ///<
    UINT32                                            Reserved_31_9:23; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx640_STRUCT;



// **** GMMx770 Register Definition ****
// Address
#define GMMx770_ADDRESS                                         0x770

// Type
#define GMMx770_TYPE                                            TYPE_GMM
// Field Data
#define GMMx770_VoltageChangeReq_OFFSET                         0
#define GMMx770_VoltageChangeReq_WIDTH                          1
#define GMMx770_VoltageChangeReq_MASK                           0x1
#define GMMx770_VoltageLevel_OFFSET                             1
#define GMMx770_VoltageLevel_WIDTH                              8
#define GMMx770_VoltageLevel_MASK                               0x1fe
#define GMMx770_VoltageChangeEn_OFFSET                          9
#define GMMx770_VoltageChangeEn_WIDTH                           1
#define GMMx770_VoltageChangeEn_MASK                            0x200
#define GMMx770_VoltageForceEn_OFFSET                           10
#define GMMx770_VoltageForceEn_WIDTH                            1
#define GMMx770_VoltageForceEn_MASK                             0x400
#define GMMx770_Reserved_31_11_OFFSET                           11
#define GMMx770_Reserved_31_11_WIDTH                            21
#define GMMx770_Reserved_31_11_MASK                             0xfffff800

/// GMMx770
typedef union {
  struct {                                                              ///<
    UINT32                                         VoltageChangeReq:1 ; ///<
    UINT32                                             VoltageLevel:8 ; ///<
    UINT32                                          VoltageChangeEn:1 ; ///<
    UINT32                                           VoltageForceEn:1 ; ///<
    UINT32                                           Reserved_31_11:21; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx770_STRUCT;

// **** GMMx774 Register Definition ****
// Address
#define GMMx774_ADDRESS                                         0x774

// Type
#define GMMx774_TYPE                                            TYPE_GMM
// Field Data
#define GMMx774_VoltageChangeAck_OFFSET                         0
#define GMMx774_VoltageChangeAck_WIDTH                          1
#define GMMx774_VoltageChangeAck_MASK                           0x1
#define GMMx774_CurrentVoltageLevel_OFFSET                      1
#define GMMx774_CurrentVoltageLevel_WIDTH                       8
#define GMMx774_CurrentVoltageLevel_MASK                        0x1fe
#define GMMx774_Reserved_31_9_OFFSET                            9
#define GMMx774_Reserved_31_9_WIDTH                             23
#define GMMx774_Reserved_31_9_MASK                              0xfffffe00

/// GMMx774
typedef union {
  struct {                                                              ///<
    UINT32                                         VoltageChangeAck:1 ; ///<
    UINT32                                      CurrentVoltageLevel:8 ; ///<
    UINT32                                            Reserved_31_9:23; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx774_STRUCT;

// **** GMMx7A0 Register Definition ****
// Address
#define GMMx7A0_ADDRESS                                         0x7a0

// Type
#define GMMx7A0_TYPE                                            TYPE_GMM
// Field Data
#define GMMx7A0_DivId_OFFSET                                    0
#define GMMx7A0_DivId_WIDTH                                     3
#define GMMx7A0_DivId_MASK                                      0x7
#define GMMx7A0_RampDis_OFFSET                                  3
#define GMMx7A0_RampDis_WIDTH                                   1
#define GMMx7A0_RampDis_MASK                                    0x8
#define GMMx7A0_Hysteresis_OFFSET                               4
#define GMMx7A0_Hysteresis_WIDTH                                12
#define GMMx7A0_Hysteresis_MASK                                 0xfff0
#define GMMx7A0_SclkRunningMask_OFFSET                          16
#define GMMx7A0_SclkRunningMask_WIDTH                           1
#define GMMx7A0_SclkRunningMask_MASK                            0x10000
#define GMMx7A0_SmuBusyMask_OFFSET                              17
#define GMMx7A0_SmuBusyMask_WIDTH                               1
#define GMMx7A0_SmuBusyMask_MASK                                0x20000
#define GMMx7A0_PcieLclkIdle1Mask_OFFSET                        18
#define GMMx7A0_PcieLclkIdle1Mask_WIDTH                         1
#define GMMx7A0_PcieLclkIdle1Mask_MASK                          0x40000
#define GMMx7A0_PcieLclkIdle2Mask_OFFSET                        19
#define GMMx7A0_PcieLclkIdle2Mask_WIDTH                         1
#define GMMx7A0_PcieLclkIdle2Mask_MASK                          0x80000
#define GMMx7A0_L1imugfxIdleMask_OFFSET                         20
#define GMMx7A0_L1imugfxIdleMask_WIDTH                          1
#define GMMx7A0_L1imugfxIdleMask_MASK                           0x100000
#define GMMx7A0_L1imugppsbIdleMask_OFFSET                       21
#define GMMx7A0_L1imugppsbIdleMask_WIDTH                        1
#define GMMx7A0_L1imugppsbIdleMask_MASK                         0x200000
#define GMMx7A0_L1imubifIdleMask_OFFSET                         22
#define GMMx7A0_L1imubifIdleMask_WIDTH                          1
#define GMMx7A0_L1imubifIdleMask_MASK                           0x400000
#define GMMx7A0_L1imuintgenIdleMask_OFFSET                      23
#define GMMx7A0_L1imuintgenIdleMask_WIDTH                       1
#define GMMx7A0_L1imuintgenIdleMask_MASK                        0x800000
#define GMMx7A0_L2imuIdleMask_OFFSET                            24
#define GMMx7A0_L2imuIdleMask_WIDTH                             1
#define GMMx7A0_L2imuIdleMask_MASK                              0x1000000
#define GMMx7A0_OrbIdleMask_OFFSET                              25
#define GMMx7A0_OrbIdleMask_WIDTH                               1
#define GMMx7A0_OrbIdleMask_MASK                                0x2000000
#define GMMx7A0_OnInbWakeMask_OFFSET                            26
#define GMMx7A0_OnInbWakeMask_WIDTH                             1
#define GMMx7A0_OnInbWakeMask_MASK                              0x4000000
#define GMMx7A0_OnInbWakeAckMask_OFFSET                         27
#define GMMx7A0_OnInbWakeAckMask_WIDTH                          1
#define GMMx7A0_OnInbWakeAckMask_MASK                           0x8000000
#define GMMx7A0_OnOutbWakeMask_OFFSET                           28
#define GMMx7A0_OnOutbWakeMask_WIDTH                            1
#define GMMx7A0_OnOutbWakeMask_MASK                             0x10000000
#define GMMx7A0_OnOutbWakeAckMask_OFFSET                        29
#define GMMx7A0_OnOutbWakeAckMask_WIDTH                         1
#define GMMx7A0_OnOutbWakeAckMask_MASK                          0x20000000
#define GMMx7A0_DmaactiveMask_OFFSET                            30
#define GMMx7A0_DmaactiveMask_WIDTH                             1
#define GMMx7A0_DmaactiveMask_MASK                              0x40000000
#define GMMx7A0_EnableDs_OFFSET                                 31
#define GMMx7A0_EnableDs_WIDTH                                  1
#define GMMx7A0_EnableDs_MASK                                   0x80000000

/// GMMx7A0
typedef union {
  struct {                                                              ///<
    UINT32                                                    DivId:3 ; ///<
    UINT32                                                  RampDis:1 ; ///<
    UINT32                                               Hysteresis:12; ///<
    UINT32                                          SclkRunningMask:1 ; ///<
    UINT32                                              SmuBusyMask:1 ; ///<
    UINT32                                        PcieLclkIdle1Mask:1 ; ///<
    UINT32                                        PcieLclkIdle2Mask:1 ; ///<
    UINT32                                         L1imugfxIdleMask:1 ; ///<
    UINT32                                       L1imugppsbIdleMask:1 ; ///<
    UINT32                                         L1imubifIdleMask:1 ; ///<
    UINT32                                      L1imuintgenIdleMask:1 ; ///<
    UINT32                                            L2imuIdleMask:1 ; ///<
    UINT32                                              OrbIdleMask:1 ; ///<
    UINT32                                            OnInbWakeMask:1 ; ///<
    UINT32                                         OnInbWakeAckMask:1 ; ///<
    UINT32                                           OnOutbWakeMask:1 ; ///<
    UINT32                                        OnOutbWakeAckMask:1 ; ///<
    UINT32                                            DmaactiveMask:1 ; ///<
    UINT32                                                 EnableDs:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx7A0_STRUCT;

// **** GMMx7B0 Register Definition ****
// Address
#define GMMx7B0_ADDRESS                                         0x7b0

// Type
#define GMMx7B0_TYPE                                            TYPE_GMM
// Field Data
#define GMMx7B0_SMU_VOLTAGE_EN_OFFSET                           0
#define GMMx7B0_SMU_VOLTAGE_EN_WIDTH                            1
#define GMMx7B0_SMU_VOLTAGE_EN_MASK                             0x1
#define GMMx7B0_SMU_VOLTAGE_LEVEL_OFFSET                        1
#define GMMx7B0_SMU_VOLTAGE_LEVEL_WIDTH                         8
#define GMMx7B0_SMU_VOLTAGE_LEVEL_MASK                          0x1fe
#define GMMx7B0_Reserved_OFFSET                                 9
#define GMMx7B0_Reserved_WIDTH                                  23
#define GMMx7B0_Reserved_MASK                                   0xfffffe00

/// GMMx7B0
typedef union {
  struct {                                                              ///<
    UINT32                                           SMU_VOLTAGE_EN:1 ; ///<
    UINT32                                        SMU_VOLTAGE_LEVEL:8 ; ///<
    UINT32                                                 Reserved:23; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx7B0_STRUCT;

// **** GMMx898 Register Definition ****
// Address
#define GMMx898_ADDRESS                                         0x898

// Type
#define GMMx898_TYPE                                            TYPE_GMM
// Field Data
#define GMMx898_Threshold_OFFSET                                0
#define GMMx898_Threshold_WIDTH                                 8
#define GMMx898_Threshold_MASK                                  0xff
#define GMMx898_Reserved_31_8_OFFSET                            8
#define GMMx898_Reserved_31_8_WIDTH                             24
#define GMMx898_Reserved_31_8_MASK                              0xffffff00

/// GMMx898
typedef union {
  struct {                                                              ///<
    UINT32                                                Threshold:8 ; ///<
    UINT32                                            Reserved_31_8:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx898_STRUCT;

// **** GMMxC64 Register Definition ****
// Address
#define GMMxC64_ADDRESS                                         0xc64

// Type
#define GMMxC64_TYPE                                            TYPE_GMM
// Field Data
#define GMMxC64_MCIFMEM_CACHE_MODE_DIS_OFFSET                   0
#define GMMxC64_MCIFMEM_CACHE_MODE_DIS_WIDTH                    1
#define GMMxC64_MCIFMEM_CACHE_MODE_DIS_MASK                     0x1
#define GMMxC64_Reserved_OFFSET                                 1
#define GMMxC64_Reserved_WIDTH                                  31
#define GMMxC64_Reserved_MASK                                   0xfffffffe

/// GMMxC64
typedef union {
  struct {                                                              ///<
    UINT32                                   MCIFMEM_CACHE_MODE_DIS:1 ; ///<
    UINT32                                                 Reserved:31; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMxC64_STRUCT;


typedef union {
  struct {                                                              ///<
    UINT32                                                    CHAN0:4 ; ///<
    UINT32                                                    CHAN1:4 ; ///<
    UINT32                                                    CHAN2:4 ; ///<
    UINT32                                                 NOOFCHAN:2 ; ///<
    UINT32                                                 Reserved:18; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1012_STRUCT;





// **** GMMx2024 Register Definition ****
// Address
#define GMMx2024_ADDRESS                                        0x2024

// Type
#define GMMx2024_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2024_FB_BASE_OFFSET                                 0
#define GMMx2024_FB_BASE_WIDTH                                  16
#define GMMx2024_FB_BASE_MASK                                   0xffff
#define GMMx2024_FB_TOP_OFFSET                                  16
#define GMMx2024_FB_TOP_WIDTH                                   16
#define GMMx2024_FB_TOP_MASK                                    0xffff0000

/// GMMx2024
typedef union {
  struct {                                                              ///<
    UINT32                                                  FB_BASE:16; ///<
    UINT32                                                   FB_TOP:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2024_STRUCT;

// **** GMMx2068 Register Definition ****
// Address
#define GMMx2068_ADDRESS                                        0x2068

// Type
#define GMMx2068_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2068_FB_OFFSET_OFFSET                               0
#define GMMx2068_FB_OFFSET_WIDTH                                18
#define GMMx2068_FB_OFFSET_MASK                                 0x3ffff
#define GMMx2068_Reserved_OFFSET                                18
#define GMMx2068_Reserved_WIDTH                                 14
#define GMMx2068_Reserved_MASK                                  0xfffc0000

/// GMMx2068
typedef union {
  struct {                                                              ///<
    UINT32                                                FB_OFFSET:18; ///<
    UINT32                                                 Reserved:14; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2068_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32                                         DEFAULT_STEERING:2 ; ///<
    UINT32                                          CLIENT_STEERING:2 ; ///<
    UINT32                                                 Reserved:28; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1017_STRUCT;







// **** GMMx20EC Register Definition ****
// Address

// **** GMMx2114 Register Definition ****
// Address
#define GMMx2114_ADDRESS                                        0x2114

// Type
#define GMMx2114_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2114_STOR1_PRI_OFFSET                               0
#define GMMx2114_STOR1_PRI_WIDTH                                8
#define GMMx2114_STOR1_PRI_MASK                                 0xff
#define GMMx2114_Reserved_OFFSET                                8
#define GMMx2114_Reserved_WIDTH                                 24
#define GMMx2114_Reserved_MASK                                  0xffffff00

/// GMMx2114
typedef union {
  struct {                                                              ///<
    UINT32                                                STOR1_PRI:8 ; ///<
    UINT32                                                 Reserved:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2114_STRUCT;


// **** GMMx2188 Register Definition ****
// Address
#define GMMx2188_ADDRESS                                        0x2188

// Type
#define GMMx2188_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2188_ENABLE_OFFSET                                  0
#define GMMx2188_ENABLE_WIDTH                                   1
#define GMMx2188_ENABLE_MASK                                    0x1
#define GMMx2188_PRESCALE_OFFSET                                1
#define GMMx2188_PRESCALE_WIDTH                                 2
#define GMMx2188_PRESCALE_MASK                                  0x6
#define GMMx2188_BLACKOUT_EXEMPT_OFFSET                         3
#define GMMx2188_BLACKOUT_EXEMPT_WIDTH                          1
#define GMMx2188_BLACKOUT_EXEMPT_MASK                           0x8
#define GMMx2188_STALL_MODE_OFFSET                              4
#define GMMx2188_STALL_MODE_WIDTH                               2
#define GMMx2188_STALL_MODE_MASK                                0x30
#define GMMx2188_STALL_OVERRIDE_OFFSET                          6
#define GMMx2188_STALL_OVERRIDE_WIDTH                           1
#define GMMx2188_STALL_OVERRIDE_MASK                            0x40
#define GMMx2188_MAXBURST_OFFSET                                7
#define GMMx2188_MAXBURST_WIDTH                                 4
#define GMMx2188_MAXBURST_MASK                                  0x780
#define GMMx2188_LAZY_TIMER_OFFSET                              11
#define GMMx2188_LAZY_TIMER_WIDTH                               4
#define GMMx2188_LAZY_TIMER_MASK                                0x7800
#define GMMx2188_STALL_OVERRIDE_WTM_OFFSET                      15
#define GMMx2188_STALL_OVERRIDE_WTM_WIDTH                       1
#define GMMx2188_STALL_OVERRIDE_WTM_MASK                        0x8000
#define GMMx2188_Reserved_OFFSET                                16
#define GMMx2188_Reserved_WIDTH                                 16
#define GMMx2188_Reserved_MASK                                  0xffff0000

/// GMMx2188
typedef union {
  struct {                                                              ///<
    UINT32                                                   ENABLE:1 ; ///<
    UINT32                                                 PRESCALE:2 ; ///<
    UINT32                                          BLACKOUT_EXEMPT:1 ; ///<
    UINT32                                               STALL_MODE:2 ; ///<
    UINT32                                           STALL_OVERRIDE:1 ; ///<
    UINT32                                                 MAXBURST:4 ; ///<
    UINT32                                               LAZY_TIMER:4 ; ///<
    UINT32                                       STALL_OVERRIDE_WTM:1 ; ///<
    UINT32                                                 Reserved:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2188_STRUCT;




#define GMMx21F4_STALL_OVERRIDE_OFFSET                          6
typedef union {
  struct {                                                              ///<
    UINT32                                             UVD_OPTIMIZE:1 ; ///<
    UINT32                                             VCE_OPTIMIZE:1 ; ///<
    UINT32                                          XB_UVD_OPTIMIZE:1 ; ///<
    UINT32                                          XB_VCE_OPTIMIZE:1 ; ///<
    UINT32                                   CITF_UVD_OPPOSITE_CHAN:1 ; ///<
    UINT32                                   CITF_UMC_OPPOSITE_CHAN:1 ; ///<
    UINT32                                   CITF_VCE_OPPOSITE_CHAN:1 ; ///<
    UINT32                                  CITF_VCEU_OPPOSITE_CHAN:1 ; ///<
    UINT32                                                 Reserved:24; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1034_STRUCT;


// **** GMMx25C0 Register Definition ****
// Address
#define GMMx25C0_ADDRESS                                        0x25c0

// Type
#define GMMx25C0_TYPE                                           TYPE_GMM
// Field Data
#define GMMx25C0_Reserved_OFFSET                                0
#define GMMx25C0_Reserved_WIDTH                                 2
#define GMMx25C0_Reserved_MASK                                  0x3
#define GMMx25C0_IGNOREPM_OFFSET                                2
#define GMMx25C0_IGNOREPM_WIDTH                                 1
#define GMMx25C0_IGNOREPM_MASK                                  0x4
#define GMMx25C0_EXEMPTPM_OFFSET                                3
#define GMMx25C0_EXEMPTPM_WIDTH                                 1
#define GMMx25C0_EXEMPTPM_MASK                                  0x8
#define GMMx25C0_GFX_IDLE_OVERRIDE_OFFSET                       4
#define GMMx25C0_GFX_IDLE_OVERRIDE_WIDTH                        2
#define GMMx25C0_GFX_IDLE_OVERRIDE_MASK                         0x30
#define GMMx25C0_MCD_SRBM_MASK_ENABLE_OFFSET                    6
#define GMMx25C0_MCD_SRBM_MASK_ENABLE_WIDTH                     1
#define GMMx25C0_MCD_SRBM_MASK_ENABLE_MASK                      0x40
#define GMMx25C0_DUMMY_OFFSET                                   7
#define GMMx25C0_DUMMY_WIDTH                                    7
#define GMMx25C0_DUMMY_MASK                                     0x3f80
#define GMMx25C0_Reserved14_31_OFFSET                           14
#define GMMx25C0_Reserved14_31_WIDTH                            18
#define GMMx25C0_Reserved14_31_MASK                             0xffffc000

/// GMMx25C0
typedef union {
  struct {                                                              ///<
    UINT32                                                 Reserved:2 ; ///<
    UINT32                                                 IGNOREPM:1 ; ///<
    UINT32                                                 EXEMPTPM:1 ; ///<
    UINT32                                        GFX_IDLE_OVERRIDE:2 ; ///<
    UINT32                                     MCD_SRBM_MASK_ENABLE:1 ; ///<
    UINT32                                                    DUMMY:7 ; ///<
    UINT32                                            Reserved14_31:18; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx25C0_STRUCT;

// **** GMMx25C8 Register Definition ****
// Address
#define GMMx25C8_ADDRESS                                        0x25c8

// Type
#define GMMx25C8_TYPE                                           TYPE_GMM
// Field Data
#define GMMx25C8_READ_LCL_OFFSET                                0
#define GMMx25C8_READ_LCL_WIDTH                                 8
#define GMMx25C8_READ_LCL_MASK                                  0xff
#define GMMx25C8_READ_HUB_OFFSET                                8
#define GMMx25C8_READ_HUB_WIDTH                                 8
#define GMMx25C8_READ_HUB_MASK                                  0xff00
#define GMMx25C8_READ_PRI_OFFSET                                16
#define GMMx25C8_READ_PRI_WIDTH                                 8
#define GMMx25C8_READ_PRI_MASK                                  0xff0000
#define GMMx25C8_LCL_PRI_OFFSET                                 24
#define GMMx25C8_LCL_PRI_WIDTH                                  1
#define GMMx25C8_LCL_PRI_MASK                                   0x1000000
#define GMMx25C8_HUB_PRI_OFFSET                                 25
#define GMMx25C8_HUB_PRI_WIDTH                                  1
#define GMMx25C8_HUB_PRI_MASK                                   0x2000000
#define GMMx25C8_Reserved_OFFSET                                26
#define GMMx25C8_Reserved_WIDTH                                 6
#define GMMx25C8_Reserved_MASK                                  0xfc000000

/// GMMx25C8
typedef union {
  struct {                                                              ///<
    UINT32                                                 READ_LCL:8 ; ///<
    UINT32                                                 READ_HUB:8 ; ///<
    UINT32                                                 READ_PRI:8 ; ///<
    UINT32                                                  LCL_PRI:1 ; ///<
    UINT32                                                  HUB_PRI:1 ; ///<
    UINT32                                                 Reserved:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx25C8_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32            ex1047_0:8;
    UINT32            ex1047_1:8;
    UINT32            ex1047_2:8;
    UINT32            ex1047_3:8;
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1047_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32            ex1048_0:8;
    UINT32            ex1048_1:8;
    UINT32            ex1048_2:8;
    UINT32            ex1048_3:5;
    UINT32                                                 Reserved:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1048_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32            ex1060_0:8;
    UINT32            ex1060_1:8;
    UINT32            ex1060_2:8;
    UINT32            ex1060_3:8;
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1060_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32            ex1061_0:8;
    UINT32            ex1061_1:8;
    UINT32            ex1061_2:8;
    UINT32            ex1061_3:5;
    UINT32                                                 Reserved:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1061_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32            ex1062_0:5;
    UINT32            ex1062_1:5;
    UINT32                                                   STATE2:5 ; ///<
    UINT32                                                   STATE3:5 ; ///<
    UINT32                                                 Reserved:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1062_STRUCT;

// **** GMMx2814 Register Definition ****
// Address
#define GMMx2814_ADDRESS                                        0x2814

// Type
#define GMMx2814_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2814_CSENABLE_OFFSET                                0
#define GMMx2814_CSENABLE_WIDTH                                 1
#define GMMx2814_CSENABLE_MASK                                  0x1
#define GMMx2814_Reserved_OFFSET                                1
#define GMMx2814_Reserved_WIDTH                                 4
#define GMMx2814_Reserved_MASK                                  0x1e
#define GMMx2814_BASEADDR21_11_OFFSET                           5
#define GMMx2814_BASEADDR21_11_WIDTH                            11
#define GMMx2814_BASEADDR21_11_MASK                             0xffe0
#define GMMx2814_Reserved16_18_OFFSET                           16
#define GMMx2814_Reserved16_18_WIDTH                            3
#define GMMx2814_Reserved16_18_MASK                             0x70000
#define GMMx2814_BASEADDR38_27_OFFSET                           19
#define GMMx2814_BASEADDR38_27_WIDTH                            12
#define GMMx2814_BASEADDR38_27_MASK                             0x7ff80000
#define GMMx2814_Reserved31_31_OFFSET                           31
#define GMMx2814_Reserved31_31_WIDTH                            1
#define GMMx2814_Reserved31_31_MASK                             0x80000000

/// GMMx2814
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSENABLE:1 ; ///<
    UINT32                                                 Reserved:4 ; ///<
    UINT32                                            BASEADDR21_11:11; ///<
    UINT32                                            Reserved16_18:3 ; ///<
    UINT32                                            BASEADDR38_27:12; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2814_STRUCT;

// **** GMMx2818 Register Definition ****
// Address
#define GMMx2818_ADDRESS                                        0x2818

// Type
#define GMMx2818_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2818_CSENABLE_OFFSET                                0
#define GMMx2818_CSENABLE_WIDTH                                 1
#define GMMx2818_CSENABLE_MASK                                  0x1
#define GMMx2818_Reserved_OFFSET                                1
#define GMMx2818_Reserved_WIDTH                                 4
#define GMMx2818_Reserved_MASK                                  0x1e
#define GMMx2818_BASEADDR21_11_OFFSET                           5
#define GMMx2818_BASEADDR21_11_WIDTH                            11
#define GMMx2818_BASEADDR21_11_MASK                             0xffe0
#define GMMx2818_Reserved16_18_OFFSET                           16
#define GMMx2818_Reserved16_18_WIDTH                            3
#define GMMx2818_Reserved16_18_MASK                             0x70000
#define GMMx2818_BASEADDR38_27_OFFSET                           19
#define GMMx2818_BASEADDR38_27_WIDTH                            12
#define GMMx2818_BASEADDR38_27_MASK                             0x7ff80000
#define GMMx2818_Reserved31_31_OFFSET                           31
#define GMMx2818_Reserved31_31_WIDTH                            1
#define GMMx2818_Reserved31_31_MASK                             0x80000000

/// GMMx2818
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSENABLE:1 ; ///<
    UINT32                                                 Reserved:4 ; ///<
    UINT32                                            BASEADDR21_11:11; ///<
    UINT32                                            Reserved16_18:3 ; ///<
    UINT32                                            BASEADDR38_27:12; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2818_STRUCT;

// **** GMMx281C Register Definition ****
// Address
#define GMMx281C_ADDRESS                                        0x281c

// Type
#define GMMx281C_TYPE                                           TYPE_GMM
// Field Data
#define GMMx281C_CSENABLE_OFFSET                                0
#define GMMx281C_CSENABLE_WIDTH                                 1
#define GMMx281C_CSENABLE_MASK                                  0x1
#define GMMx281C_Reserved_OFFSET                                1
#define GMMx281C_Reserved_WIDTH                                 4
#define GMMx281C_Reserved_MASK                                  0x1e
#define GMMx281C_BASEADDR21_11_OFFSET                           5
#define GMMx281C_BASEADDR21_11_WIDTH                            11
#define GMMx281C_BASEADDR21_11_MASK                             0xffe0
#define GMMx281C_Reserved16_18_OFFSET                           16
#define GMMx281C_Reserved16_18_WIDTH                            3
#define GMMx281C_Reserved16_18_MASK                             0x70000
#define GMMx281C_BASEADDR38_27_OFFSET                           19
#define GMMx281C_BASEADDR38_27_WIDTH                            12
#define GMMx281C_BASEADDR38_27_MASK                             0x7ff80000
#define GMMx281C_Reserved31_31_OFFSET                           31
#define GMMx281C_Reserved31_31_WIDTH                            1
#define GMMx281C_Reserved31_31_MASK                             0x80000000

/// GMMx281C
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSENABLE:1 ; ///<
    UINT32                                                 Reserved:4 ; ///<
    UINT32                                            BASEADDR21_11:11; ///<
    UINT32                                            Reserved16_18:3 ; ///<
    UINT32                                            BASEADDR38_27:12; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx281C_STRUCT;

// **** GMMx2820 Register Definition ****
// Address
#define GMMx2820_ADDRESS                                        0x2820

// Type
#define GMMx2820_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2820_CSENABLE_OFFSET                                0
#define GMMx2820_CSENABLE_WIDTH                                 1
#define GMMx2820_CSENABLE_MASK                                  0x1
#define GMMx2820_Reserved_OFFSET                                1
#define GMMx2820_Reserved_WIDTH                                 4
#define GMMx2820_Reserved_MASK                                  0x1e
#define GMMx2820_BASEADDR21_11_OFFSET                           5
#define GMMx2820_BASEADDR21_11_WIDTH                            11
#define GMMx2820_BASEADDR21_11_MASK                             0xffe0
#define GMMx2820_Reserved16_18_OFFSET                           16
#define GMMx2820_Reserved16_18_WIDTH                            3
#define GMMx2820_Reserved16_18_MASK                             0x70000
#define GMMx2820_BASEADDR38_27_OFFSET                           19
#define GMMx2820_BASEADDR38_27_WIDTH                            12
#define GMMx2820_BASEADDR38_27_MASK                             0x7ff80000
#define GMMx2820_Reserved31_31_OFFSET                           31
#define GMMx2820_Reserved31_31_WIDTH                            1
#define GMMx2820_Reserved31_31_MASK                             0x80000000

/// GMMx2820
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSENABLE:1 ; ///<
    UINT32                                                 Reserved:4 ; ///<
    UINT32                                            BASEADDR21_11:11; ///<
    UINT32                                            Reserved16_18:3 ; ///<
    UINT32                                            BASEADDR38_27:12; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2820_STRUCT;

// **** GMMx2824 Register Definition ****
// Address
#define GMMx2824_ADDRESS                                        0x2824

// Type
#define GMMx2824_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2824_CSENABLE_OFFSET                                0
#define GMMx2824_CSENABLE_WIDTH                                 1
#define GMMx2824_CSENABLE_MASK                                  0x1
#define GMMx2824_Reserved_OFFSET                                1
#define GMMx2824_Reserved_WIDTH                                 4
#define GMMx2824_Reserved_MASK                                  0x1e
#define GMMx2824_BASEADDR21_11_OFFSET                           5
#define GMMx2824_BASEADDR21_11_WIDTH                            11
#define GMMx2824_BASEADDR21_11_MASK                             0xffe0
#define GMMx2824_Reserved16_18_OFFSET                           16
#define GMMx2824_Reserved16_18_WIDTH                            3
#define GMMx2824_Reserved16_18_MASK                             0x70000
#define GMMx2824_BASEADDR38_27_OFFSET                           19
#define GMMx2824_BASEADDR38_27_WIDTH                            12
#define GMMx2824_BASEADDR38_27_MASK                             0x7ff80000
#define GMMx2824_Reserved31_31_OFFSET                           31
#define GMMx2824_Reserved31_31_WIDTH                            1
#define GMMx2824_Reserved31_31_MASK                             0x80000000

/// GMMx2824
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSENABLE:1 ; ///<
    UINT32                                                 Reserved:4 ; ///<
    UINT32                                            BASEADDR21_11:11; ///<
    UINT32                                            Reserved16_18:3 ; ///<
    UINT32                                            BASEADDR38_27:12; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2824_STRUCT;

// **** GMMx2828 Register Definition ****
// Address
#define GMMx2828_ADDRESS                                        0x2828

// Type
#define GMMx2828_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2828_CSENABLE_OFFSET                                0
#define GMMx2828_CSENABLE_WIDTH                                 1
#define GMMx2828_CSENABLE_MASK                                  0x1
#define GMMx2828_Reserved_OFFSET                                1
#define GMMx2828_Reserved_WIDTH                                 4
#define GMMx2828_Reserved_MASK                                  0x1e
#define GMMx2828_BASEADDR21_11_OFFSET                           5
#define GMMx2828_BASEADDR21_11_WIDTH                            11
#define GMMx2828_BASEADDR21_11_MASK                             0xffe0
#define GMMx2828_Reserved16_18_OFFSET                           16
#define GMMx2828_Reserved16_18_WIDTH                            3
#define GMMx2828_Reserved16_18_MASK                             0x70000
#define GMMx2828_BASEADDR38_27_OFFSET                           19
#define GMMx2828_BASEADDR38_27_WIDTH                            12
#define GMMx2828_BASEADDR38_27_MASK                             0x7ff80000
#define GMMx2828_Reserved31_31_OFFSET                           31
#define GMMx2828_Reserved31_31_WIDTH                            1
#define GMMx2828_Reserved31_31_MASK                             0x80000000

/// GMMx2828
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSENABLE:1 ; ///<
    UINT32                                                 Reserved:4 ; ///<
    UINT32                                            BASEADDR21_11:11; ///<
    UINT32                                            Reserved16_18:3 ; ///<
    UINT32                                            BASEADDR38_27:12; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2828_STRUCT;

// **** GMMx282C Register Definition ****
// Address
#define GMMx282C_ADDRESS                                        0x282c

// Type
#define GMMx282C_TYPE                                           TYPE_GMM
// Field Data
#define GMMx282C_CSENABLE_OFFSET                                0
#define GMMx282C_CSENABLE_WIDTH                                 1
#define GMMx282C_CSENABLE_MASK                                  0x1
#define GMMx282C_Reserved_OFFSET                                1
#define GMMx282C_Reserved_WIDTH                                 4
#define GMMx282C_Reserved_MASK                                  0x1e
#define GMMx282C_BASEADDR21_11_OFFSET                           5
#define GMMx282C_BASEADDR21_11_WIDTH                            11
#define GMMx282C_BASEADDR21_11_MASK                             0xffe0
#define GMMx282C_Reserved16_18_OFFSET                           16
#define GMMx282C_Reserved16_18_WIDTH                            3
#define GMMx282C_Reserved16_18_MASK                             0x70000
#define GMMx282C_BASEADDR38_27_OFFSET                           19
#define GMMx282C_BASEADDR38_27_WIDTH                            12
#define GMMx282C_BASEADDR38_27_MASK                             0x7ff80000
#define GMMx282C_Reserved31_31_OFFSET                           31
#define GMMx282C_Reserved31_31_WIDTH                            1
#define GMMx282C_Reserved31_31_MASK                             0x80000000

/// GMMx282C
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSENABLE:1 ; ///<
    UINT32                                                 Reserved:4 ; ///<
    UINT32                                            BASEADDR21_11:11; ///<
    UINT32                                            Reserved16_18:3 ; ///<
    UINT32                                            BASEADDR38_27:12; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx282C_STRUCT;

// **** GMMx2830 Register Definition ****
// Address
#define GMMx2830_ADDRESS                                        0x2830

// Type
#define GMMx2830_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2830_CSENABLE_OFFSET                                0
#define GMMx2830_CSENABLE_WIDTH                                 1
#define GMMx2830_CSENABLE_MASK                                  0x1
#define GMMx2830_Reserved_OFFSET                                1
#define GMMx2830_Reserved_WIDTH                                 4
#define GMMx2830_Reserved_MASK                                  0x1e
#define GMMx2830_BASEADDR21_11_OFFSET                           5
#define GMMx2830_BASEADDR21_11_WIDTH                            11
#define GMMx2830_BASEADDR21_11_MASK                             0xffe0
#define GMMx2830_Reserved16_18_OFFSET                           16
#define GMMx2830_Reserved16_18_WIDTH                            3
#define GMMx2830_Reserved16_18_MASK                             0x70000
#define GMMx2830_BASEADDR38_27_OFFSET                           19
#define GMMx2830_BASEADDR38_27_WIDTH                            12
#define GMMx2830_BASEADDR38_27_MASK                             0x7ff80000
#define GMMx2830_Reserved31_31_OFFSET                           31
#define GMMx2830_Reserved31_31_WIDTH                            1
#define GMMx2830_Reserved31_31_MASK                             0x80000000

/// GMMx2830
typedef union {
  struct {                                                              ///<
    UINT32                                                 CSENABLE:1 ; ///<
    UINT32                                                 Reserved:4 ; ///<
    UINT32                                            BASEADDR21_11:11; ///<
    UINT32                                            Reserved16_18:3 ; ///<
    UINT32                                            BASEADDR38_27:12; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2830_STRUCT;

// **** GMMx2834 Register Definition ****
// Address
#define GMMx2834_ADDRESS                                        0x2834

// Type
#define GMMx2834_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2834_Reserved_OFFSET                                0
#define GMMx2834_Reserved_WIDTH                                 5
#define GMMx2834_Reserved_MASK                                  0x1f
#define GMMx2834_ADDRMASK21_11_OFFSET                           5
#define GMMx2834_ADDRMASK21_11_WIDTH                            11
#define GMMx2834_ADDRMASK21_11_MASK                             0xffe0
#define GMMx2834_Reserved16_18_OFFSET                           16
#define GMMx2834_Reserved16_18_WIDTH                            3
#define GMMx2834_Reserved16_18_MASK                             0x70000
#define GMMx2834_ADDRMASK38_27_OFFSET                           19
#define GMMx2834_ADDRMASK38_27_WIDTH                            12
#define GMMx2834_ADDRMASK38_27_MASK                             0x7ff80000
#define GMMx2834_Reserved31_31_OFFSET                           31
#define GMMx2834_Reserved31_31_WIDTH                            1
#define GMMx2834_Reserved31_31_MASK                             0x80000000

/// GMMx2834
typedef union {
  struct {                                                              ///<
    UINT32                                                 Reserved:5 ; ///<
    UINT32                                            ADDRMASK21_11:11; ///<
    UINT32                                            Reserved16_18:3 ; ///<
    UINT32                                            ADDRMASK38_27:12; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2834_STRUCT;

// **** GMMx2838 Register Definition ****
// Address
#define GMMx2838_ADDRESS                                        0x2838

// Type
#define GMMx2838_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2838_Reserved_OFFSET                                0
#define GMMx2838_Reserved_WIDTH                                 5
#define GMMx2838_Reserved_MASK                                  0x1f
#define GMMx2838_ADDRMASK21_11_OFFSET                           5
#define GMMx2838_ADDRMASK21_11_WIDTH                            11
#define GMMx2838_ADDRMASK21_11_MASK                             0xffe0
#define GMMx2838_Reserved16_18_OFFSET                           16
#define GMMx2838_Reserved16_18_WIDTH                            3
#define GMMx2838_Reserved16_18_MASK                             0x70000
#define GMMx2838_ADDRMASK38_27_OFFSET                           19
#define GMMx2838_ADDRMASK38_27_WIDTH                            12
#define GMMx2838_ADDRMASK38_27_MASK                             0x7ff80000
#define GMMx2838_Reserved31_31_OFFSET                           31
#define GMMx2838_Reserved31_31_WIDTH                            1
#define GMMx2838_Reserved31_31_MASK                             0x80000000

/// GMMx2838
typedef union {
  struct {                                                              ///<
    UINT32                                                 Reserved:5 ; ///<
    UINT32                                            ADDRMASK21_11:11; ///<
    UINT32                                            Reserved16_18:3 ; ///<
    UINT32                                            ADDRMASK38_27:12; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2838_STRUCT;

// **** GMMx283C Register Definition ****
// Address
#define GMMx283C_ADDRESS                                        0x283c

// Type
#define GMMx283C_TYPE                                           TYPE_GMM
// Field Data
#define GMMx283C_Reserved_OFFSET                                0
#define GMMx283C_Reserved_WIDTH                                 5
#define GMMx283C_Reserved_MASK                                  0x1f
#define GMMx283C_ADDRMASK21_11_OFFSET                           5
#define GMMx283C_ADDRMASK21_11_WIDTH                            11
#define GMMx283C_ADDRMASK21_11_MASK                             0xffe0
#define GMMx283C_Reserved16_18_OFFSET                           16
#define GMMx283C_Reserved16_18_WIDTH                            3
#define GMMx283C_Reserved16_18_MASK                             0x70000
#define GMMx283C_ADDRMASK38_27_OFFSET                           19
#define GMMx283C_ADDRMASK38_27_WIDTH                            12
#define GMMx283C_ADDRMASK38_27_MASK                             0x7ff80000
#define GMMx283C_Reserved31_31_OFFSET                           31
#define GMMx283C_Reserved31_31_WIDTH                            1
#define GMMx283C_Reserved31_31_MASK                             0x80000000

/// GMMx283C
typedef union {
  struct {                                                              ///<
    UINT32                                                 Reserved:5 ; ///<
    UINT32                                            ADDRMASK21_11:11; ///<
    UINT32                                            Reserved16_18:3 ; ///<
    UINT32                                            ADDRMASK38_27:12; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx283C_STRUCT;

// **** GMMx2840 Register Definition ****
// Address
#define GMMx2840_ADDRESS                                        0x2840

// Type
#define GMMx2840_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2840_Reserved_OFFSET                                0
#define GMMx2840_Reserved_WIDTH                                 5
#define GMMx2840_Reserved_MASK                                  0x1f
#define GMMx2840_ADDRMASK21_11_OFFSET                           5
#define GMMx2840_ADDRMASK21_11_WIDTH                            11
#define GMMx2840_ADDRMASK21_11_MASK                             0xffe0
#define GMMx2840_Reserved16_18_OFFSET                           16
#define GMMx2840_Reserved16_18_WIDTH                            3
#define GMMx2840_Reserved16_18_MASK                             0x70000
#define GMMx2840_ADDRMASK38_27_OFFSET                           19
#define GMMx2840_ADDRMASK38_27_WIDTH                            12
#define GMMx2840_ADDRMASK38_27_MASK                             0x7ff80000
#define GMMx2840_Reserved31_31_OFFSET                           31
#define GMMx2840_Reserved31_31_WIDTH                            1
#define GMMx2840_Reserved31_31_MASK                             0x80000000

/// GMMx2840
typedef union {
  struct {                                                              ///<
    UINT32                                                 Reserved:5 ; ///<
    UINT32                                            ADDRMASK21_11:11; ///<
    UINT32                                            Reserved16_18:3 ; ///<
    UINT32                                            ADDRMASK38_27:12; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2840_STRUCT;

// **** GMMx2844 Register Definition ****
// Address
#define GMMx2844_ADDRESS                                        0x2844

// Type
#define GMMx2844_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2844_DIMM0ADDRMAP_OFFSET                            0
#define GMMx2844_DIMM0ADDRMAP_WIDTH                             4
#define GMMx2844_DIMM0ADDRMAP_MASK                              0xf
#define GMMx2844_DIMM1ADDRMAP_OFFSET                            4
#define GMMx2844_DIMM1ADDRMAP_WIDTH                             4
#define GMMx2844_DIMM1ADDRMAP_MASK                              0xf0
#define GMMx2844_Reserved_OFFSET                                8
#define GMMx2844_Reserved_WIDTH                                 8
#define GMMx2844_Reserved_MASK                                  0xff00
#define GMMx2844_BANKSWIZZLEMODE_OFFSET                         16
#define GMMx2844_BANKSWIZZLEMODE_WIDTH                          1
#define GMMx2844_BANKSWIZZLEMODE_MASK                           0x10000
#define GMMx2844_DDR3MODE_OFFSET                                17
#define GMMx2844_DDR3MODE_WIDTH                                 1
#define GMMx2844_DDR3MODE_MASK                                  0x20000
#define GMMx2844_BURSTLENGTH32_OFFSET                           18
#define GMMx2844_BURSTLENGTH32_WIDTH                            1
#define GMMx2844_BURSTLENGTH32_MASK                             0x40000
#define GMMx2844_BANKSWAP_OFFSET                                19
#define GMMx2844_BANKSWAP_WIDTH                                 1
#define GMMx2844_BANKSWAP_MASK                                  0x80000
#define GMMx2844_Reserved20_31_OFFSET                           20
#define GMMx2844_Reserved20_31_WIDTH                            12
#define GMMx2844_Reserved20_31_MASK                             0xfff00000

/// GMMx2844
typedef union {
  struct {                                                              ///<
    UINT32                                             DIMM0ADDRMAP:4 ; ///<
    UINT32                                             DIMM1ADDRMAP:4 ; ///<
    UINT32                                                 Reserved:8 ; ///<
    UINT32                                          BANKSWIZZLEMODE:1 ; ///<
    UINT32                                                 DDR3MODE:1 ; ///<
    UINT32                                            BURSTLENGTH32:1 ; ///<
    UINT32                                                 BANKSWAP:1 ; ///<
    UINT32                                            Reserved20_31:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2844_STRUCT;

// **** GMMx2848 Register Definition ****
// Address
#define GMMx2848_ADDRESS                                        0x2848

// Type
#define GMMx2848_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2848_DIMM0ADDRMAP_OFFSET                            0
#define GMMx2848_DIMM0ADDRMAP_WIDTH                             4
#define GMMx2848_DIMM0ADDRMAP_MASK                              0xf
#define GMMx2848_DIMM1ADDRMAP_OFFSET                            4
#define GMMx2848_DIMM1ADDRMAP_WIDTH                             4
#define GMMx2848_DIMM1ADDRMAP_MASK                              0xf0
#define GMMx2848_Reserved_OFFSET                                8
#define GMMx2848_Reserved_WIDTH                                 8
#define GMMx2848_Reserved_MASK                                  0xff00
#define GMMx2848_BANKSWIZZLEMODE_OFFSET                         16
#define GMMx2848_BANKSWIZZLEMODE_WIDTH                          1
#define GMMx2848_BANKSWIZZLEMODE_MASK                           0x10000
#define GMMx2848_DDR3MODE_OFFSET                                17
#define GMMx2848_DDR3MODE_WIDTH                                 1
#define GMMx2848_DDR3MODE_MASK                                  0x20000
#define GMMx2848_BURSTLENGTH32_OFFSET                           18
#define GMMx2848_BURSTLENGTH32_WIDTH                            1
#define GMMx2848_BURSTLENGTH32_MASK                             0x40000
#define GMMx2848_BANKSWAP_OFFSET                                19
#define GMMx2848_BANKSWAP_WIDTH                                 1
#define GMMx2848_BANKSWAP_MASK                                  0x80000
#define GMMx2848_Reserved20_31_OFFSET                           20
#define GMMx2848_Reserved20_31_WIDTH                            12
#define GMMx2848_Reserved20_31_MASK                             0xfff00000

/// GMMx2848
typedef union {
  struct {                                                              ///<
    UINT32                                             DIMM0ADDRMAP:4 ; ///<
    UINT32                                             DIMM1ADDRMAP:4 ; ///<
    UINT32                                                 Reserved:8 ; ///<
    UINT32                                          BANKSWIZZLEMODE:1 ; ///<
    UINT32                                                 DDR3MODE:1 ; ///<
    UINT32                                            BURSTLENGTH32:1 ; ///<
    UINT32                                                 BANKSWAP:1 ; ///<
    UINT32                                            Reserved20_31:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2848_STRUCT;

// **** GMMx284C Register Definition ****
// Address
#define GMMx284C_ADDRESS                                        0x284c

// Type
#define GMMx284C_TYPE                                           TYPE_GMM
// Field Data
#define GMMx284C_DCTSELHIRNGEN_OFFSET                           0
#define GMMx284C_DCTSELHIRNGEN_WIDTH                            1
#define GMMx284C_DCTSELHIRNGEN_MASK                             0x1
#define GMMx284C_DCTSELHI_OFFSET                                1
#define GMMx284C_DCTSELHI_WIDTH                                 1
#define GMMx284C_DCTSELHI_MASK                                  0x2
#define GMMx284C_DCTSELINTLVEN_OFFSET                           2
#define GMMx284C_DCTSELINTLVEN_WIDTH                            1
#define GMMx284C_DCTSELINTLVEN_MASK                             0x4
#define GMMx284C_Reserved_OFFSET                                3
#define GMMx284C_Reserved_WIDTH                                 3
#define GMMx284C_Reserved_MASK                                  0x38
#define GMMx284C_DCTSELINTLVADDR_1_0_OFFSET                     6
#define GMMx284C_DCTSELINTLVADDR_1_0_WIDTH                      2
#define GMMx284C_DCTSELINTLVADDR_1_0_MASK                       0xc0
#define GMMx284C_Reserved8_10_OFFSET                            8
#define GMMx284C_Reserved8_10_WIDTH                             3
#define GMMx284C_Reserved8_10_MASK                              0x700
#define GMMx284C_DCTSELBASEADDR39_27_OFFSET                     11
#define GMMx284C_DCTSELBASEADDR39_27_WIDTH                      13
#define GMMx284C_DCTSELBASEADDR39_27_MASK                       0xfff800
#define GMMx284C_Reserved24_31_OFFSET                           24
#define GMMx284C_Reserved24_31_WIDTH                            8
#define GMMx284C_Reserved24_31_MASK                             0xff000000

/// GMMx284C
typedef union {
  struct {                                                              ///<
    UINT32                                            DCTSELHIRNGEN:1 ; ///<
    UINT32                                                 DCTSELHI:1 ; ///<
    UINT32                                            DCTSELINTLVEN:1 ; ///<
    UINT32                                                 Reserved:3 ; ///<
    UINT32                                      DCTSELINTLVADDR_1_0:2 ; ///<
    UINT32                                             Reserved8_10:3 ; ///<
    UINT32                                      DCTSELBASEADDR39_27:13; ///<
    UINT32                                            Reserved24_31:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx284C_STRUCT;

// **** GMMx2850 Register Definition ****
// Address
#define GMMx2850_ADDRESS                                        0x2850

// Type
#define GMMx2850_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2850_Reserved_OFFSET                                0
#define GMMx2850_Reserved_WIDTH                                 9
#define GMMx2850_Reserved_MASK                                  0x1ff
#define GMMx2850_DCTSELINTLVADDR_2_OFFSET                       9
#define GMMx2850_DCTSELINTLVADDR_2_WIDTH                        1
#define GMMx2850_DCTSELINTLVADDR_2_MASK                         0x200
#define GMMx2850_DCTSELBASEOFFSET_39_26_OFFSET                  10
#define GMMx2850_DCTSELBASEOFFSET_39_26_WIDTH                   14
#define GMMx2850_DCTSELBASEOFFSET_39_26_MASK                    0xfffc00
#define GMMx2850_Reserved24_31_OFFSET                           24
#define GMMx2850_Reserved24_31_WIDTH                            8
#define GMMx2850_Reserved24_31_MASK                             0xff000000

/// GMMx2850
typedef union {
  struct {                                                              ///<
    UINT32                                                 Reserved:9 ; ///<
    UINT32                                        DCTSELINTLVADDR_2:1 ; ///<
    UINT32                                   DCTSELBASEOFFSET_39_26:14; ///<
    UINT32                                            Reserved24_31:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2850_STRUCT;

// **** GMMx2854 Register Definition ****
// Address
#define GMMx2854_ADDRESS                                        0x2854

// Type
#define GMMx2854_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2854_DRAMHOLEVALID_OFFSET                           0
#define GMMx2854_DRAMHOLEVALID_WIDTH                            1
#define GMMx2854_DRAMHOLEVALID_MASK                             0x1
#define GMMx2854_Reserved_OFFSET                                1
#define GMMx2854_Reserved_WIDTH                                 1
#define GMMx2854_Reserved_MASK                                  0x2
#define GMMx2854_DRAMHTHOLEVALID_OFFSET                         2
#define GMMx2854_DRAMHTHOLEVALID_WIDTH                          1
#define GMMx2854_DRAMHTHOLEVALID_MASK                           0x4
#define GMMx2854_Reserved3_6_OFFSET                             3
#define GMMx2854_Reserved3_6_WIDTH                              4
#define GMMx2854_Reserved3_6_MASK                               0x78
#define GMMx2854_DRAMHOLEOFFSET31_23_OFFSET                     7
#define GMMx2854_DRAMHOLEOFFSET31_23_WIDTH                      9
#define GMMx2854_DRAMHOLEOFFSET31_23_MASK                       0xff80
#define GMMx2854_Reserved16_23_OFFSET                           16
#define GMMx2854_Reserved16_23_WIDTH                            8
#define GMMx2854_Reserved16_23_MASK                             0xff0000
#define GMMx2854_DRAMHOLEBASE31_24_OFFSET                       24
#define GMMx2854_DRAMHOLEBASE31_24_WIDTH                        8
#define GMMx2854_DRAMHOLEBASE31_24_MASK                         0xff000000

/// GMMx2854
typedef union {
  struct {                                                              ///<
    UINT32                                            DRAMHOLEVALID:1 ; ///<
    UINT32                                                 Reserved:1 ; ///<
    UINT32                                          DRAMHTHOLEVALID:1 ; ///<
    UINT32                                              Reserved3_6:4 ; ///<
    UINT32                                      DRAMHOLEOFFSET31_23:9 ; ///<
    UINT32                                            Reserved16_23:8 ; ///<
    UINT32                                        DRAMHOLEBASE31_24:8 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2854_STRUCT;

// **** GMMx285C Register Definition ****
// Address
#define GMMx285C_ADDRESS                                        0x285c

// Type
#define GMMx285C_TYPE                                           TYPE_GMM
// Field Data
#define GMMx285C_INTLVRGNSWAPEN_OFFSET                          0
#define GMMx285C_INTLVRGNSWAPEN_WIDTH                           1
#define GMMx285C_INTLVRGNSWAPEN_MASK                            0x1
#define GMMx285C_Reserved_OFFSET                                1
#define GMMx285C_Reserved_WIDTH                                 2
#define GMMx285C_Reserved_MASK                                  0x6
#define GMMx285C_INTLVRGNBASEADDR33_27_OFFSET                   3
#define GMMx285C_INTLVRGNBASEADDR33_27_WIDTH                    7
#define GMMx285C_INTLVRGNBASEADDR33_27_MASK                     0x3f8
#define GMMx285C_Reserved10_10_OFFSET                           10
#define GMMx285C_Reserved10_10_WIDTH                            1
#define GMMx285C_Reserved10_10_MASK                             0x400
#define GMMx285C_INTLVRGNLMTADDR33_27_OFFSET                    11
#define GMMx285C_INTLVRGNLMTADDR33_27_WIDTH                     7
#define GMMx285C_INTLVRGNLMTADDR33_27_MASK                      0x3f800
#define GMMx285C_Reserved18_19_OFFSET                           18
#define GMMx285C_Reserved18_19_WIDTH                            2
#define GMMx285C_Reserved18_19_MASK                             0xc0000
#define GMMx285C_INTLVRGNSIZE33_27_OFFSET                       20
#define GMMx285C_INTLVRGNSIZE33_27_WIDTH                        7
#define GMMx285C_INTLVRGNSIZE33_27_MASK                         0x7f00000
#define GMMx285C_Reserved27_31_OFFSET                           27
#define GMMx285C_Reserved27_31_WIDTH                            5
#define GMMx285C_Reserved27_31_MASK                             0xf8000000

/// GMMx285C
typedef union {
  struct {                                                              ///<
    UINT32                                           INTLVRGNSWAPEN:1 ; ///<
    UINT32                                                 Reserved:2 ; ///<
    UINT32                                    INTLVRGNBASEADDR33_27:7 ; ///<
    UINT32                                            Reserved10_10:1 ; ///<
    UINT32                                     INTLVRGNLMTADDR33_27:7 ; ///<
    UINT32                                            Reserved18_19:2 ; ///<
    UINT32                                        INTLVRGNSIZE33_27:7 ; ///<
    UINT32                                            Reserved27_31:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx285C_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32                                                     BASE:20; ///<
    UINT32                                                 Reserved:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1064_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32                                                      TOP:20; ///<
    UINT32                                                 Reserved:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1065_STRUCT;

// **** GMMx2870 Register Definition ****
// Address
#define GMMx2870_ADDRESS                                        0x2870

// Type
#define GMMx2870_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2870_BASE_OFFSET                                    0
#define GMMx2870_BASE_WIDTH                                     20
#define GMMx2870_BASE_MASK                                      0xfffff
#define GMMx2870_Reserved_OFFSET                                20
#define GMMx2870_Reserved_WIDTH                                 12
#define GMMx2870_Reserved_MASK                                  0xfff00000

/// GMMx2870
typedef union {
  struct {                                                              ///<
    UINT32                                                     BASE:20; ///<
    UINT32                                                 Reserved:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2870_STRUCT;

// **** GMMx2874 Register Definition ****
// Address
#define GMMx2874_ADDRESS                                        0x2874

// Type
#define GMMx2874_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2874_TOP_OFFSET                                     0
#define GMMx2874_TOP_WIDTH                                      20
#define GMMx2874_TOP_MASK                                       0xfffff
#define GMMx2874_Reserved_OFFSET                                20
#define GMMx2874_Reserved_WIDTH                                 12
#define GMMx2874_Reserved_MASK                                  0xfff00000

/// GMMx2874
typedef union {
  struct {                                                              ///<
    UINT32                                                      TOP:20; ///<
    UINT32                                                 Reserved:12; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2874_STRUCT;


// **** GMMx287C Register Definition ****
// Address
#define GMMx287C_ADDRESS                                        0x287c

// Type
#define GMMx287C_TYPE                                           TYPE_GMM
// Field Data
#define GMMx287C_DEF_OFFSET                                     0
#define GMMx287C_DEF_WIDTH                                      28
#define GMMx287C_DEF_MASK                                       0xfffffff
#define GMMx287C_Reserved_OFFSET                                28
#define GMMx287C_Reserved_WIDTH                                 4
#define GMMx287C_Reserved_MASK                                  0xf0000000

/// GMMx287C
typedef union {
  struct {                                                              ///<
    UINT32                                                      DEF:28; ///<
    UINT32                                                 Reserved:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx287C_STRUCT;

// **** GMMx2888 Register Definition ****
// Address
#define GMMx2888_ADDRESS                                        0x2888

// Type
#define GMMx2888_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2888_NO_XBAR_OFFSET                                 0
#define GMMx2888_NO_XBAR_WIDTH                                  1
#define GMMx2888_NO_XBAR_MASK                                   0x1
#define GMMx2888_XBAR_UVD_HP_RD_OFFSET                          1
#define GMMx2888_XBAR_UVD_HP_RD_WIDTH                           1
#define GMMx2888_XBAR_UVD_HP_RD_MASK                            0x2
#define GMMx2888_XBAR_UMC_HP_RD_OFFSET                          2
#define GMMx2888_XBAR_UMC_HP_RD_WIDTH                           1
#define GMMx2888_XBAR_UMC_HP_RD_MASK                            0x4
#define GMMx2888_XBAR_VCE_HP_RD_OFFSET                          3
#define GMMx2888_XBAR_VCE_HP_RD_WIDTH                           1
#define GMMx2888_XBAR_VCE_HP_RD_MASK                            0x8
#define GMMx2888_XBAR_VCEU_HP_RD_OFFSET                         4
#define GMMx2888_XBAR_VCEU_HP_RD_WIDTH                          1
#define GMMx2888_XBAR_VCEU_HP_RD_MASK                           0x10
#define GMMx2888_XBAR_VMC_HP_RD_OFFSET                          5
#define GMMx2888_XBAR_VMC_HP_RD_WIDTH                           1
#define GMMx2888_XBAR_VMC_HP_RD_MASK                            0x20
#define GMMx2888_XBAR_DMIF_HP_RD_OFFSET                         6
#define GMMx2888_XBAR_DMIF_HP_RD_WIDTH                          1
#define GMMx2888_XBAR_DMIF_HP_RD_MASK                           0x40
#define GMMx2888_XBAR_UVD_HP_WR_OFFSET                          7
#define GMMx2888_XBAR_UVD_HP_WR_WIDTH                           1
#define GMMx2888_XBAR_UVD_HP_WR_MASK                            0x80
#define GMMx2888_XBAR_UMC_HP_WR_OFFSET                          8
#define GMMx2888_XBAR_UMC_HP_WR_WIDTH                           1
#define GMMx2888_XBAR_UMC_HP_WR_MASK                            0x100
#define GMMx2888_XBAR_VCE_HP_WR_OFFSET                          9
#define GMMx2888_XBAR_VCE_HP_WR_WIDTH                           1
#define GMMx2888_XBAR_VCE_HP_WR_MASK                            0x200
#define GMMx2888_XBAR_VCEU_HP_WR_OFFSET                         10
#define GMMx2888_XBAR_VCEU_HP_WR_WIDTH                          1
#define GMMx2888_XBAR_VCEU_HP_WR_MASK                           0x400
#define GMMx2888_Reserved_OFFSET                                11
#define GMMx2888_Reserved_WIDTH                                 21
#define GMMx2888_Reserved_MASK                                  0xfffff800

/// GMMx2888
typedef union {
  struct {                                                              ///<
    UINT32                                                  NO_XBAR:1 ; ///<
    UINT32                                           XBAR_UVD_HP_RD:1 ; ///<
    UINT32                                           XBAR_UMC_HP_RD:1 ; ///<
    UINT32                                           XBAR_VCE_HP_RD:1 ; ///<
    UINT32                                          XBAR_VCEU_HP_RD:1 ; ///<
    UINT32                                           XBAR_VMC_HP_RD:1 ; ///<
    UINT32                                          XBAR_DMIF_HP_RD:1 ; ///<
    UINT32                                           XBAR_UVD_HP_WR:1 ; ///<
    UINT32                                           XBAR_UMC_HP_WR:1 ; ///<
    UINT32                                           XBAR_VCE_HP_WR:1 ; ///<
    UINT32                                          XBAR_VCEU_HP_WR:1 ; ///<
    UINT32                                                 Reserved:21; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2888_STRUCT;


// **** GMMx28D4 Register Definition ****
// Address
#define GMMx28D4_ADDRESS                                        0x28d4

// Type
#define GMMx28D4_TYPE                                           TYPE_GMM
// Field Data
#define GMMx28D4_RENG_EXECUTE_ON_PWR_UP_OFFSET                  0
#define GMMx28D4_RENG_EXECUTE_ON_PWR_UP_WIDTH                   1
#define GMMx28D4_RENG_EXECUTE_ON_PWR_UP_MASK                    0x1
#define GMMx28D4_RENG_EXECUTE_NOW_OFFSET                        1
#define GMMx28D4_RENG_EXECUTE_NOW_WIDTH                         1
#define GMMx28D4_RENG_EXECUTE_NOW_MASK                          0x2
#define GMMx28D4_RENG_EXECUTE_NOW_START_PTR_OFFSET              2
#define GMMx28D4_RENG_EXECUTE_NOW_START_PTR_WIDTH               10
#define GMMx28D4_RENG_EXECUTE_NOW_START_PTR_MASK                0xffc
#define GMMx28D4_RENG_EXECUTE_DSP_END_PTR_OFFSET                12
#define GMMx28D4_RENG_EXECUTE_DSP_END_PTR_WIDTH                 10
#define GMMx28D4_RENG_EXECUTE_DSP_END_PTR_MASK                  0x3ff000
#define GMMx28D4_RENG_EXECUTE_END_PTR_OFFSET                    22
#define GMMx28D4_RENG_EXECUTE_END_PTR_WIDTH                     10
#define GMMx28D4_RENG_EXECUTE_END_PTR_MASK                      0xffc00000

/// GMMx28D4
typedef union {
  struct {                                                              ///<
    UINT32                                   RENG_EXECUTE_ON_PWR_UP:1 ; ///<
    UINT32                                         RENG_EXECUTE_NOW:1 ; ///<
    UINT32                               RENG_EXECUTE_NOW_START_PTR:10; ///<
    UINT32                                 RENG_EXECUTE_DSP_END_PTR:10; ///<
    UINT32                                     RENG_EXECUTE_END_PTR:10; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx28D4_STRUCT;

// **** GMMx28D8 Register Definition ****
// Address
#define GMMx28D8_ADDRESS                                        0x28d8

// Type
#define GMMx28D8_TYPE                                           TYPE_GMM
// Field Data
#define GMMx28D8_RENG_EXECUTE_NONSECURE_START_PTR_OFFSET        0
#define GMMx28D8_RENG_EXECUTE_NONSECURE_START_PTR_WIDTH         10
#define GMMx28D8_RENG_EXECUTE_NONSECURE_START_PTR_MASK          0x3ff
#define GMMx28D8_RENG_EXECUTE_NOW_MODE_OFFSET                   10
#define GMMx28D8_RENG_EXECUTE_NOW_MODE_WIDTH                    1
#define GMMx28D8_RENG_EXECUTE_NOW_MODE_MASK                     0x400
#define GMMx28D8_RENG_EXECUTE_ON_REG_UPDATE_OFFSET              11
#define GMMx28D8_RENG_EXECUTE_ON_REG_UPDATE_WIDTH               1
#define GMMx28D8_RENG_EXECUTE_ON_REG_UPDATE_MASK                0x800
#define GMMx28D8_RENG_SRBM_CREDITS_MCD_OFFSET                   12
#define GMMx28D8_RENG_SRBM_CREDITS_MCD_WIDTH                    4
#define GMMx28D8_RENG_SRBM_CREDITS_MCD_MASK                     0xf000
#define GMMx28D8_STCTRL_STUTTER_EN_OFFSET                       16
#define GMMx28D8_STCTRL_STUTTER_EN_WIDTH                        1
#define GMMx28D8_STCTRL_STUTTER_EN_MASK                         0x10000
#define GMMx28D8_STCTRL_GMC_IDLE_THRESHOLD_OFFSET               17
#define GMMx28D8_STCTRL_GMC_IDLE_THRESHOLD_WIDTH                2
#define GMMx28D8_STCTRL_GMC_IDLE_THRESHOLD_MASK                 0x60000
#define GMMx28D8_STCTRL_SRBM_IDLE_THRESHOLD_OFFSET              19
#define GMMx28D8_STCTRL_SRBM_IDLE_THRESHOLD_WIDTH               2
#define GMMx28D8_STCTRL_SRBM_IDLE_THRESHOLD_MASK                0x180000
#define GMMx28D8_STCTRL_IGNORE_PRE_SR_OFFSET                    21
#define GMMx28D8_STCTRL_IGNORE_PRE_SR_WIDTH                     1
#define GMMx28D8_STCTRL_IGNORE_PRE_SR_MASK                      0x200000
#define GMMx28D8_STCTRL_IGNORE_ALLOW_STOP_OFFSET                22
#define GMMx28D8_STCTRL_IGNORE_ALLOW_STOP_WIDTH                 1
#define GMMx28D8_STCTRL_IGNORE_ALLOW_STOP_MASK                  0x400000
#define GMMx28D8_STCTRL_IGNORE_SR_COMMIT_OFFSET                 23
#define GMMx28D8_STCTRL_IGNORE_SR_COMMIT_WIDTH                  1
#define GMMx28D8_STCTRL_IGNORE_SR_COMMIT_MASK                   0x800000
#define GMMx28D8_STCTRL_IGNORE_PROTECTION_FAULT_OFFSET          24
#define GMMx28D8_STCTRL_IGNORE_PROTECTION_FAULT_WIDTH           1
#define GMMx28D8_STCTRL_IGNORE_PROTECTION_FAULT_MASK            0x1000000
#define GMMx28D8_STCTRL_DISABLE_ALLOW_SR_OFFSET                 25
#define GMMx28D8_STCTRL_DISABLE_ALLOW_SR_WIDTH                  1
#define GMMx28D8_STCTRL_DISABLE_ALLOW_SR_MASK                   0x2000000
#define GMMx28D8_STCTRL_DISABLE_GMC_OFFLINE_OFFSET              26
#define GMMx28D8_STCTRL_DISABLE_GMC_OFFLINE_WIDTH               1
#define GMMx28D8_STCTRL_DISABLE_GMC_OFFLINE_MASK                0x4000000
#define GMMx28D8_CRITICAL_REGS_LOCK_OFFSET                      27
#define GMMx28D8_CRITICAL_REGS_LOCK_WIDTH                       1
#define GMMx28D8_CRITICAL_REGS_LOCK_MASK                        0x8000000
#define GMMx28D8_ALLOW_DEEP_SLEEP_MODE_OFFSET                   28
#define GMMx28D8_ALLOW_DEEP_SLEEP_MODE_WIDTH                    2
#define GMMx28D8_ALLOW_DEEP_SLEEP_MODE_MASK                     0x30000000
#define GMMx28D8_STCTRL_FORCE_ALLOW_SR_OFFSET                   30
#define GMMx28D8_STCTRL_FORCE_ALLOW_SR_WIDTH                    1
#define GMMx28D8_STCTRL_FORCE_ALLOW_SR_MASK                     0x40000000
#define GMMx28D8_Reserved_OFFSET                                31
#define GMMx28D8_Reserved_WIDTH                                 1
#define GMMx28D8_Reserved_MASK                                  0x80000000

/// GMMx28D8
typedef union {
  struct {                                                              ///<
    UINT32                         RENG_EXECUTE_NONSECURE_START_PTR:10; ///<
    UINT32                                    RENG_EXECUTE_NOW_MODE:1 ; ///<
    UINT32                               RENG_EXECUTE_ON_REG_UPDATE:1 ; ///<
    UINT32                                    RENG_SRBM_CREDITS_MCD:4 ; ///<
    UINT32                                        STCTRL_STUTTER_EN:1 ; ///<
    UINT32                                STCTRL_GMC_IDLE_THRESHOLD:2 ; ///<
    UINT32                               STCTRL_SRBM_IDLE_THRESHOLD:2 ; ///<
    UINT32                                     STCTRL_IGNORE_PRE_SR:1 ; ///<
    UINT32                                 STCTRL_IGNORE_ALLOW_STOP:1 ; ///<
    UINT32                                  STCTRL_IGNORE_SR_COMMIT:1 ; ///<
    UINT32                           STCTRL_IGNORE_PROTECTION_FAULT:1 ; ///<
    UINT32                                  STCTRL_DISABLE_ALLOW_SR:1 ; ///<
    UINT32                               STCTRL_DISABLE_GMC_OFFLINE:1 ; ///<
    UINT32                                       CRITICAL_REGS_LOCK:1 ; ///<
    UINT32                                    ALLOW_DEEP_SLEEP_MODE:2 ; ///<
    UINT32                                    STCTRL_FORCE_ALLOW_SR:1 ; ///<
    UINT32                                                 Reserved:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx28D8_STRUCT;

// **** GMMx2C04 Register Definition ****
// Address
#define GMMx2C04_ADDRESS                                        0x2c04

// Type
#define GMMx2C04_TYPE                                           TYPE_GMM
// Field Data
#define GMMx2C04_NONSURF_BASE_OFFSET                            0
#define GMMx2C04_NONSURF_BASE_WIDTH                             32
#define GMMx2C04_NONSURF_BASE_MASK                              0xffffffff

/// GMMx2C04
typedef union {
  struct {                                                              ///<
    UINT32                                             NONSURF_BASE:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx2C04_STRUCT;

// **** GMMx5428 Register Definition ****
// Address
#define GMMx5428_ADDRESS                                        0x5428

// Type
#define GMMx5428_TYPE                                           TYPE_GMM
// Field Data
#define GMMx5428_CONFIG_MEMSIZE_OFFSET                          0
#define GMMx5428_CONFIG_MEMSIZE_WIDTH                           32
#define GMMx5428_CONFIG_MEMSIZE_MASK                            0xffffffff

/// GMMx5428
typedef union {
  struct {                                                              ///<
    UINT32                                           CONFIG_MEMSIZE:32; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx5428_STRUCT;

// **** GMMx5490 Register Definition ****
// Address
#define GMMx5490_ADDRESS                                        0x5490

// Type
#define GMMx5490_TYPE                                           TYPE_GMM
// Field Data
#define GMMx5490_FB_READ_EN_OFFSET                              0
#define GMMx5490_FB_READ_EN_WIDTH                               1
#define GMMx5490_FB_READ_EN_MASK                                0x1
#define GMMx5490_FB_WRITE_EN_OFFSET                             1
#define GMMx5490_FB_WRITE_EN_WIDTH                              1
#define GMMx5490_FB_WRITE_EN_MASK                               0x2
#define GMMx5490_Reserved_OFFSET                                2
#define GMMx5490_Reserved_WIDTH                                 30
#define GMMx5490_Reserved_MASK                                  0xfffffffc

/// GMMx5490
typedef union {
  struct {                                                              ///<
    UINT32                                               FB_READ_EN:1 ; ///<
    UINT32                                              FB_WRITE_EN:1 ; ///<
    UINT32                                                 Reserved:30; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx5490_STRUCT;

// **** MSRC001_0010 Register Definition ****
// Address
#define MSRC001_0010_ADDRESS                                    0xc0010010

// Type
#define MSRC001_0010_TYPE                                       TYPE_MSR
// Field Data
#define MSRC001_0010_Reserved_15_0_OFFSET                       0
#define MSRC001_0010_Reserved_15_0_WIDTH                        16
#define MSRC001_0010_Reserved_15_0_MASK                         0xffff
#define MSRC001_0010_ChgToDirtyDis_OFFSET                       16
#define MSRC001_0010_ChgToDirtyDis_WIDTH                        1
#define MSRC001_0010_ChgToDirtyDis_MASK                         0x10000
#define MSRC001_0010_Reserved_17_17_OFFSET                      17
#define MSRC001_0010_Reserved_17_17_WIDTH                       1
#define MSRC001_0010_Reserved_17_17_MASK                        0x20000
#define MSRC001_0010_MtrrFixDramEn_OFFSET                       18
#define MSRC001_0010_MtrrFixDramEn_WIDTH                        1
#define MSRC001_0010_MtrrFixDramEn_MASK                         0x40000
#define MSRC001_0010_MtrrFixDramModEn_OFFSET                    19
#define MSRC001_0010_MtrrFixDramModEn_WIDTH                     1
#define MSRC001_0010_MtrrFixDramModEn_MASK                      0x80000
#define MSRC001_0010_MtrrVarDramEn_OFFSET                       20
#define MSRC001_0010_MtrrVarDramEn_WIDTH                        1
#define MSRC001_0010_MtrrVarDramEn_MASK                         0x100000
#define MSRC001_0010_MtrrTom2En_OFFSET                          21
#define MSRC001_0010_MtrrTom2En_WIDTH                           1
#define MSRC001_0010_MtrrTom2En_MASK                            0x200000
#define MSRC001_0010_Tom2ForceMemTypeWB_OFFSET                  22
#define MSRC001_0010_Tom2ForceMemTypeWB_WIDTH                   1
#define MSRC001_0010_Tom2ForceMemTypeWB_MASK                    0x400000
#define MSRC001_0010_Reserved_63_23_OFFSET                      23
#define MSRC001_0010_Reserved_63_23_WIDTH                       41
#define MSRC001_0010_Reserved_63_23_MASK                        0xffffffffff800000

/// MSRC001_0010
typedef union {
  struct {                                                              ///<
    UINT64                                            Reserved_15_0:16; ///<
    UINT64                                            ChgToDirtyDis:1 ; ///<
    UINT64                                           Reserved_17_17:1 ; ///<
    UINT64                                            MtrrFixDramEn:1 ; ///<
    UINT64                                         MtrrFixDramModEn:1 ; ///<
    UINT64                                            MtrrVarDramEn:1 ; ///<
    UINT64                                               MtrrTom2En:1 ; ///<
    UINT64                                       Tom2ForceMemTypeWB:1 ; ///<
    UINT64                                           Reserved_63_23:41; ///<
  } Field;                                                              ///<
  UINT64 Value;                                                         ///<
} MSRC001_0010_STRUCT;

// **** MSRC001_001A Register Definition ****
// Address
#define MSRC001_001A_ADDRESS                                    0xc001001a

// Type
#define MSRC001_001A_TYPE                                       TYPE_MSR
// Field Data
#define MSRC001_001A_RAZ_22_0_OFFSET                            0
#define MSRC001_001A_RAZ_22_0_WIDTH                             23
#define MSRC001_001A_RAZ_22_0_MASK                              0x7fffff
#define MSRC001_001A_TOM_47_23__OFFSET                          23
#define MSRC001_001A_TOM_47_23__WIDTH                           25
#define MSRC001_001A_TOM_47_23__MASK                            0xffffff800000
#define MSRC001_001A_RAZ_63_48_OFFSET                           48
#define MSRC001_001A_RAZ_63_48_WIDTH                            16
#define MSRC001_001A_RAZ_63_48_MASK                             0xffff000000000000

/// MSRC001_001A
typedef union {
  struct {                                                              ///<
    UINT64                                                 RAZ_22_0:23; ///<
    UINT64                                               TOM_47_23_:25; ///<
    UINT64                                                RAZ_63_48:16; ///<
  } Field;                                                              ///<
  UINT64 Value;                                                         ///<
} MSRC001_001A_STRUCT;

// **** MSRC001_001D Register Definition ****
// Address
#define MSRC001_001D_ADDRESS                                    0xc001001d

// Type
#define MSRC001_001D_TYPE                                       TYPE_MSR
// Field Data
#define MSRC001_001D_RAZ_22_0_OFFSET                            0
#define MSRC001_001D_RAZ_22_0_WIDTH                             23
#define MSRC001_001D_RAZ_22_0_MASK                              0x7fffff
#define MSRC001_001D_TOM2_47_23__OFFSET                         23
#define MSRC001_001D_TOM2_47_23__WIDTH                          25
#define MSRC001_001D_TOM2_47_23__MASK                           0xffffff800000
#define MSRC001_001D_RAZ_63_48_OFFSET                           48
#define MSRC001_001D_RAZ_63_48_WIDTH                            16
#define MSRC001_001D_RAZ_63_48_MASK                             0xffff000000000000

/// MSRC001_001D
typedef union {
  struct {                                                              ///<
    UINT64                                                 RAZ_22_0:23; ///<
    UINT64                                              TOM2_47_23_:25; ///<
    UINT64                                                RAZ_63_48:16; ///<
  } Field;                                                              ///<
  UINT64 Value;                                                         ///<
} MSRC001_001D_STRUCT;

// **** D0F0xBC_xE01040A8 Field Definition ****
// Address
#define D0F0xBC_xE01040A8_ADDRESS                               0xe01040a8

// Type
#define D0F0xBC_xE01040A8_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE01040A8_Reserved0_14_OFFSET                   0
#define D0F0xBC_xE01040A8_Reserved0_14_WIDTH                    15
#define D0F0xBC_xE01040A8_Reserved0_14_MASK                     0x7fff
#define D0F0xBC_xE01040A8_SviLoadLineVdd_OFFSET                 15
#define D0F0xBC_xE01040A8_SviLoadLineVdd_WIDTH                  7
#define D0F0xBC_xE01040A8_SviLoadLineVdd_MASK                   0x3f8000
#define D0F0xBC_xE01040A8_SviLoadLineVddNb_OFFSET               22
#define D0F0xBC_xE01040A8_SviLoadLineVddNb_WIDTH                7
#define D0F0xBC_xE01040A8_SviLoadLineVddNb_MASK                 0x1fc00000
#define D0F0xBC_xE01040A8_Reserved29_31_OFFSET                  29
#define D0F0xBC_xE01040A8_Reserved29_31_WIDTH                   3
#define D0F0xBC_xE01040A8_Reserved29_31_MASK                    0xe0000000

/// D0F0xBC_xE01040A8
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved0_14:15; ///<
    UINT32                                           SviLoadLineVdd:7 ; ///<
    UINT32                                         SviLoadLineVddNb:7 ; ///<
    UINT32                                            Reserved29_31:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE01040A8_STRUCT;

// **** D0F0xBC_xE0104158 Field Definition ****
// Address
#define D0F0xBC_xE0104158_ADDRESS                               0xe0104158

// Type
#define D0F0xBC_xE0104158_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE0104158_Reserved0_9_OFFSET                    0
#define D0F0xBC_xE0104158_Reserved0_9_WIDTH                     10
#define D0F0xBC_xE0104158_Reserved0_9_MASK                      0x3ff
#define D0F0xBC_xE0104158_EClkDid0_OFFSET                       10
#define D0F0xBC_xE0104158_EClkDid0_WIDTH                        7
#define D0F0xBC_xE0104158_EClkDid0_MASK                         0x1fc00
#define D0F0xBC_xE0104158_EClkDid1_OFFSET                       17
#define D0F0xBC_xE0104158_EClkDid1_WIDTH                        7
#define D0F0xBC_xE0104158_EClkDid1_MASK                         0xfe0000
#define D0F0xBC_xE0104158_EClkDid2_OFFSET                       24
#define D0F0xBC_xE0104158_EClkDid2_WIDTH                        7
#define D0F0xBC_xE0104158_EClkDid2_MASK                         0x7f000000
#define D0F0xBC_xE0104158_Reserved31_31_OFFSET                  31
#define D0F0xBC_xE0104158_Reserved31_31_WIDTH                   1
#define D0F0xBC_xE0104158_Reserved31_31_MASK                    0x80000000

/// D0F0xBC_xE0104158
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_9:10; ///<
    UINT32                                                 EClkDid0:7 ; ///<
    UINT32                                                 EClkDid1:7 ; ///<
    UINT32                                                 EClkDid2:7 ; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0104158_STRUCT;

// **** D0F0xBC_xE010415B Field Definition ****
// Address
#define D0F0xBC_xE010415B_ADDRESS                               0xe010415b

// Type
#define D0F0xBC_xE010415B_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE010415B_Reserved0_6_OFFSET                    0
#define D0F0xBC_xE010415B_Reserved0_6_WIDTH                     7
#define D0F0xBC_xE010415B_Reserved0_6_MASK                      0x7f
#define D0F0xBC_xE010415B_EClkDid3_OFFSET                       7
#define D0F0xBC_xE010415B_EClkDid3_WIDTH                        7
#define D0F0xBC_xE010415B_EClkDid3_MASK                         0x3f80
#define D0F0xBC_xE010415B_Reserved14_31_OFFSET                  14
#define D0F0xBC_xE010415B_Reserved14_31_WIDTH                   18
#define D0F0xBC_xE010415B_Reserved14_31_MASK                    0xffffc000

/// D0F0xBC_xE010415B
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_6:7 ; ///<
    UINT32                                                 EClkDid3:7 ; ///<
    UINT32                                            Reserved14_31:18; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE010415B_STRUCT;

// **** D0F0xBC_xE0104184 Field Definition ****
// Address
#define D0F0xBC_xE0104184_ADDRESS                               0xe0104184

// Type
#define D0F0xBC_xE0104184_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE0104184_SviLoadLineTrimVdd_OFFSET             0
#define D0F0xBC_xE0104184_SviLoadLineTrimVdd_WIDTH              3
#define D0F0xBC_xE0104184_SviLoadLineTrimVdd_MASK               0x7
#define D0F0xBC_xE0104184_SviLoadLineTrimVddNb_OFFSET           3
#define D0F0xBC_xE0104184_SviLoadLineTrimVddNb_WIDTH            3
#define D0F0xBC_xE0104184_SviLoadLineTrimVddNb_MASK             0x38
#define D0F0xBC_xE0104184_SviLoadLineOffsetVdd_OFFSET           6
#define D0F0xBC_xE0104184_SviLoadLineOffsetVdd_WIDTH            2
#define D0F0xBC_xE0104184_SviLoadLineOffsetVdd_MASK             0xc0
#define D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_OFFSET         8
#define D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_WIDTH          2
#define D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_MASK           0x300
#define D0F0xBC_xE0104184_VCEFlag0_OFFSET                       10
#define D0F0xBC_xE0104184_VCEFlag0_WIDTH                        8
#define D0F0xBC_xE0104184_VCEFlag0_MASK                         0x3fc00
#define D0F0xBC_xE0104184_VCEFlag1_OFFSET                       18
#define D0F0xBC_xE0104184_VCEFlag1_WIDTH                        8
#define D0F0xBC_xE0104184_VCEFlag1_MASK                         0x3fc0000
#define D0F0xBC_xE0104184_Reserved26_31_OFFSET                  26
#define D0F0xBC_xE0104184_Reserved26_31_WIDTH                   6
#define D0F0xBC_xE0104184_Reserved26_31_MASK                    0xfc000000

/// D0F0xBC_xE0104184
typedef union {
  struct {                                                              ///<
    UINT32                                       SviLoadLineTrimVdd:3 ; ///<
    UINT32                                     SviLoadLineTrimVddNb:3 ; ///<
    UINT32                                     SviLoadLineOffsetVdd:2 ; ///<
    UINT32                                   SviLoadLineOffsetVddNb:2 ; ///<
    UINT32                                                 VCEFlag0:8 ; ///<
    UINT32                                                 VCEFlag1:8 ; ///<
    UINT32                                            Reserved26_31:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0104184_STRUCT;

// **** D0F0xBC_xE0104187 Field Definition ****
// Address
#define D0F0xBC_xE0104187_ADDRESS                               0xe0104187

// Type
#define D0F0xBC_xE0104187_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE0104187_Reserved0_1_OFFSET                    0
#define D0F0xBC_xE0104187_Reserved0_1_WIDTH                     2
#define D0F0xBC_xE0104187_Reserved0_1_MASK                      0x3
#define D0F0xBC_xE0104187_VCEFlag2_OFFSET                       2
#define D0F0xBC_xE0104187_VCEFlag2_WIDTH                        8
#define D0F0xBC_xE0104187_VCEFlag2_MASK                         0x3fc
#define D0F0xBC_xE0104187_Reserved10_31_OFFSET                  10
#define D0F0xBC_xE0104187_Reserved10_31_WIDTH                   22
#define D0F0xBC_xE0104187_Reserved10_31_MASK                    0xfffffc00

/// D0F0xBC_xE0104187
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_1:2 ; ///<
    UINT32                                                 VCEFlag2:8 ; ///<
    UINT32                                            Reserved10_31:22; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0104187_STRUCT;

// **** D0F0xBC_xE0104188 Field Definition ****
// Address
#define D0F0xBC_xE0104188_ADDRESS                               0xe0104188

// Type
#define D0F0xBC_xE0104188_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE0104188_Reserved0_1_OFFSET                    0
#define D0F0xBC_xE0104188_Reserved0_1_WIDTH                     2
#define D0F0xBC_xE0104188_Reserved0_1_MASK                      0x3
#define D0F0xBC_xE0104188_VCEFlag3_OFFSET                       2
#define D0F0xBC_xE0104188_VCEFlag3_WIDTH                        8
#define D0F0xBC_xE0104188_VCEFlag3_MASK                         0x3fc
#define D0F0xBC_xE0104188_ReqSclkSel0_OFFSET                    10
#define D0F0xBC_xE0104188_ReqSclkSel0_WIDTH                     3
#define D0F0xBC_xE0104188_ReqSclkSel0_MASK                      0x1c00
#define D0F0xBC_xE0104188_ReqSclkSel1_OFFSET                    13
#define D0F0xBC_xE0104188_ReqSclkSel1_WIDTH                     3
#define D0F0xBC_xE0104188_ReqSclkSel1_MASK                      0xe000
#define D0F0xBC_xE0104188_ReqSclkSel2_OFFSET                    16
#define D0F0xBC_xE0104188_ReqSclkSel2_WIDTH                     3
#define D0F0xBC_xE0104188_ReqSclkSel2_MASK                      0x70000
#define D0F0xBC_xE0104188_ReqSclkSel3_OFFSET                    19
#define D0F0xBC_xE0104188_ReqSclkSel3_WIDTH                     3
#define D0F0xBC_xE0104188_ReqSclkSel3_MASK                      0x380000
#define D0F0xBC_xE0104188_VCEMclk_OFFSET                        22
#define D0F0xBC_xE0104188_VCEMclk_WIDTH                         4
#define D0F0xBC_xE0104188_VCEMclk_MASK                          0x3c00000
#define D0F0xBC_xE0104188_LhtcPstateLimit_OFFSET                26
#define D0F0xBC_xE0104188_LhtcPstateLimit_WIDTH                 3
#define D0F0xBC_xE0104188_LhtcPstateLimit_MASK                  0x1c000000
#define D0F0xBC_xE0104188_BapmMeasuredTemp_OFFSET               29
#define D0F0xBC_xE0104188_BapmMeasuredTemp_WIDTH                1
#define D0F0xBC_xE0104188_BapmMeasuredTemp_MASK                 0x20000000
#define D0F0xBC_xE0104188_BapmDisable_OFFSET                    30
#define D0F0xBC_xE0104188_BapmDisable_WIDTH                     1
#define D0F0xBC_xE0104188_BapmDisable_MASK                      0x40000000
#define D0F0xBC_xE0104188_Reserved31_31_OFFSET                  31
#define D0F0xBC_xE0104188_Reserved31_31_WIDTH                   1
#define D0F0xBC_xE0104188_Reserved31_31_MASK                    0x80000000

/// D0F0xBC_xE0104188
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_1:2 ; ///<
    UINT32                                                 VCEFlag3:8 ; ///<
    UINT32                                              ReqSclkSel0:3 ; ///<
    UINT32                                              ReqSclkSel1:3 ; ///<
    UINT32                                              ReqSclkSel2:3 ; ///<
    UINT32                                              ReqSclkSel3:3 ; ///<
    UINT32                                                  VCEMclk:4 ; ///<
    UINT32                                          LhtcPstateLimit:3 ; ///<
    UINT32                                         BapmMeasuredTemp:1 ; ///<
    UINT32                                              BapmDisable:1 ; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0104188_STRUCT;

// **** D0F0xBC_xE0106020 Field Definition ****
// Address
#define D0F0xBC_xE0106020_ADDRESS                               0xe0106020

// Type
#define D0F0xBC_xE0106020_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE0106020_Reserved0_24_OFFSET                   0
#define D0F0xBC_xE0106020_Reserved0_24_WIDTH                    25
#define D0F0xBC_xE0106020_Reserved0_24_MASK                     0x1ffffff
#define D0F0xBC_xE0106020_PowerplayDClkVClkSel0_OFFSET          25
#define D0F0xBC_xE0106020_PowerplayDClkVClkSel0_WIDTH           2
#define D0F0xBC_xE0106020_PowerplayDClkVClkSel0_MASK            0x6000000
#define D0F0xBC_xE0106020_PowerplayDClkVClkSel1_OFFSET          27
#define D0F0xBC_xE0106020_PowerplayDClkVClkSel1_WIDTH           2
#define D0F0xBC_xE0106020_PowerplayDClkVClkSel1_MASK            0x18000000
#define D0F0xBC_xE0106020_PowerplayDClkVClkSel2_OFFSET          29
#define D0F0xBC_xE0106020_PowerplayDClkVClkSel2_WIDTH           2
#define D0F0xBC_xE0106020_PowerplayDClkVClkSel2_MASK            0x60000000
#define D0F0xBC_xE0106020_Reserved31_31_OFFSET                  31
#define D0F0xBC_xE0106020_Reserved31_31_WIDTH                   1
#define D0F0xBC_xE0106020_Reserved31_31_MASK                    0x80000000

/// D0F0xBC_xE0106020
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved0_24:25; ///<
    UINT32                                    PowerplayDClkVClkSel0:2 ; ///<
    UINT32                                    PowerplayDClkVClkSel1:2 ; ///<
    UINT32                                    PowerplayDClkVClkSel2:2 ; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0106020_STRUCT;

// **** D0F0xBC_xE0106023 Field Definition ****
// Address
#define D0F0xBC_xE0106023_ADDRESS                               0xe0106023

// Type
#define D0F0xBC_xE0106023_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE0106023_Reserved0_6_OFFSET                    0
#define D0F0xBC_xE0106023_Reserved0_6_WIDTH                     7
#define D0F0xBC_xE0106023_Reserved0_6_MASK                      0x7f
#define D0F0xBC_xE0106023_PowerplayDClkVClkSel3_OFFSET          7
#define D0F0xBC_xE0106023_PowerplayDClkVClkSel3_WIDTH           2
#define D0F0xBC_xE0106023_PowerplayDClkVClkSel3_MASK            0x180
#define D0F0xBC_xE0106023_Reserved9_31_OFFSET                   9
#define D0F0xBC_xE0106023_Reserved9_31_WIDTH                    23
#define D0F0xBC_xE0106023_Reserved9_31_MASK                     0xfffffe00

/// D0F0xBC_xE0106023
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_6:7 ; ///<
    UINT32                                    PowerplayDClkVClkSel3:2 ; ///<
    UINT32                                             Reserved9_31:23; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0106023_STRUCT;

// **** D0F0xBC_xE0106024 Field Definition ****
// Address
#define D0F0xBC_xE0106024_ADDRESS                               0xe0106024

// Type
#define D0F0xBC_xE0106024_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE0106024_Reserved0_0_OFFSET                    0
#define D0F0xBC_xE0106024_Reserved0_0_WIDTH                     1
#define D0F0xBC_xE0106024_Reserved0_0_MASK                      0x1
#define D0F0xBC_xE0106024_PowerplayDClkVClkSel4_OFFSET          1
#define D0F0xBC_xE0106024_PowerplayDClkVClkSel4_WIDTH           2
#define D0F0xBC_xE0106024_PowerplayDClkVClkSel4_MASK            0x6
#define D0F0xBC_xE0106024_PowerplayDClkVClkSel5_OFFSET          3
#define D0F0xBC_xE0106024_PowerplayDClkVClkSel5_WIDTH           2
#define D0F0xBC_xE0106024_PowerplayDClkVClkSel5_MASK            0x18
#define D0F0xBC_xE0106024_Reserved5_31_OFFSET                   5
#define D0F0xBC_xE0106024_Reserved5_31_WIDTH                    27
#define D0F0xBC_xE0106024_Reserved5_31_MASK                     0xffffffe0

/// D0F0xBC_xE0106024
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_0:1 ; ///<
    UINT32                                    PowerplayDClkVClkSel4:2 ; ///<
    UINT32                                    PowerplayDClkVClkSel5:2 ; ///<
    UINT32                                             Reserved5_31:27; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0106024_STRUCT;


// **** D0F0xBC_xE010705C Field Definition ****
// Address
#define D0F0xBC_xE010705C_ADDRESS                               0xe010705c

// Type
#define D0F0xBC_xE010705C_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE010705C_Reserved0_17_OFFSET                   0
#define D0F0xBC_xE010705C_Reserved0_17_WIDTH                    18
#define D0F0xBC_xE010705C_Reserved0_17_MASK                     0x3ffff
#define D0F0xBC_xE010705C_PowerplayTableRev_OFFSET              18
#define D0F0xBC_xE010705C_PowerplayTableRev_WIDTH               4
#define D0F0xBC_xE010705C_PowerplayTableRev_MASK                0x3c0000
#define D0F0xBC_xE010705C_SClkThermDid_OFFSET                   22
#define D0F0xBC_xE010705C_SClkThermDid_WIDTH                    7
#define D0F0xBC_xE010705C_SClkThermDid_MASK                     0x1fc00000
#define D0F0xBC_xE010705C_PcieGen2Vid_OFFSET                    29
#define D0F0xBC_xE010705C_PcieGen2Vid_WIDTH                     2
#define D0F0xBC_xE010705C_PcieGen2Vid_MASK                      0x60000000
#define D0F0xBC_xE010705C_Reserved31_31_OFFSET                  31
#define D0F0xBC_xE010705C_Reserved31_31_WIDTH                   1
#define D0F0xBC_xE010705C_Reserved31_31_MASK                    0x80000000

/// D0F0xBC_xE010705C
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved0_17:18; ///<
    UINT32                                        PowerplayTableRev:4 ; ///<
    UINT32                                             SClkThermDid:7 ; ///<
    UINT32                                              PcieGen2Vid:2 ; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE010705C_STRUCT;

// **** D0F0xBC_xE010705F Field Definition ****
// Address
#define D0F0xBC_xE010705F_ADDRESS                               0xe010705f

// Type
#define D0F0xBC_xE010705F_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE010705F_Reserved0_6_OFFSET                    0
#define D0F0xBC_xE010705F_Reserved0_6_WIDTH                     7
#define D0F0xBC_xE010705F_Reserved0_6_MASK                      0x7f
#define D0F0xBC_xE010705F_SClkDpmVid0_OFFSET                    7
#define D0F0xBC_xE010705F_SClkDpmVid0_WIDTH                     2
#define D0F0xBC_xE010705F_SClkDpmVid0_MASK                      0x180
#define D0F0xBC_xE010705F_Reserved9_31_OFFSET                   9
#define D0F0xBC_xE010705F_Reserved9_31_WIDTH                    23
#define D0F0xBC_xE010705F_Reserved9_31_MASK                     0xfffffe00

/// D0F0xBC_xE010705F
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_6:7 ; ///<
    UINT32                                              SClkDpmVid0:2 ; ///<
    UINT32                                             Reserved9_31:23; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE010705F_STRUCT;

// **** D0F0xBC_xE0107060 Field Definition ****
// Address
#define D0F0xBC_xE0107060_ADDRESS                               0xe0107060

// Type
#define D0F0xBC_xE0107060_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE0107060_Reserved0_0_OFFSET                    0
#define D0F0xBC_xE0107060_Reserved0_0_WIDTH                     1
#define D0F0xBC_xE0107060_Reserved0_0_MASK                      0x1
#define D0F0xBC_xE0107060_SClkDpmVid1_OFFSET                    1
#define D0F0xBC_xE0107060_SClkDpmVid1_WIDTH                     2
#define D0F0xBC_xE0107060_SClkDpmVid1_MASK                      0x6
#define D0F0xBC_xE0107060_SClkDpmVid2_OFFSET                    3
#define D0F0xBC_xE0107060_SClkDpmVid2_WIDTH                     2
#define D0F0xBC_xE0107060_SClkDpmVid2_MASK                      0x18
#define D0F0xBC_xE0107060_SClkDpmVid3_OFFSET                    5
#define D0F0xBC_xE0107060_SClkDpmVid3_WIDTH                     2
#define D0F0xBC_xE0107060_SClkDpmVid3_MASK                      0x60
#define D0F0xBC_xE0107060_SClkDpmVid4_OFFSET                    7
#define D0F0xBC_xE0107060_SClkDpmVid4_WIDTH                     2
#define D0F0xBC_xE0107060_SClkDpmVid4_MASK                      0x180
#define D0F0xBC_xE0107060_SClkDpmDid0_OFFSET                    9
#define D0F0xBC_xE0107060_SClkDpmDid0_WIDTH                     7
#define D0F0xBC_xE0107060_SClkDpmDid0_MASK                      0xfe00
#define D0F0xBC_xE0107060_SClkDpmDid1_OFFSET                    16
#define D0F0xBC_xE0107060_SClkDpmDid1_WIDTH                     7
#define D0F0xBC_xE0107060_SClkDpmDid1_MASK                      0x7f0000
#define D0F0xBC_xE0107060_SClkDpmDid2_OFFSET                    23
#define D0F0xBC_xE0107060_SClkDpmDid2_WIDTH                     7
#define D0F0xBC_xE0107060_SClkDpmDid2_MASK                      0x3f800000
#define D0F0xBC_xE0107060_Reserved30_31_OFFSET                  30
#define D0F0xBC_xE0107060_Reserved30_31_WIDTH                   2
#define D0F0xBC_xE0107060_Reserved30_31_MASK                    0xc0000000

/// D0F0xBC_xE0107060
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_0:1 ; ///<
    UINT32                                              SClkDpmVid1:2 ; ///<
    UINT32                                              SClkDpmVid2:2 ; ///<
    UINT32                                              SClkDpmVid3:2 ; ///<
    UINT32                                              SClkDpmVid4:2 ; ///<
    UINT32                                              SClkDpmDid0:7 ; ///<
    UINT32                                              SClkDpmDid1:7 ; ///<
    UINT32                                              SClkDpmDid2:7 ; ///<
    UINT32                                            Reserved30_31:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0107060_STRUCT;

// **** D0F0xBC_xE0107063 Field Definition ****
// Address
#define D0F0xBC_xE0107063_ADDRESS                               0xe0107063

// Type
#define D0F0xBC_xE0107063_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE0107063_Reserved0_5_OFFSET                    0
#define D0F0xBC_xE0107063_Reserved0_5_WIDTH                     6
#define D0F0xBC_xE0107063_Reserved0_5_MASK                      0x3f
#define D0F0xBC_xE0107063_SClkDpmDid3_OFFSET                    6
#define D0F0xBC_xE0107063_SClkDpmDid3_WIDTH                     7
#define D0F0xBC_xE0107063_SClkDpmDid3_MASK                      0x1fc0
#define D0F0xBC_xE0107063_Reserved13_31_OFFSET                  13
#define D0F0xBC_xE0107063_Reserved13_31_WIDTH                   19
#define D0F0xBC_xE0107063_Reserved13_31_MASK                    0xffffe000

/// D0F0xBC_xE0107063
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_5:6 ; ///<
    UINT32                                              SClkDpmDid3:7 ; ///<
    UINT32                                            Reserved13_31:19; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0107063_STRUCT;

// **** D0F0xBC_xE0107064 Field Definition ****
// Address
#define D0F0xBC_xE0107064_ADDRESS                               0xe0107064

// Type
#define D0F0xBC_xE0107064_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE0107064_Reserved0_4_OFFSET                    0
#define D0F0xBC_xE0107064_Reserved0_4_WIDTH                     5
#define D0F0xBC_xE0107064_Reserved0_4_MASK                      0x1f
#define D0F0xBC_xE0107064_SClkDpmDid4_OFFSET                    5
#define D0F0xBC_xE0107064_SClkDpmDid4_WIDTH                     7
#define D0F0xBC_xE0107064_SClkDpmDid4_MASK                      0xfe0
#define D0F0xBC_xE0107064_Reserved12_31_OFFSET                  12
#define D0F0xBC_xE0107064_Reserved12_31_WIDTH                   20
#define D0F0xBC_xE0107064_Reserved12_31_MASK                    0xfffff000

/// D0F0xBC_xE0107064
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_4:5 ; ///<
    UINT32                                              SClkDpmDid4:7 ; ///<
    UINT32                                            Reserved12_31:20; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0107064_STRUCT;

// **** D0F0xBC_xE0107067 Field Definition ****
// Address
#define D0F0xBC_xE0107067_ADDRESS                               0xe0107067

// Type
#define D0F0xBC_xE0107067_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE0107067_Reserved0_3_OFFSET                    0
#define D0F0xBC_xE0107067_Reserved0_3_WIDTH                     4
#define D0F0xBC_xE0107067_Reserved0_3_MASK                      0xf
#define D0F0xBC_xE0107067_DispClkDid0_OFFSET                    4
#define D0F0xBC_xE0107067_DispClkDid0_WIDTH                     7
#define D0F0xBC_xE0107067_DispClkDid0_MASK                      0x7f0
#define D0F0xBC_xE0107067_Reserved11_31_OFFSET                  11
#define D0F0xBC_xE0107067_Reserved11_31_WIDTH                   21
#define D0F0xBC_xE0107067_Reserved11_31_MASK                    0xfffff800

/// D0F0xBC_xE0107067
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_3:4 ; ///<
    UINT32                                              DispClkDid0:7 ; ///<
    UINT32                                            Reserved11_31:21; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0107067_STRUCT;

// **** D0F0xBC_xE0107068 Field Definition ****
// Address
#define D0F0xBC_xE0107068_ADDRESS                               0xe0107068

// Type
#define D0F0xBC_xE0107068_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE0107068_Reserved0_2_OFFSET                    0
#define D0F0xBC_xE0107068_Reserved0_2_WIDTH                     3
#define D0F0xBC_xE0107068_Reserved0_2_MASK                      0x7
#define D0F0xBC_xE0107068_DispClkDid1_OFFSET                    3
#define D0F0xBC_xE0107068_DispClkDid1_WIDTH                     7
#define D0F0xBC_xE0107068_DispClkDid1_MASK                      0x3f8
#define D0F0xBC_xE0107068_DispClkDid2_OFFSET                    10
#define D0F0xBC_xE0107068_DispClkDid2_WIDTH                     7
#define D0F0xBC_xE0107068_DispClkDid2_MASK                      0x1fc00
#define D0F0xBC_xE0107068_DispClkDid3_OFFSET                    17
#define D0F0xBC_xE0107068_DispClkDid3_WIDTH                     7
#define D0F0xBC_xE0107068_DispClkDid3_MASK                      0xfe0000
#define D0F0xBC_xE0107068_LClkDpmDid0_OFFSET                    24
#define D0F0xBC_xE0107068_LClkDpmDid0_WIDTH                     7
#define D0F0xBC_xE0107068_LClkDpmDid0_MASK                      0x7f000000
#define D0F0xBC_xE0107068_Reserved31_31_OFFSET                  31
#define D0F0xBC_xE0107068_Reserved31_31_WIDTH                   1
#define D0F0xBC_xE0107068_Reserved31_31_MASK                    0x80000000

/// D0F0xBC_xE0107068
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_2:3 ; ///<
    UINT32                                              DispClkDid1:7 ; ///<
    UINT32                                              DispClkDid2:7 ; ///<
    UINT32                                              DispClkDid3:7 ; ///<
    UINT32                                              LClkDpmDid0:7 ; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0107068_STRUCT;

// **** D0F0xBC_xE010706B Field Definition ****
// Address
#define D0F0xBC_xE010706B_ADDRESS                               0xe010706b

// Type
#define D0F0xBC_xE010706B_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE010706B_Reserved0_6_OFFSET                    0
#define D0F0xBC_xE010706B_Reserved0_6_WIDTH                     7
#define D0F0xBC_xE010706B_Reserved0_6_MASK                      0x7f
#define D0F0xBC_xE010706B_LClkDpmDid1_OFFSET                    7
#define D0F0xBC_xE010706B_LClkDpmDid1_WIDTH                     7
#define D0F0xBC_xE010706B_LClkDpmDid1_MASK                      0x3f80
#define D0F0xBC_xE010706B_Reserved14_31_OFFSET                  14
#define D0F0xBC_xE010706B_Reserved14_31_WIDTH                   18
#define D0F0xBC_xE010706B_Reserved14_31_MASK                    0xffffc000

/// D0F0xBC_xE010706B
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_6:7 ; ///<
    UINT32                                              LClkDpmDid1:7 ; ///<
    UINT32                                            Reserved14_31:18; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE010706B_STRUCT;

// **** D0F0xBC_xE010706C Field Definition ****
// Address
#define D0F0xBC_xE010706C_ADDRESS                               0xe010706c

// Type
#define D0F0xBC_xE010706C_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE010706C_Reserved0_5_OFFSET                    0
#define D0F0xBC_xE010706C_Reserved0_5_WIDTH                     6
#define D0F0xBC_xE010706C_Reserved0_5_MASK                      0x3f
#define D0F0xBC_xE010706C_LClkDpmDid2_OFFSET                    6
#define D0F0xBC_xE010706C_LClkDpmDid2_WIDTH                     7
#define D0F0xBC_xE010706C_LClkDpmDid2_MASK                      0x1fc0
#define D0F0xBC_xE010706C_LClkDpmDid3_OFFSET                    13
#define D0F0xBC_xE010706C_LClkDpmDid3_WIDTH                     7
#define D0F0xBC_xE010706C_LClkDpmDid3_MASK                      0xfe000
#define D0F0xBC_xE010706C_LClkDpmValid_OFFSET                   20
#define D0F0xBC_xE010706C_LClkDpmValid_WIDTH                    4
#define D0F0xBC_xE010706C_LClkDpmValid_MASK                     0xf00000
#define D0F0xBC_xE010706C_DClkDid0_OFFSET                       24
#define D0F0xBC_xE010706C_DClkDid0_WIDTH                        7
#define D0F0xBC_xE010706C_DClkDid0_MASK                         0x7f000000
#define D0F0xBC_xE010706C_Reserved31_31_OFFSET                  31
#define D0F0xBC_xE010706C_Reserved31_31_WIDTH                   1
#define D0F0xBC_xE010706C_Reserved31_31_MASK                    0x80000000

/// D0F0xBC_xE010706C
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_5:6 ; ///<
    UINT32                                              LClkDpmDid2:7 ; ///<
    UINT32                                              LClkDpmDid3:7 ; ///<
    UINT32                                             LClkDpmValid:4 ; ///<
    UINT32                                                 DClkDid0:7 ; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE010706C_STRUCT;

// **** D0F0xBC_xE010706F Field Definition ****
// Address
#define D0F0xBC_xE010706F_ADDRESS                               0xe010706f

// Type
#define D0F0xBC_xE010706F_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE010706F_Reserved0_6_OFFSET                    0
#define D0F0xBC_xE010706F_Reserved0_6_WIDTH                     7
#define D0F0xBC_xE010706F_Reserved0_6_MASK                      0x7f
#define D0F0xBC_xE010706F_DClkDid1_OFFSET                       7
#define D0F0xBC_xE010706F_DClkDid1_WIDTH                        7
#define D0F0xBC_xE010706F_DClkDid1_MASK                         0x3f80
#define D0F0xBC_xE010706F_Reserved14_31_OFFSET                  14
#define D0F0xBC_xE010706F_Reserved14_31_WIDTH                   18
#define D0F0xBC_xE010706F_Reserved14_31_MASK                    0xffffc000

/// D0F0xBC_xE010706F
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_6:7 ; ///<
    UINT32                                                 DClkDid1:7 ; ///<
    UINT32                                            Reserved14_31:18; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE010706F_STRUCT;

// **** D0F0xBC_xE0107070 Field Definition ****
// Address
#define D0F0xBC_xE0107070_ADDRESS                               0xe0107070

// Type
#define D0F0xBC_xE0107070_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE0107070_Reserved0_5_OFFSET                    0
#define D0F0xBC_xE0107070_Reserved0_5_WIDTH                     6
#define D0F0xBC_xE0107070_Reserved0_5_MASK                      0x3f
#define D0F0xBC_xE0107070_DClkDid2_OFFSET                       6
#define D0F0xBC_xE0107070_DClkDid2_WIDTH                        7
#define D0F0xBC_xE0107070_DClkDid2_MASK                         0x1fc0
#define D0F0xBC_xE0107070_DClkDid3_OFFSET                       13
#define D0F0xBC_xE0107070_DClkDid3_WIDTH                        7
#define D0F0xBC_xE0107070_DClkDid3_MASK                         0xfe000
#define D0F0xBC_xE0107070_VClkDid0_OFFSET                       20
#define D0F0xBC_xE0107070_VClkDid0_WIDTH                        7
#define D0F0xBC_xE0107070_VClkDid0_MASK                         0x7f00000
#define D0F0xBC_xE0107070_Reserved27_31_OFFSET                  27
#define D0F0xBC_xE0107070_Reserved27_31_WIDTH                   5
#define D0F0xBC_xE0107070_Reserved27_31_MASK                    0xf8000000

/// D0F0xBC_xE0107070
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_5:6 ; ///<
    UINT32                                                 DClkDid2:7 ; ///<
    UINT32                                                 DClkDid3:7 ; ///<
    UINT32                                                 VClkDid0:7 ; ///<
    UINT32                                            Reserved27_31:5 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0107070_STRUCT;

// **** D0F0xBC_xE0107073 Field Definition ****
// Address
#define D0F0xBC_xE0107073_ADDRESS                               0xe0107073

// Type
#define D0F0xBC_xE0107073_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE0107073_Reserved0_2_OFFSET                    0
#define D0F0xBC_xE0107073_Reserved0_2_WIDTH                     3
#define D0F0xBC_xE0107073_Reserved0_2_MASK                      0x7
#define D0F0xBC_xE0107073_VClkDid1_OFFSET                       3
#define D0F0xBC_xE0107073_VClkDid1_WIDTH                        7
#define D0F0xBC_xE0107073_VClkDid1_MASK                         0x3f8
#define D0F0xBC_xE0107073_Reserved10_31_OFFSET                  10
#define D0F0xBC_xE0107073_Reserved10_31_WIDTH                   22
#define D0F0xBC_xE0107073_Reserved10_31_MASK                    0xfffffc00

/// D0F0xBC_xE0107073
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_2:3 ; ///<
    UINT32                                                 VClkDid1:7 ; ///<
    UINT32                                            Reserved10_31:22; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0107073_STRUCT;

// **** D0F0xBC_xE0107074 Field Definition ****
// Address
#define D0F0xBC_xE0107074_ADDRESS                               0xe0107074

// Type
#define D0F0xBC_xE0107074_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE0107074_Reserved0_1_OFFSET                    0
#define D0F0xBC_xE0107074_Reserved0_1_WIDTH                     2
#define D0F0xBC_xE0107074_Reserved0_1_MASK                      0x3
#define D0F0xBC_xE0107074_VClkDid2_OFFSET                       2
#define D0F0xBC_xE0107074_VClkDid2_WIDTH                        7
#define D0F0xBC_xE0107074_VClkDid2_MASK                         0x1fc
#define D0F0xBC_xE0107074_VClkDid3_OFFSET                       9
#define D0F0xBC_xE0107074_VClkDid3_WIDTH                        7
#define D0F0xBC_xE0107074_VClkDid3_MASK                         0xfe00
#define D0F0xBC_xE0107074_PowerplaySclkDpmValid0_OFFSET         16
#define D0F0xBC_xE0107074_PowerplaySclkDpmValid0_WIDTH          5
#define D0F0xBC_xE0107074_PowerplaySclkDpmValid0_MASK           0x1f0000
#define D0F0xBC_xE0107074_PowerplaySclkDpmValid1_OFFSET         21
#define D0F0xBC_xE0107074_PowerplaySclkDpmValid1_WIDTH          5
#define D0F0xBC_xE0107074_PowerplaySclkDpmValid1_MASK           0x3e00000
#define D0F0xBC_xE0107074_PowerplaySclkDpmValid2_OFFSET         26
#define D0F0xBC_xE0107074_PowerplaySclkDpmValid2_WIDTH          5
#define D0F0xBC_xE0107074_PowerplaySclkDpmValid2_MASK           0x7c000000
#define D0F0xBC_xE0107074_Reserved31_31_OFFSET                  31
#define D0F0xBC_xE0107074_Reserved31_31_WIDTH                   1
#define D0F0xBC_xE0107074_Reserved31_31_MASK                    0x80000000

/// D0F0xBC_xE0107074
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_1:2 ; ///<
    UINT32                                                 VClkDid2:7 ; ///<
    UINT32                                                 VClkDid3:7 ; ///<
    UINT32                                   PowerplaySclkDpmValid0:5 ; ///<
    UINT32                                   PowerplaySclkDpmValid1:5 ; ///<
    UINT32                                   PowerplaySclkDpmValid2:5 ; ///<
    UINT32                                            Reserved31_31:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0107074_STRUCT;

// **** D0F0xBC_xE0107077 Field Definition ****
// Address
#define D0F0xBC_xE0107077_ADDRESS                               0xe0107077

// Type
#define D0F0xBC_xE0107077_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE0107077_Reserved0_6_OFFSET                    0
#define D0F0xBC_xE0107077_Reserved0_6_WIDTH                     7
#define D0F0xBC_xE0107077_Reserved0_6_MASK                      0x7f
#define D0F0xBC_xE0107077_PowerplaySclkDpmValid3_OFFSET         7
#define D0F0xBC_xE0107077_PowerplaySclkDpmValid3_WIDTH          5
#define D0F0xBC_xE0107077_PowerplaySclkDpmValid3_MASK           0xf80
#define D0F0xBC_xE0107077_Reserved12_31_OFFSET                  12
#define D0F0xBC_xE0107077_Reserved12_31_WIDTH                   20
#define D0F0xBC_xE0107077_Reserved12_31_MASK                    0xfffff000

/// D0F0xBC_xE0107077
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_6:7 ; ///<
    UINT32                                   PowerplaySclkDpmValid3:5 ; ///<
    UINT32                                            Reserved12_31:20; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0107077_STRUCT;

// **** D0F0xBC_xE0107078 Field Definition ****
// Address
#define D0F0xBC_xE0107078_ADDRESS                               0xe0107078

// Type
#define D0F0xBC_xE0107078_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE0107078_Reserved0_3_OFFSET                    0
#define D0F0xBC_xE0107078_Reserved0_3_WIDTH                     4
#define D0F0xBC_xE0107078_Reserved0_3_MASK                      0xf
#define D0F0xBC_xE0107078_PowerplaySclkDpmValid4_OFFSET         4
#define D0F0xBC_xE0107078_PowerplaySclkDpmValid4_WIDTH          5
#define D0F0xBC_xE0107078_PowerplaySclkDpmValid4_MASK           0x1f0
#define D0F0xBC_xE0107078_PowerplaySclkDpmValid5_OFFSET         9
#define D0F0xBC_xE0107078_PowerplaySclkDpmValid5_WIDTH          5
#define D0F0xBC_xE0107078_PowerplaySclkDpmValid5_MASK           0x3e00
#define D0F0xBC_xE0107078_PowerplayPolicyLabel0_OFFSET          14
#define D0F0xBC_xE0107078_PowerplayPolicyLabel0_WIDTH           2
#define D0F0xBC_xE0107078_PowerplayPolicyLabel0_MASK            0xc000
#define D0F0xBC_xE0107078_PowerplayPolicyLabel1_OFFSET          16
#define D0F0xBC_xE0107078_PowerplayPolicyLabel1_WIDTH           2
#define D0F0xBC_xE0107078_PowerplayPolicyLabel1_MASK            0x30000
#define D0F0xBC_xE0107078_PowerplayPolicyLabel2_OFFSET          18
#define D0F0xBC_xE0107078_PowerplayPolicyLabel2_WIDTH           2
#define D0F0xBC_xE0107078_PowerplayPolicyLabel2_MASK            0xc0000
#define D0F0xBC_xE0107078_PowerplayPolicyLabel3_OFFSET          20
#define D0F0xBC_xE0107078_PowerplayPolicyLabel3_WIDTH           2
#define D0F0xBC_xE0107078_PowerplayPolicyLabel3_MASK            0x300000
#define D0F0xBC_xE0107078_PowerplayPolicyLabel4_OFFSET          22
#define D0F0xBC_xE0107078_PowerplayPolicyLabel4_WIDTH           2
#define D0F0xBC_xE0107078_PowerplayPolicyLabel4_MASK            0xc00000
#define D0F0xBC_xE0107078_PowerplayPolicyLabel5_OFFSET          24
#define D0F0xBC_xE0107078_PowerplayPolicyLabel5_WIDTH           2
#define D0F0xBC_xE0107078_PowerplayPolicyLabel5_MASK            0x3000000
#define D0F0xBC_xE0107078_Reserved26_31_OFFSET                  26
#define D0F0xBC_xE0107078_Reserved26_31_WIDTH                   6
#define D0F0xBC_xE0107078_Reserved26_31_MASK                    0xfc000000

/// D0F0xBC_xE0107078
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_3:4 ; ///<
    UINT32                                   PowerplaySclkDpmValid4:5 ; ///<
    UINT32                                   PowerplaySclkDpmValid5:5 ; ///<
    UINT32                                    PowerplayPolicyLabel0:2 ; ///<
    UINT32                                    PowerplayPolicyLabel1:2 ; ///<
    UINT32                                    PowerplayPolicyLabel2:2 ; ///<
    UINT32                                    PowerplayPolicyLabel3:2 ; ///<
    UINT32                                    PowerplayPolicyLabel4:2 ; ///<
    UINT32                                    PowerplayPolicyLabel5:2 ; ///<
    UINT32                                            Reserved26_31:6 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE0107078_STRUCT;

// **** D0F0xBC_xE010707B Field Definition ****
// Address
#define D0F0xBC_xE010707B_ADDRESS                               0xe010707b

// Type
#define D0F0xBC_xE010707B_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE010707B_Reserved0_1_OFFSET                    0
#define D0F0xBC_xE010707B_Reserved0_1_WIDTH                     2
#define D0F0xBC_xE010707B_Reserved0_1_MASK                      0x3
#define D0F0xBC_xE010707B_PowerplayStateFlag0_OFFSET            2
#define D0F0xBC_xE010707B_PowerplayStateFlag0_WIDTH             7
#define D0F0xBC_xE010707B_PowerplayStateFlag0_MASK              0x1fc
#define D0F0xBC_xE010707B_Reserved9_31_OFFSET                   9
#define D0F0xBC_xE010707B_Reserved9_31_WIDTH                    23
#define D0F0xBC_xE010707B_Reserved9_31_MASK                     0xfffffe00

/// D0F0xBC_xE010707B
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_1:2 ; ///<
    UINT32                                      PowerplayStateFlag0:7 ; ///<
    UINT32                                             Reserved9_31:23; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE010707B_STRUCT;

// **** D0F0xBC_xE010707C Field Definition ****
// Address
#define D0F0xBC_xE010707C_ADDRESS                               0xe010707c

// Type
#define D0F0xBC_xE010707C_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE010707C_Reserved0_0_OFFSET                    0
#define D0F0xBC_xE010707C_Reserved0_0_WIDTH                     1
#define D0F0xBC_xE010707C_Reserved0_0_MASK                      0x1
#define D0F0xBC_xE010707C_PowerplayStateFlag1_OFFSET            1
#define D0F0xBC_xE010707C_PowerplayStateFlag1_WIDTH             7
#define D0F0xBC_xE010707C_PowerplayStateFlag1_MASK              0xfe
#define D0F0xBC_xE010707C_PowerplayStateFlag2_OFFSET            8
#define D0F0xBC_xE010707C_PowerplayStateFlag2_WIDTH             7
#define D0F0xBC_xE010707C_PowerplayStateFlag2_MASK              0x7f00
#define D0F0xBC_xE010707C_PowerplayStateFlag3_OFFSET            15
#define D0F0xBC_xE010707C_PowerplayStateFlag3_WIDTH             7
#define D0F0xBC_xE010707C_PowerplayStateFlag3_MASK              0x3f8000
#define D0F0xBC_xE010707C_PowerplayStateFlag4_OFFSET            22
#define D0F0xBC_xE010707C_PowerplayStateFlag4_WIDTH             7
#define D0F0xBC_xE010707C_PowerplayStateFlag4_MASK              0x1fc00000
#define D0F0xBC_xE010707C_Reserved29_31_OFFSET                  29
#define D0F0xBC_xE010707C_Reserved29_31_WIDTH                   3
#define D0F0xBC_xE010707C_Reserved29_31_MASK                    0xe0000000

/// D0F0xBC_xE010707C
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_0:1 ; ///<
    UINT32                                      PowerplayStateFlag1:7 ; ///<
    UINT32                                      PowerplayStateFlag2:7 ; ///<
    UINT32                                      PowerplayStateFlag3:7 ; ///<
    UINT32                                      PowerplayStateFlag4:7 ; ///<
    UINT32                                            Reserved29_31:3 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE010707C_STRUCT;

// **** D0F0xBC_xE010707F Field Definition ****
// Address
#define D0F0xBC_xE010707F_ADDRESS                               0xe010707f

// Type
#define D0F0xBC_xE010707F_TYPE                                  TYPE_D0F0xBC
#define D0F0xBC_xE010707F_Reserved0_4_OFFSET                    0
#define D0F0xBC_xE010707F_Reserved0_4_WIDTH                     5
#define D0F0xBC_xE010707F_Reserved0_4_MASK                      0x1f
#define D0F0xBC_xE010707F_PowerplayStateFlag5_OFFSET            5
#define D0F0xBC_xE010707F_PowerplayStateFlag5_WIDTH             7
#define D0F0xBC_xE010707F_PowerplayStateFlag5_MASK              0xfe0
#define D0F0xBC_xE010707F_Reserved12_31_OFFSET                  12
#define D0F0xBC_xE010707F_Reserved12_31_WIDTH                   20
#define D0F0xBC_xE010707F_Reserved12_31_MASK                    0xfffff000

/// D0F0xBC_xE010707F
typedef union {
  struct {                                                              ///<
    UINT32                                              Reserved0_4:5 ; ///<
    UINT32                                      PowerplayStateFlag5:7 ; ///<
    UINT32                                            Reserved12_31:20; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE010707F_STRUCT;

// **** D0F0xBC_x1F630 Register Definition ****
// Address
#define D0F0xBC_x1F630_ADDRESS                                  0x1f630

// Type
#define D0F0xBC_x1F630_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F630_RECONF_WAIT_OFFSET                       0
#define D0F0xBC_x1F630_RECONF_WAIT_WIDTH                        8
#define D0F0xBC_x1F630_RECONF_WAIT_MASK                         0xff
#define D0F0xBC_x1F630_RECONF_WRAPPER_OFFSET                    8
#define D0F0xBC_x1F630_RECONF_WRAPPER_WIDTH                     8
#define D0F0xBC_x1F630_RECONF_WRAPPER_MASK                      0x00ff00

/// D0F0xBC_x1F630
typedef union {
  struct {                                                              ///<
    UINT32                                              RECONF_WAIT:8;  ///<
    UINT32                                           RECONF_WRAPPER:8;  ///<
    UINT32                                                Reserved:16;  ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F630_STRUCT;

// **** D0F0xE4_WRAP_8012 Register Definition ****
// Address
#define D0F0xE4_WRAP_8012_ADDRESS                               0x8012

// Type
#define D0F0xE4_WRAP_8012_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET           0
#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH            6
#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK             0x3f
#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET                   6
#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH                    1
#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK                     0x40
#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET            7
#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH             1
#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK              0x80
#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET         8
#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH          6
#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK           0x3f00
#define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET                 14
#define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH                  2
#define D0F0xE4_WRAP_8012_Reserved_15_14_MASK                   0xc000
#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET         16
#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH          6
#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK           0x3f0000
#define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET                 22
#define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH                  1
#define D0F0xE4_WRAP_8012_Reserved_22_22_MASK                   0x400000
#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET          23
#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH           1
#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK            0x800000
#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET       24
#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH        6
#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK         0x3f000000
#define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET                 30
#define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH                  2
#define D0F0xE4_WRAP_8012_Reserved_31_30_MASK                   0xc0000000

/// D0F0xE4_WRAP_8012
typedef union {
  struct {                                                              ///<
    UINT32                                     Pif1xIdleGateLatency:6 ; ///<
    UINT32                                             Reserved_6_6:1 ; ///<
    UINT32                                      Pif1xIdleGateEnable:1 ; ///<
    UINT32                                   Pif1xIdleResumeLatency:6 ; ///<
    UINT32                                           Reserved_15_14:2 ; ///<
    UINT32                                   Pif2p5xIdleGateLatency:6 ; ///<
    UINT32                                           Reserved_22_22:1 ; ///<
    UINT32                                    Pif2p5xIdleGateEnable:1 ; ///<
    UINT32                                 Pif2p5xIdleResumeLatency:6 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_8012_STRUCT;

// **** D0F0xE4_WRAP_8014 Register Definition ****
// Address
#define D0F0xE4_WRAP_8014_ADDRESS                               0x8014

// Type
#define D0F0xE4_WRAP_8014_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET            0
#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH             1
#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK              0x1
#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET            1
#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH             1
#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK              0x2
#define D0F0xE4_WRAP_8014_DdiGatePifA1xEnable_OFFSET            2
#define D0F0xE4_WRAP_8014_DdiGatePifA1xEnable_WIDTH             1
#define D0F0xE4_WRAP_8014_DdiGatePifA1xEnable_MASK              0x4
#define D0F0xE4_WRAP_8014_DdiGatePifB1xEnable_OFFSET            3
#define D0F0xE4_WRAP_8014_DdiGatePifB1xEnable_WIDTH             1
#define D0F0xE4_WRAP_8014_DdiGatePifB1xEnable_MASK              0x8
#define D0F0xE4_WRAP_8014_DdiGatePifC1xEnable_OFFSET            4
#define D0F0xE4_WRAP_8014_DdiGatePifC1xEnable_WIDTH             1
#define D0F0xE4_WRAP_8014_DdiGatePifC1xEnable_MASK              0x10
#define D0F0xE4_WRAP_8014_DdiGatePifD1xEnable_OFFSET            5
#define D0F0xE4_WRAP_8014_DdiGatePifD1xEnable_WIDTH             1
#define D0F0xE4_WRAP_8014_DdiGatePifD1xEnable_MASK              0x20
#define D0F0xE4_WRAP_8014_Reserved_7_6_OFFSET                   6
#define D0F0xE4_WRAP_8014_Reserved_7_6_WIDTH                    2
#define D0F0xE4_WRAP_8014_Reserved_7_6_MASK                     0xc0
#define D0F0xE4_WRAP_8014_DdiGatePifA2p5xEnable_OFFSET          8
#define D0F0xE4_WRAP_8014_DdiGatePifA2p5xEnable_WIDTH           1
#define D0F0xE4_WRAP_8014_DdiGatePifA2p5xEnable_MASK            0x100
#define D0F0xE4_WRAP_8014_DdiGatePifB2p5xEnable_OFFSET          9
#define D0F0xE4_WRAP_8014_DdiGatePifB2p5xEnable_WIDTH           1
#define D0F0xE4_WRAP_8014_DdiGatePifB2p5xEnable_MASK            0x200
#define D0F0xE4_WRAP_8014_DdiGatePifC2p5xEnable_OFFSET          10
#define D0F0xE4_WRAP_8014_DdiGatePifC2p5xEnable_WIDTH           1
#define D0F0xE4_WRAP_8014_DdiGatePifC2p5xEnable_MASK            0x400
#define D0F0xE4_WRAP_8014_DdiGatePifD2p5xEnable_OFFSET          11
#define D0F0xE4_WRAP_8014_DdiGatePifD2p5xEnable_WIDTH           1
#define D0F0xE4_WRAP_8014_DdiGatePifD2p5xEnable_MASK            0x800
#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET           12
#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH            1
#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK             0x1000
#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_OFFSET           13
#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_WIDTH            1
#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_MASK             0x2000
#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_OFFSET           14
#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_WIDTH            1
#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_MASK             0x4000
#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_OFFSET           15
#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_WIDTH            1
#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_MASK             0x8000
#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET         16
#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH          1
#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK           0x10000
#define D0F0xE4_WRAP_8014_PcieGatePifB2p5xEnable_OFFSET         17
#define D0F0xE4_WRAP_8014_PcieGatePifB2p5xEnable_WIDTH          1
#define D0F0xE4_WRAP_8014_PcieGatePifB2p5xEnable_MASK           0x20000
#define D0F0xE4_WRAP_8014_PcieGatePifC2p5xEnable_OFFSET         18
#define D0F0xE4_WRAP_8014_PcieGatePifC2p5xEnable_WIDTH          1
#define D0F0xE4_WRAP_8014_PcieGatePifC2p5xEnable_MASK           0x40000
#define D0F0xE4_WRAP_8014_PcieGatePifD2p5xEnable_OFFSET         19
#define D0F0xE4_WRAP_8014_PcieGatePifD2p5xEnable_WIDTH          1
#define D0F0xE4_WRAP_8014_PcieGatePifD2p5xEnable_MASK           0x80000
#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET  20
#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH   1
#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK    0x100000
#define D0F0xE4_WRAP_8014_Reserved_23_21_OFFSET                 21
#define D0F0xE4_WRAP_8014_Reserved_23_21_WIDTH                  3
#define D0F0xE4_WRAP_8014_Reserved_23_21_MASK                   0xe00000
#define D0F0xE4_WRAP_8014_DdiGateDigAEnable_OFFSET              24
#define D0F0xE4_WRAP_8014_DdiGateDigAEnable_WIDTH               1
#define D0F0xE4_WRAP_8014_DdiGateDigAEnable_MASK                0x1000000
#define D0F0xE4_WRAP_8014_DdiGateDigBEnable_OFFSET              25
#define D0F0xE4_WRAP_8014_DdiGateDigBEnable_WIDTH               1
#define D0F0xE4_WRAP_8014_DdiGateDigBEnable_MASK                0x2000000
#define D0F0xE4_WRAP_8014_DdiGateDigCEnable_OFFSET              26
#define D0F0xE4_WRAP_8014_DdiGateDigCEnable_WIDTH               1
#define D0F0xE4_WRAP_8014_DdiGateDigCEnable_MASK                0x4000000
#define D0F0xE4_WRAP_8014_DdiGateDigDEnable_OFFSET              27
#define D0F0xE4_WRAP_8014_DdiGateDigDEnable_WIDTH               1
#define D0F0xE4_WRAP_8014_DdiGateDigDEnable_MASK                0x8000000
#define D0F0xE4_WRAP_8014_SpareRegRw_OFFSET                     28
#define D0F0xE4_WRAP_8014_SpareRegRw_WIDTH                      4
#define D0F0xE4_WRAP_8014_SpareRegRw_MASK                       0xf0000000

/// D0F0xE4_WRAP_8014
typedef union {
  struct {                                                              ///<
    UINT32                                      TxclkPermGateEnable:1 ; ///<
    UINT32                                      TxclkPrbsGateEnable:1 ; ///<
    UINT32                                      DdiGatePifA1xEnable:1 ; ///<
    UINT32                                      DdiGatePifB1xEnable:1 ; ///<
    UINT32                                      DdiGatePifC1xEnable:1 ; ///<
    UINT32                                      DdiGatePifD1xEnable:1 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                    DdiGatePifA2p5xEnable:1 ; ///<
    UINT32                                    DdiGatePifB2p5xEnable:1 ; ///<
    UINT32                                    DdiGatePifC2p5xEnable:1 ; ///<
    UINT32                                    DdiGatePifD2p5xEnable:1 ; ///<
    UINT32                                     PcieGatePifA1xEnable:1 ; ///<
    UINT32                                     PcieGatePifB1xEnable:1 ; ///<
    UINT32                                     PcieGatePifC1xEnable:1 ; ///<
    UINT32                                     PcieGatePifD1xEnable:1 ; ///<
    UINT32                                   PcieGatePifA2p5xEnable:1 ; ///<
    UINT32                                   PcieGatePifB2p5xEnable:1 ; ///<
    UINT32                                   PcieGatePifC2p5xEnable:1 ; ///<
    UINT32                                   PcieGatePifD2p5xEnable:1 ; ///<
    UINT32                            TxclkPermGateOnlyWhenPllPwrDn:1 ; ///<
    UINT32                                           Reserved_23_21:3 ; ///<
    UINT32                                        DdiGateDigAEnable:1 ; ///<
    UINT32                                        DdiGateDigBEnable:1 ; ///<
    UINT32                                        DdiGateDigCEnable:1 ; ///<
    UINT32                                        DdiGateDigDEnable:1 ; ///<
    UINT32                                               SpareRegRw:4 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_8014_STRUCT;

// **** D0F0xE4_WRAP_8015 Register Definition ****
// Address
#define D0F0xE4_WRAP_8015_ADDRESS                               0x8015

// Type
#define D0F0xE4_WRAP_8015_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_OFFSET          16
#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_WIDTH           6
#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_MASK            0x3f0000
#define D0F0xE4_WRAP_8015_Reserved_22_22_OFFSET                 22
#define D0F0xE4_WRAP_8015_Reserved_22_22_WIDTH                  1
#define D0F0xE4_WRAP_8015_Reserved_22_22_MASK                   0x400000
#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_OFFSET           23
#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_WIDTH            1
#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_MASK             0x800000
#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_OFFSET          24
#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_WIDTH           6
#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_MASK            0x3f000000
#define D0F0xE4_WRAP_8015_Reserved_30_30_OFFSET                 30
#define D0F0xE4_WRAP_8015_Reserved_30_30_WIDTH                  1
#define D0F0xE4_WRAP_8015_Reserved_30_30_MASK                   0x40000000
#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_OFFSET           31
#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_WIDTH            1
#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_MASK             0x80000000

/// D0F0xE4_WRAP_8015
typedef union {
  struct {                                                              ///<
    UINT32  /*                                      EnableD0StateReport*/:1 ; ///<
    UINT32  /*                                             Reserved_1_1*/:1 ; ///<
    UINT32  line477/*                               SlowRefclkThroughTxclk2p5x*/:1 ; ///<
    UINT32  line478/*                                SlowRefclkEnableTxclk2p5x*/:1 ; ///<
    UINT32  line479/*                                SlowRefclkDivideTxclk2p5x*/:2 ; ///<
    UINT32  line480/*                                 SlowRefclkBurstTxclk2p5x*/:2 ; ///<
    UINT32  /*                                             Reserved_8_8*/:1 ; ///<
    UINT32  line482/*                                  SlowRefclkLcntGateForce*/:1 ; ///<
    UINT32  line483/*                                 SlowRefclkThroughTxclk1x*/:1 ; ///<
    UINT32  line484/*                                  SlowRefclkEnableTxclk1x*/:1 ; ///<
    UINT32  line485/*                                  SlowRefclkDivideTxclk1x*/:2 ; ///<
    UINT32  line486/*                                   SlowRefclkBurstTxclk1x*/:2 ; ///<
    UINT32                                    RefclkRegsGateLatency:6 ; ///<
    UINT32                                           Reserved_22_22:1 ; ///<
    UINT32                                     RefclkRegsGateEnable:1 ; ///<
    UINT32                                    RefclkBphyGateLatency:6 ; ///<
    UINT32                                           Reserved_30_30:1 ; ///<
    UINT32                                     RefclkBphyGateEnable:1 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_8015_STRUCT;

// **** PGFSM_Delay_Reg_0 Register Definition ****
// Address

// **** GMMx670 Register Definition ****
// Address
#define GMMx670_ADDRESS                                         0x670

// Type
#define GMMx670_TYPE                                            TYPE_GMM

typedef union {
  struct {                                                              ///<
    UINT32            ex1071_0:1;
    UINT32                                             Reserved_7_1:7 ; ///<
    UINT32                                             TdpClampMode:8 ; ///<
    UINT32            ex1071_3:8;
    UINT32            ex1071_4:8;
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1071_STRUCT;



// **** GMMx600 Register Definition ****
// Address
#define GMMx600_ADDRESS                                         0x600

// Type
#define GMMx600_TYPE                                            TYPE_GMM
// Field Data
#define GMMx600_IndClkDiv_OFFSET                                0
#define GMMx600_IndClkDiv_WIDTH                                 7
#define GMMx600_IndClkDiv_MASK                                  0x7f
#define GMMx600_Reserved_7_7_OFFSET                             7
#define GMMx600_Reserved_7_7_WIDTH                              1
#define GMMx600_Reserved_7_7_MASK                               0x80
#define GMMx600_ClkDirCntlEn_OFFSET                             8
#define GMMx600_ClkDirCntlEn_WIDTH                              1
#define GMMx600_ClkDirCntlEn_MASK                               0x100
#define GMMx600_ClkDirCntlTog_OFFSET                            9
#define GMMx600_ClkDirCntlTog_WIDTH                             1
#define GMMx600_ClkDirCntlTog_MASK                              0x200
#define GMMx600_ClkDirCntlDiv_OFFSET                            10
#define GMMx600_ClkDirCntlDiv_WIDTH                             7
#define GMMx600_ClkDirCntlDiv_MASK                              0x1fc00
#define GMMx600_Reserved_31_17_OFFSET                           17
#define GMMx600_Reserved_31_17_WIDTH                            15
#define GMMx600_Reserved_31_17_MASK                             0xfffe0000

/// GMMx600
typedef union {
  struct {                                                              ///<
    UINT32                                                IndClkDiv:7 ; ///<
    UINT32                                             Reserved_7_7:1 ; ///<
    UINT32                                             ClkDirCntlEn:1 ; ///<
    UINT32                                            ClkDirCntlTog:1 ; ///<
    UINT32                                            ClkDirCntlDiv:7 ; ///<
    UINT32                                           Reserved_31_17:15; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx600_STRUCT;

// **** GMMx604 Register Definition ****
// Address
#define GMMx604_ADDRESS                                         0x604

// Type
#define GMMx604_TYPE                                            TYPE_GMM
// Field Data
#define GMMx604_SclkStatus_OFFSET                               0
#define GMMx604_SclkStatus_WIDTH                                1
#define GMMx604_SclkStatus_MASK                                 0x1
#define GMMx604_SclkForceStatus_OFFSET                          1
#define GMMx604_SclkForceStatus_WIDTH                           1
#define GMMx604_SclkForceStatus_MASK                            0x2
#define GMMx604_SclkOverclkDetect_OFFSET                        2
#define GMMx604_SclkOverclkDetect_WIDTH                         1
#define GMMx604_SclkOverclkDetect_MASK                          0x4
#define GMMx604_SclkDirCntlTogDone_OFFSET                       3
#define GMMx604_SclkDirCntlTogDone_WIDTH                        1
#define GMMx604_SclkDirCntlTogDone_MASK                         0x8
#define GMMx604_Reserved_31_4_OFFSET                            4
#define GMMx604_Reserved_31_4_WIDTH                             28
#define GMMx604_Reserved_31_4_MASK                              0xfffffff0

/// GMMx604
typedef union {
  struct {                                                              ///<
    UINT64                                               SclkStatus:1 ; ///<
    UINT64                                          SclkForceStatus:1 ; ///<
    UINT64                                        SclkOverclkDetect:1 ; ///<
    UINT64                                       SclkDirCntlTogDone:1 ; ///<
    UINT64                                            Reserved_31_4:28; ///<
  } Field;                                                              ///<
  UINT64 Value;                                                         ///<
} GMMx604_STRUCT;

// **** GMMx5F50 Register Definition ****
// Address
#define GMMx5F50_ADDRESS                                        0x5F50

// Type
#define GMMx5F50_TYPE                                           TYPE_GMM
// Field Data
#define GMMx5F50_PortConnectivity_OFFSET                        0
#define GMMx5F50_PortConnectivity_WIDTH                         3
#define GMMx5F50_PortConnectivity_MASK                          0x7
#define GMMx5F50_Reserved_3_3_OFFSET                            3
#define GMMx5F50_Reserved_3_3_WIDTH                             1
#define GMMx5F50_Reserved_3_3_MASK                              0x8
#define GMMx5F50_PortConnectivityOverrideEnable_OFFSET          4
#define GMMx5F50_PortConnectivityOverrideEnable_WIDTH           1
#define GMMx5F50_PortConnectivityOverrideEnable_MASK            0x10
#define GMMx5F50_Reserved_31_5_OFFSET                           5
#define GMMx5F50_Reserved_31_5_WIDTH                            27
#define GMMx5F50_Reserved_31_5_MASK                             0xffffffe0

/// GMMx5F50
typedef union {
  struct {                                                              ///<
    UINT32                                         PortConnectivity:3 ; ///<
    UINT32                                             Reserved_3_3:1 ; ///<
    UINT32                           PortConnectivityOverrideEnable:1 ; ///<
    UINT32                                            Reserved_31_5:27; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} GMMx5F50_STRUCT;

// **** D0F0xE4_WRAP_8020 Register Definition ****
// Address
#define D0F0xE4_WRAP_8020_ADDRESS                               0x8020

// Type
#define D0F0xE4_WRAP_8020_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8020_Reserved_0_0_OFFSET                   0
#define D0F0xE4_WRAP_8020_Reserved_0_0_WIDTH                    1
#define D0F0xE4_WRAP_8020_Reserved_0_0_MASK                     0x1
#define D0F0xE4_WRAP_8020_PrbsPcieLbSelect_OFFSET               3
#define D0F0xE4_WRAP_8020_PrbsPcieLbSelect_WIDTH                1
#define D0F0xE4_WRAP_8020_PrbsPcieLbSelect_MASK                 0x8
#define D0F0xE4_WRAP_8020_Reserved_31_5_OFFSET                  5
#define D0F0xE4_WRAP_8020_Reserved_31_5_WIDTH                   27
#define D0F0xE4_WRAP_8020_Reserved_31_5_MASK                    0xffffffe0

/// D0F0xE4_WRAP_8020
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_0_0:1 ; ///<
    UINT32                                           :2 ; ///<
    UINT32                                         PrbsPcieLbSelect:1 ; ///<
    UINT32                                         :1 ; ///<
    UINT32                                            Reserved_31_5:27; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_8020_STRUCT;

// **** D0F0xE4_WRAP_8025 Register Definition ****
// Address
#define D0F0xE4_WRAP_8025_ADDRESS                               0x8025

// Type
#define D0F0xE4_WRAP_8025_TYPE                                  TYPE_D0F0xE4
// Field Data
#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET                    0
#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_WIDTH                     3
#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK                      0x7
#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_OFFSET                    3
#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_WIDTH                     2
#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_MASK                      0x18
#define D0F0xE4_WRAP_8025_LMLinkSpeed0_OFFSET                   5
#define D0F0xE4_WRAP_8025_LMLinkSpeed0_WIDTH                    1
#define D0F0xE4_WRAP_8025_LMLinkSpeed0_MASK                     0x20
#define D0F0xE4_WRAP_8025_Reserved_7_6_OFFSET                   6
#define D0F0xE4_WRAP_8025_Reserved_7_6_WIDTH                    2
#define D0F0xE4_WRAP_8025_Reserved_7_6_MASK                     0xc0
#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET                    8
#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_WIDTH                     3
#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK                      0x700
#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_OFFSET                    11
#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_WIDTH                     2
#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_MASK                      0x1800
#define D0F0xE4_WRAP_8025_LMLinkSpeed1_OFFSET                   13
#define D0F0xE4_WRAP_8025_LMLinkSpeed1_WIDTH                    1
#define D0F0xE4_WRAP_8025_LMLinkSpeed1_MASK                     0x2000
#define D0F0xE4_WRAP_8025_Reserved_15_14_OFFSET                 14
#define D0F0xE4_WRAP_8025_Reserved_15_14_WIDTH                  2
#define D0F0xE4_WRAP_8025_Reserved_15_14_MASK                   0xc000
#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_OFFSET                    16
#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_WIDTH                     3
#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_MASK                      0x70000
#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_OFFSET                    19
#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_WIDTH                     2
#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_MASK                      0x180000
#define D0F0xE4_WRAP_8025_LMLinkSpeed2_OFFSET                   21
#define D0F0xE4_WRAP_8025_LMLinkSpeed2_WIDTH                    1
#define D0F0xE4_WRAP_8025_LMLinkSpeed2_MASK                     0x200000
#define D0F0xE4_WRAP_8025_Reserved_23_22_OFFSET                 22
#define D0F0xE4_WRAP_8025_Reserved_23_22_WIDTH                  2
#define D0F0xE4_WRAP_8025_Reserved_23_22_MASK                   0xc00000
#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_OFFSET                    24
#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_WIDTH                     3
#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_MASK                      0x7000000
#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_OFFSET                    27
#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_WIDTH                     2
#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_MASK                      0x18000000
#define D0F0xE4_WRAP_8025_LMLinkSpeed3_OFFSET                   29
#define D0F0xE4_WRAP_8025_LMLinkSpeed3_WIDTH                    1
#define D0F0xE4_WRAP_8025_LMLinkSpeed3_MASK                     0x20000000
#define D0F0xE4_WRAP_8025_Reserved_31_30_OFFSET                 30
#define D0F0xE4_WRAP_8025_Reserved_31_30_WIDTH                  2
#define D0F0xE4_WRAP_8025_Reserved_31_30_MASK                   0xc0000000

/// D0F0xE4_WRAP_8025
typedef union {
  struct {                                                              ///<
    UINT32                                              LMTxPhyCmd0:3 ; ///<
    UINT32                                              LMRxPhyCmd0:2 ; ///<
    UINT32                                             LMLinkSpeed0:1 ; ///<
    UINT32                                             Reserved_7_6:2 ; ///<
    UINT32                                              LMTxPhyCmd1:3 ; ///<
    UINT32                                              LMRxPhyCmd1:2 ; ///<
    UINT32                                             LMLinkSpeed1:1 ; ///<
    UINT32                                           Reserved_15_14:2 ; ///<
    UINT32                                              LMTxPhyCmd2:3 ; ///<
    UINT32                                              LMRxPhyCmd2:2 ; ///<
    UINT32                                             LMLinkSpeed2:1 ; ///<
    UINT32                                           Reserved_23_22:2 ; ///<
    UINT32                                              LMTxPhyCmd3:3 ; ///<
    UINT32                                              LMRxPhyCmd3:2 ; ///<
    UINT32                                             LMLinkSpeed3:1 ; ///<
    UINT32                                           Reserved_31_30:2 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xE4_WRAP_8025_STRUCT;
typedef union {
  struct {                                                              ///<
    UINT32            ex1072_0:8;
    UINT32                                               NumDropLsb:8 ; ///<
    UINT32            ex1072_2:16;
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1072_STRUCT;

// **** D0F0xBC_x1F840 Register Definition ****
// Address
#define D0F0xBC_x1F840_ADDRESS                                  0x1f840

// Type
#define D0F0xBC_x1F840_TYPE                                     TYPE_D0F0xBC
// Field Data
#define D0F0xBC_x1F840_IddspikeOCP_OFFSET                               0
#define D0F0xBC_x1F840_IddspikeOCP_WIDTH                                16
#define D0F0xBC_x1F840_IddspikeOCP_MASK                                 0xffff
#define D0F0xBC_x1F840_IddNbspikeOCP_OFFSET                             16
#define D0F0xBC_x1F840_IddNbspikeOCP_WIDTH                              16
#define D0F0xBC_x1F840_IddNbspikeOCP_MASK                               0xffff0000

/// D0F0xBC_x1F840
typedef union {
  struct {                                                              ///<
    UINT32                                              IddspikeOCP:16; ///<
    UINT32                                            IddNbspikeOCP:16; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_x1F840_STRUCT;

typedef union {
  struct {                                                              ///<
    UINT32            ex1073_0:32;
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1073_STRUCT;

// **** D0F0xBC_xE010703C Register Definition ****
// Address
#define D0F0xBC_xE010703C_ADDRESS                               0xe010703c

// Type
#define D0F0xBC_xE010703C_TYPE                                  TYPE_D0F0xBC
// Field Data
#define D0F0xBC_xE010703C_Reserved_2_0_OFFSET                   0
#define D0F0xBC_xE010703C_Reserved_2_0_WIDTH                    3
#define D0F0xBC_xE010703C_Reserved_2_0_MASK                     0x7
#define D0F0xBC_xE010703C_NbPstateHi_OFFSET                     3
#define D0F0xBC_xE010703C_NbPstateHi_WIDTH                      2
#define D0F0xBC_xE010703C_NbPstateHi_MASK                       0x18
#define D0F0xBC_xE010703C_NbPstateLo_OFFSET                     5
#define D0F0xBC_xE010703C_NbPstateLo_WIDTH                      2
#define D0F0xBC_xE010703C_NbPstateLo_MASK                       0x60
#define D0F0xBC_xE010703C_Reserved_31_7_OFFSET                  7
#define D0F0xBC_xE010703C_Reserved_31_7_WIDTH                   25
#define D0F0xBC_xE010703C_Reserved_31_7_MASK                    0xffffff80

/// D0F0xBC_xE010703C
typedef union {
  struct {                                                              ///<
    UINT32                                             Reserved_2_0:3 ; ///<
    UINT32                                               NbPstateHi:2 ; ///<
    UINT32                                               NbPstateLo:2 ; ///<
    UINT32                                            Reserved_31_7:25; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} D0F0xBC_xE010703C_STRUCT;



typedef union {
  struct {                                                              ///<
    UINT32            ex1075_0:11;
    UINT32                                           Reserved_31_11:21 ; ///<
  } Field;                                                              ///<
  UINT32 Value;                                                         ///<
} ex1075_STRUCT;



// Address
#define D0F0xBC_x1F480_ADDRESS                                  0x1f480

// Type
#define D0F0xBC_x1F480_TYPE                                     TYPE_D0F0xBC

#endif


